A8E/A8S Merom/GM965/PM965 BLOCK DIAGRAM CPU ... MEROM. 3,4 HOST BUS CRESTLINE GM965/PM965 11~15 X4 DMI PCI EXPRESS X1 3 3 SYSTEM

Transcription

1 E/S Merom/GM/PM LOK IGRM E Sub block iagram / OM option VI ual H. HOST US RT & TV ON LVS & INV ON VORE R SRM /MHz SYSTEM.VS &.0VS R & VTT +VO & +.VS HRGER PI ETET PROTET LO SWITH FLOWHRT VG ON US x /T Nvidia Nx series TI Mx series amera FingerPrint IS ROM LF LF LF LF VG OR US.0 TTERY TYPE SP PT X MI... R / SOIMM X IN RT FN ON. <Variant Name> SIGNL LOK GEN ISLPRGLF-T K ITE K T/P 0, ST FIR VG ON 0 ST O H Master NEW R (EUG) SIO LPN PI-E x LP, MHz TPM Module PU MEROM RESTLINE GM/PM IHM 0~, ~ PI EXPRESS X PI_US Z zalia L0 OP TP0 PHONE MI_IN M ON PU P US x SLOT.V, MHz IN R REER 0 +.V +0.VS RUS RIOH R POWER SEQENE,... R LN G RTL LN IO SW & LE P/RES 0 & T ON FN TRL MINI R x 0 SUSTeK OMPUTER IN ustom RJ,RJ ON ES THERML ONTROL NEW R 0 LOKIGRM ate:,, 00 Sheet of.0 E

2 Reset I _T_SYS SUS_ON SUS_ON +V +V +V_E +VSUS +VSUS +VSUS +.V +V +V +V +0.VS +.VS +.VS +.VS +VS +VS +VS +V_E VSUS_ON SUS_PWRG 0 E ITE PWRSW#_E PM_PWROK PM_PWRTN# E_LK_EN IH L_PWROK PWROK PM LK Gen. PM_RSMRST# Power On SWITH VRMPWRG L_PWROK PWROK SLP_S# SLP_S# SLP_S# + VRMPWRG PWROK + VRMPWRG H_PURST# LK_PWRG To E LK_PWRG asserted when both PM_SUS# and VRM_PWRG are high. Merom elay ms PU_VRON Power On Sequence +VORE heck sequence & SUSTeK OMPUTER IN PowerOn sequence ustom ES ate:,, 00 Sheet of.0

3 0 H_#[:0] H_#[:0] 0 0 H_#[:] H_REQ#[:0] H_#[:] H_REQ#[:0] T00 TPT T00 TPT H_ST#0 H_ST# H_0M# H_FERR# H_IGNNE# H_STPLK# H_INTR H_NMI H_SMI# PU PU H_# J H_#0 H_# []# S# H H_S# E H_# [0]# L H_# []# NR# E H_NR# F H_# []# L H_# []# PRI# G H_PRI# E H_# []# K H_# []# G H_# []# M H_# []# EFER# H H_EFER# F H_# []# N H_# []# RY# F H_RY# G H_# []# J H_#0 []# SY# E H_SY# E H_# []# N H_# [0]# E H_# []# P H_# []# R0# F H_R0# K +VP_PU H_# []# P H_# []# G L 0 H_IERR# R00 Ohm H_#0 []# H_# []# IERR# J H_# [0]# P H_# []# INIT# H_INIT# 0 J H_# []# P H_# []# H R H_# []# []# LOK# H H_LOK# F H_# []# M ST[0]# K H_# []# H_REQ#0 RESET# H_PURST# H H_RS#0 []# K H_REQ# REQ[0]# RS[0]# F H_RS#0 0 H_STN#0 J H_RS# STN[0]# H H_REQ# REQ[]# RS[]# F H_RS# 0 0 H_STP#0 H H_RS# STP[0]# K H_REQ# REQ[]# RS[]# G H_RS# 0 0 H_INV#0 H INV[0]# J H_REQ# REQ[]# TRY# G H_TRY# L REQ[]# G H_# H_# HIT# H_HIT# 0 N Y E H_# []# H_# []# HITM# H_HITM# K U H_# []# H_# []# P R T00 H_# []# H_#0 []# PM[0]# R W XP_PM# H_#0 []# H_# [0]# PM[]# TPT L U T00 H_# [0]# H_# []# PM[]# M Y T00 H_# []# H_# []# PM[]# TPT L U T00 H_# []# H_# []# PRY# TPT M R H_PREQ# H_# []# H_# []# PREQ# TPT P T H_TK H_# []# H_# []# TK P T H_TI H_# []# H_# []# TI P W H_TO +VP_PU H_# []# H_# []# TO T W H_TMS H_# []# H_# []# TMS R Y H_TRST# H_# []# H_#0 []# TRST# L U 0 H_R# H_#0 []# H_# [0]# R# T V R00 H_# [0]# H_# []# N W KOhm []# H_# []# 0 H_STN# L THERML % STN[]# H_# []# H_STP# M STP[]# H_# []# 0 H_INV# N H_PROHOT_S# INV[]# []# PROHOT# V GTL_REF T00 ST[]# THRM PU_THERM_ 0 THRM R00 % KOhm GTLREF PU_THERM_ 0 MIS TPT R00 % KOhm TEST 0M# FERR# THERMTRIP# R00 T00 TEST PM_THRMTRIP#,0 00 KOhm T00 TEST IGNNE# TPT F T00 0.UF/0V % T0 TEST TPT F TPT T0 TEST STPLK# TPT TEST LINT0 H LK TPT LINT LK[0] LK_PU_LK PU_SEL0 SEL[0] SMI# LK[] LK_PU_LK# PU_SEL SEL[] PU_SEL T0 SEL[] M T0 RSV TPT N Zo= ohm, 0." max SOKET T0 RSV TPT T RSV for GTLREF T0 TPT V T00 RSV TPT T0 RSV TPT T0 RSV TPT T0 RSV TPT T0 RSV TPT T0 RSV TPT F RSV0 TPT efault Strapping When Not Used +VP_PU SOKET +VP_PU []# []# []# []# []# []# []# []# Y V V V T U U [0]# Y []# W []# Y []# W []# W []# []# []# STN[]# Y STP[]# INV[]# U []# E []# [0]# []# []# []# []# 0 []# E []# F []# []# E []# [0]# []# []# F []# STN[]# E STP[]# F INV[]# 0 OMP[0] OMP[] OMP[] OMP[] PRSTP# PSLP# PWR# PWRGOO SLP# PSI# R U Y E E H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_OMP0 H_OMP H_OMP H_OMP H_STN# 0 H_STP# 0 H_INV# 0 H_STN# 0 H_STP# H_INV# R00.Ohm R00.Ohm R00.Ohm R00.Ohm omp0, connect with Zo=. ohm, make trace length shorter than 0.". omp, connect with Z0= ohm, make trace length shorter than 0.". T0 T0 TPT T0 TPT TPT H_PRSTP#,0,0 H_PSLP# 0 H_PWR# H_PWRG 0 H_PUSLP# 0 PM_PSI# XP_PM# R0.Ohm % H_PREQ# R00.Ohm % H_TI R0 % H_TO R0.Ohm % H_TMS R0 Ohm % H_R# H_TK H_TRST# R0 KOhm% R0.Ohm % R0 Ohm GN +VS H_PROHOT_S# R0 Ohm Q00 G S N00 THRO_PU 0 SUSTeK OMPUTER IN ustom ES MEROM PU () ate:, 0, 00 Sheet of.0

4 VSENSE, VSSSENSE trace at. ohm with 0 mils spacing. Place PU and P within " of PU. +V_PU 0 m ustom, 0, 00 SUSTeK OMPUTER IN MEROM PU ().0 ES ate: Sheet of H_VI H_VI0 H_VI H_VI H_VI H_VI H_VI +VORE +VP_PU +VORE +.VS +VORE 00 0.UF/V RN00 RN00 RN UF/.V PU SOKET E E E0 E E E E E E0 F F F0 F F F F F F E E0 E E E E E E0 F F0 F F F F F F0 J K M J K M N N R R T T V W F F E F E F E E G V V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 V VP VP VP VP VP VP VP VP0 VP VP VP VP VP VP VSENSE VI[0] VI[] VI[] VI[] VI[] VI[] VI[] VSSSENSE V VP VP R00 r00_h RN00 RN00 RN00 PU SOKET P E F E E E E E E E E E F F F F F F F F F G G G G H H H H J J J J K K K K L L L L M M M M N N N N P F F F F F F F E E E P P R R R R T T T T U U U U V V V V W W W W Y Y Y E E Y E E E F VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS0 VSS VSS RN00 R00 0 R00 0 RN00 VR_VI VR_VI VSSSENSE VSENSE VR_VI VR_VI VR_VI VR_VI0 VR_VI

5 +VORE for Merom 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V +VP 0 0UF/.V 0 0UF/.V 0 0UF/.V JP00 MM_OPEN_MIL 0 0UF/.V 0 0UF/.V + E00 0 0UF/.V +VP ecoupling apacitor (Place near PU) 0UF/V 0 0UF/.V + E00 0UF/V 0 0.UF/V XR 0 0UF/.V 0 0UF/.V + E00 0UF/V 0 0.UF/V XR 0 0UF/.V 0 0UF/.V 0 0.UF/V XR 0 0UF/.V 0 0UF/.V 0 0.UF/V XR 0 0UF/.V 0 0UF/.V EN-000,EN UF/V XR 0 0UF/.V 0 0.UF/V XR 00 0UF/.V 00 0UF/.V +VP_PU 0 0UF/.V 0 0uF/0V ecoupling guide from INTEL VORE uf/0v * pcs 0uF/V * pcs VP 0.uF * pcs for PU 0uF * pcs for PU VORE 0uF/0V * pcs 0uF/V * 0pcs VP 0.uF * pcs for PU 0uF * pcs for PU 0uF/0V * pcs SUSTeK OMPUTER IN PU P ES ate:,, 00 Sheet of.0

6 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

7 Layout Note: Place these High-Freq decoupling aps near the GMH Upper:hannel Layout Note: Place these aps near SO IMM 0 Layout Note: Place these aps near SO IMM 0 Higher slot: SP/TS=/ ustom, 0, 00 SUSTeK OMPUTER IN R SO-IMM.0 ES ate: Sheet of M M M M M M M M M M 0 M 0 M M M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M QS#0 M QS0 M M M M0 M QS# M QS# M QS M QS M QS M QS# M M M M M QS# M QS# M QS M QS M M M M M M M M M QS# M QS# M QS M QS +.V +VS VTT_REF +VS +.V_GMH +.V +.V 0 UF/0V 00 0.UF/V 0 UF/0V 0 UF/0V IMM R_IMM_00P /P 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q _ Q 00 0.UF/V 00 0.UF/V 00 0.UF/V R00 0KOhm 00 0.UF/V IMM R_IMM_00P V V V V V V V V V V0 V V VSP N N N N NTEST VREF GN0 GN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS NP_N NP_N 0 0.UF/V 00 0.UF/V 00 0.UF/V 00 0.UF/V 00.UF/.V 0 UF/0V 00 0.UF/V M QS#[0..] M S#, M Q[0..] OT M S#0, M RS# SS#, S_S,,,, M QS[0..] SKE SL_S,,,, OT M S# M WE# SKE SS# M S#, M M[0..] M [0..], LK# LK LK LK# M, PM_EXTTS#

8 Layout Note: Place these aps near SO IMM Layout Note: Place these aps near SO IMM Lower:hannel Lower slot: SP/TS=0/0 ES.PR ustom, 0, 00 SUSTeK OMPUTER IN R SO-IMM_TOP.0 ES ate: Sheet of M M M Q M M Q M Q M Q M Q M M Q0 M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q0 M M Q M 0 M Q M Q M Q M Q M Q M Q M M Q M M Q M Q M Q M M Q M Q M Q M Q M Q M Q M M Q M M Q M Q0 M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M 0 M Q M Q M Q M Q M Q0 M Q M Q M M Q M Q M Q M Q0 M Q M Q M Q M QS M QS# M QS#0 M QS0 M M M M0 M QS# M QS M QS# M QS M M M M M QS# M QS# M QS M QS M M M M M M M M M QS# M QS M QS# M QS +.V +.V +VS VTT_REF +.V 00 0.UF/V 00 0.UF/V 00 0.UF/V 00 0.UF/V 00 0.UF/V 00 UF/0V 00 UF/0V 0 UF/0V IMM R_IMM_00P G /P 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q _ Q IMM R_IMM_00P G V V V V V V V V V V0 V V VSP N N N N NTEST VREF GN0 GN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS NP_N NP_N + E00 00uF/.V 00.UF/.V 00 UF/0V 00 0.UF/V M S# M QS#[0..] M S#0, OT OT0 M S# M QS[0..] M WE#, M RS#, SS0# SS# S_S,,,, SKE0 M Q[0..] M [0..], SL_S,,,, SKE, M S#, M M[0:] M, PM_EXTTS#0 LK# LK LK0 LK0#

9 0.V_VTT_REF +0.V +0.V +0.V UF/V 0.UF/V 0 0.UF/V 00 0.UF/V +.V +.V R00 0KOhm % 0.V_VTT_REF_R R00 0KOhm % R0 0KOhm 00 0.UF/V +V UF/V V+ ES.ER R UF/V V- U00 LMVIVR L00 /00Mhz VTT_REF VTT_REF 00 UF/0V Layout note: Place one cap close to every pullup resistors terminated to +0.V 00 0.UF/V R0 0KOhm OT M UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V T00 TPT M RS# SS# M [0..], M S#[0..], M [0..], M S#[0..], SKE[0:], OT[0:] M, M, Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 RN000 Ohm RN000 Ohm RN000 Ohm RN000 Ohm RN000E Ohm RN000F Ohm RN000G Ohm 0 RN000H Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F Ohm RN00G Ohm 0 RN00H Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F Ohm RN00G Ohm 0 RN00H Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F Ohm RN00G Ohm 0 RN00H Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F Ohm RN00G Ohm 0 RN00H Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F Ohm RN00G Ohm 0 RN00H Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F Ohm RN00G Ohm 0 RN00H Ohm M 0 M S#0 SS# OT M 0 M S# SS0# OT0 M M 0 M M S#0 OT SS# SKE0 M M S# M M M M SKE M M M M M M SKE M S# M M M M M M M M 0 M S# M M M M M M WE# M S# SS#, M RS#, SS0# M WE#, M S#, SS# R0 Ohm SUSTeK OMPUTER IN ustom SKE ES R R TERM ate:, 0, 00 Sheet of.0

10 ustom, 0, 00 SUSTeK OMPUTER IN PM -- PU ().0 ES 0 ate: Sheet of H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_REQ#[:0] H_RS# H_# H_RS# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_REQ# H_# H_# H_#0 H_# H_# H_REQ# H_RS#0 H_# H_REQ#0 H_# H_#0 H_#0 H_# H_# H_# H_# H_#[:0] H_#0 H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_#[:] H_# H_# H_# H_REQ# H_REQ# H_# H_#0 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_PWR# H_EFER# H_ST# H_NR# H_RY# H_ST#0 H_PRI# H_R0# H_S# H_SY# H_VREF H_SOMP H_ROMP H_SOMP# H_SWING H_SWING H_SOMP# H_SOMP H_ROMP +VP +VP +VP R00.Ohm % R00.Ohm % T00 TPT 00 0.UF/V R00 KOhm % R00 R00 0 % R00.Ohm % N RESTLINE_PM G K L J K P R H0 L M N J E J E M F L G H G0 E F M M E H G M0 M W J E N H 0 N N H P K M W0 Y V G J N N W W N Y Y P M N E H Y E G J H H E E H J H J E J J G J H H F K L E H K M K H L K J0 W E G0 M E N E E W H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_0 H_ST#_ H_NR# H_PRI# H_REQ# HPLL_LK# H_PURST# HPLL_LK H_#_0 H_REQ#_ H_REQ#_ H_#_ H_#_0 H_#_0 H_#_0 H_#_0 H_#_0 H_#_0 H_#_ H_#_ H_SY# H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_EFER# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_PWR# H_RY# H_STN#_0 H_STN#_ H_STN#_ H_STN#_ H_STP#_0 H_STP#_ H_STP#_ H_STP#_ H_SOMP H_VREF H_VREF H_TRY# H_HIT# H_HITM# H_LOK# H_REQ#_0 H_REQ#_ H_REQ#_ H_#_ H_#_ H_#_ H_#_ H_SWING H_PUSLP# H_ROMP H_RS#_0 H_RS#_ H_RS#_ H_SOMP# R00 KOhm % R00 Ohm 00 0.UF/0V H_INV# H_RS#0 H_TRY# H_INV# H_INV# H_STP#0 H_STN# H_RS# H_RS# H_STN# H_STN# H_#[:0] H_STP# H_LOK# H_REQ#[:0] H_#[:] H_STN#0 H_HITM# H_INV#0 H_STP# H_HIT# H_STP# H_ST# H_SY# H_PRI# H_NR# H_R0# H_PWR# H_S# H_RY# H_EFER# H_ST#0 H_PUSLP# LK_MH_LK# LK_MH_LK H_PURST#

11 +.V PM_PRSTP#:0 will change PRSTP# buffer type from HVMOS to LVMOS,0,0 R0 KOhm R0.0KOHM R0 KOhm PM_MUSY# H_PRSTP# PM_PWROK SM_ROMP_VOH 0.UF/.V SM_ROMP_VOL 0.UF/.V,, MH_SEL0 MH_SEL MH_SEL MH_FG_ MH_FG_ MH_FG_ R M M MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 UF_PLT_RST#_,0 PM_THRMTRIP#,0 PM_PRSLPVR 0 0.0UF/V 0 0.0UF/V R.0 T0 T0 TPT TPT T0 TPT T0 TPT T0 T TPT TPT T T TPT TPT T TPT 0 0.UF/0V G L PM_EXTTS#0 L PM_EXTTS# J PWROK W 0 % V0 R N0 G THERMTRIP#:latched until RSTIN# is asserted J K K0 L0 L L L K J E 0 0 K P P R N R R M N J R M L M 0 H0 J0 K F H0 K J F G J E H W0 K0 P N N F N G J0 0 R L J E E0 K M0 M L N L N RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV S_M_ S_M_ RSV RSV RSV LVS_T#_ LVS_T_ RSV RSV0 RSV RSV RSV RSV RSV FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 PM_M_USY# PM_PRSTP# PM_EXT_TS#_0 PM_EXT_TS#_ PWROK RSTIN# THERMTRIP# PRSLPVR N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ SM_K_0 SM_K_ SM_K_ SM_K_ SM_K#_0 SM_K#_ SM_K#_ SM_K#_ SM_KE_0 SM_KE_ SM_KE_ SM_KE_ SM_S#_0 SM_S#_ SM_S#_ SM_S#_ SM_OT_0 SM_OT_ SM_OT_ SM_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF_0 SM_VREF_ PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_0 GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF SVO_TRL_LK SVO_TRL_T LK_REQ# IH_SYN# TEST_ TEST_ V V W0 W W E Y G G0 K G E H J J E L K K L R W H H K K N J N N M J N N J J M0 M J J M M LK0 LK LK LK LK0# LK# LK# LK# SM_ROMP_VOH SM_ROMP_VOL WWN +.V ual -Frequency Graphics Technology E E M K0 T N M0 H K G G0 R T TPT T TPT PM_PWROK R0 LVS_IG.KOHM T0 TV GM TV GM TV GM GM _G_GM _R_GM GM_RT_LK K GM_RT_TG RT_HSYN_GM F RT_VSYN_GM E +VS SKE0 SKE, SKE SKE SS0# SS# SS# SS#, OT0 OT OT OT R0 % R0 % LK_REF LK_REF# LK_REFSS LK_REFSS# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP T T TPT T0 TPT T TPT T TPT TPT 0 R 0KOhm R 0.UF/0V R LK0 LK LK LK LK0# LK# LK# LK# LK_MH_GPLL LK_MH_GPLL# L_LK0 L_T0 L_RST# VTT_REF 0.UF/.V L_VREF0_MH MH_IH_SYN# LK0 0.PF/0V LK0# 0 0.0UF/V +.VS LK.PF/0V LK# L_KEN_GM EI_LK_GM EI_T_GM L_V_EN_GM LVS_LKN_GM LVS_LKP_GM LVS_LKN_GM LVS_LKP_GM LVS_Y0N_GM LVS_YN_GM LVS_YN_GM LVS_Y0P_GM LVS_YP_GM LVS_YP_GM LVS_Y0N_GM LVS_YN_GM LVS_YN_GM LVS_Y0P_GM LVS_YP_GM LVS_YP_GM TV GM TV GM TV GM GM _G_GM _R_GM PM_PWROK,0 R KOhm R Ohm LK.PF/0V LK# T0 T0 T0 T0 R J0 H E E0 K0 L L N N0 E G E F G0 E0 F G E E G K F J L M P H G K J F E.KOhm LK.PF/0V LK# N RESTLINE_PM TV GM TV GM TV GM GM _G_GM _R_GM L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONSEL_0 TV_ONSEL_ RT_LUE RT_LUE# RT_GREEN RT_GREEN# RT_RE RT_RE# RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN within 00mil;.Ohm impendance PEG_OMPI PEG_OMPO PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ N M J L N T T0 U0 Y Y0 W 0 G H G G J0 L0 M U T T W W 0 Y H G H G N U U N R0 T Y W W H E H M T T N0 R U W Y Y 0 G E0 H R0 R R 0 ohm:gm 0 ohm : PM R R R R R R 0 ohm:gm 0 ohm : PM R R0 R PEG_OMP % R0.Ohm PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP +VP PIEN_RXN[:0] 0 PIEN_RXP[:0] 0 PIEN_TXN[:0] PIEN_TXP[:0] +VS R R 0KOhm 0KOhm PM_EXTTS#0 PM_EXTTS# PM_EXTTS#0 PM_EXTTS# RESTLINE_PM 0KOhm _GM _GM RT_HSYN RT_VSYN R R R R GM_RT_LK GM_RT_T Ohm RT_HSYN_GM Ohm RT_VSYN_GM R R0 R R 0 ohm : PM SUSTeK OMPUTER IN PM--R/PEG () ustom ES ate:, 0, 00 Sheet of.0

12 , 0, 00 SUSTeK OMPUTER IN PM--R bus ().0 ES ate: Sheet of M QS# M QS0 M QS M M 0 M M QS M M M M M M QS# M M M M QS M M M M M M QS0 M M QS M QS# M 0 M QS# M 0 M M M QS M QS# M M M QS# M QS M M M M QS#0 M M QS M M M M QS# M M M M QS# M QS M M M M 0 M M M M QS M M M M M M QS# M M M M QS M M M QS#0 M QS# M QS M QS M QS# M M0 M M M QS M M M0 M QS# M QS M M M QS# M QS# M M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q T0 TPT N RESTLINE_PM R W G J G0 H E W E G E0 F H G0 F0 R0 W0 T W W Y Y V T V T W V U T R E0 0 Y G0 W Y R T T Y R R R N M N0 T T N M N W F K F L T W W G Y T E H P N T H P J 0 E G0 J K H L K J J L E Y0 S_Q_0 S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_S_0 S_S_ S_S_ S_S# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_M_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# T0 TPT NE RESTLINE_PM P R E0 Y F0 F J0 J J L W0 K K K K J L J J K J0 W L K K E K E G N J0 L K L K K0 J J F H N0 G K E J R T V0 Y Y U T V 0 0 Y G G E R0 K L H J F W T0 0 K K J L E V U0 0 L K K K F V G G E G G W F E Y V Y S_Q_0 S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_S_0 S_S_ S_S_ S_S# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# M QS[0:] M RS#, M S#, M [0:], M QS#[0:] M [0:], M WE#, M RS# M QS[0:] M S#, M WE# M S#0, M Q[0:] M M[0:] M QS#[0:] M M[0..] M S#, M Q[0:] M S# M S# M S#0, M S#

13 Max: m Max: 00m Max: 0m Max: 000m TP GM.0V/W PM.0V/W V(GM) m V(PM) 0m V_XG 00m ES.ER ES.PR EN-000,EN-000 ustom,, 00 SUSTeK OMPUTER IN PM--POWER ().0 ES <Variant Name> ate: Sheet of +VGFX_ORE +.V_GMH +VP +VP +V_GMH +.V_GMH +V_XM +V_XM +.V +VGFX_ORE +V_GMH +VGFX_ORE +VP + E0 00UF/V 0.UF/0V 0.UF/0V 0 0.UF/.V POWER NG RESTLINE_PM K J J H H H F T F J W Y E E E U F G G G H H H J J U K K K K U U U0 U U U V V V V0 T V V V Y Y Y Y Y0 Y Y T Y Y Y Y T F F H H H H T J J J K K L L L L0 L T L M M M M M P P P T P P0 P U U L V W T T U R0 T W W Y F F H0 H H H P P R0 R R R R R0 H J0 N W E W T H M0 U0 V V V Y V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_SM_0 V_SM_0 V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_SM_ V_SM_ V_SM_ V_XG_NTF_ V_ V_SM_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_ V_XG_ V_XG_ V_XG_ V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_XG_ V_XG_ V_ V_XG_NTF_ V_SM_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ 0 0UF/0V UF/.V L0 /00Mhz 0.UF/.V R00 r00_h 0 UF/.V 0.UF/.V R0 r00_h R0 r00_h 0UF/0V 0 0.UF/0V L0 /00Mhz 0.UF/0V 0 0.UF/0V + E0 00uF/.V 0.UF/0V 0 0.UF/0V 0UF/0V JP0 MM_OPEN_MIL 0 0UF/0V R0 r00_h 0 0.UF/0V + E0 00uF/.V JP0 MM_OPEN_MIL 0.UF/.V 0 0UF/0V R0 r00_h UF/.V 0.UF/.V 0.UF/0V 0.UF/0V JP0 MM_OPEN_MIL 0 0.UF/0V 0UF/0V POWER NF RESTLINE_PM K P U F F H H H H J K K K L L P R R T0 T T U U U U U V V V T T U U V V F K M P R R R Y K K J J L L L M M M M P P R Y Y Y Y L L J F J K L L L M M M M P P P R R T T V V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 V_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ V_NTF_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_0 V_XM_NTF_ V_XM_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ VSS_S VSS_S VSS_S VSS_S VSS_S VSS_S V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ VSS_NTF_ V_NTF_ V_XM_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ VSS_NTF_ V_XM_NTF_ V_XM_NTF_ V_NTF_ VSS_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_ V_XM_ V_NTF_ 0 0.UF/.V

14 HIGH = LNES REVERSE +VS +.VS +VS_TV L0 +V_RT /00Mhz 0 0.UF/0V R0 NOTE:0.uF caps in.vs_xpll need to be located as edge caps within 00 mils. L0 +.V_GMH L /00Mhz /00Mhz /00Mhz R0 0 R 0.UF/0V L0 /00Mhz L0 /00Mhz R0 R 0.UF/0V L0 L0 /00Mhz ES.ER 0UF/0V +VSYN+.VS:GM GN: PM + E0 00uF/.V + E0 +.VS:GM GN: PM +.VS_PLL +.VS_PLL 00uF/.V + E0 0UF/0V 00UF/V 0.UF/0V 0.UF/0V 0 0.UF/0V 0UF/0V 0UF/0V 0UF/0V +.VS_PEGPLL +.VS_HPLL +.VS_MPLL + E0 000PF/0V 0UF/0V 00uF/.V 0.UF/0V +.VS_TXLVS +VS_TV R0 +VS G 0 0.UF/0V +.VS_TXLVS R0 R0 +VS_TV L0 /00Mhz R0 V_TX_V_LVS V_TV_ UF/.V +.VS 0.UF/0V +.VS:GM GN: PM 0UF/0V +.V:GM GN: PM +.VS:GM GN: PM 0UF/.V +.VS +VSYN +V_RT +VS G +.VS_PLL +.VS_PLL R0 +.VS_HPLL L V_HPLL +.VS_TV +.VS_MPLL M V_MPLL R +.VS_TV_R +.VS:GM V_TX_V_LVS GN: PM R V_LVS +.VS_TV +VS VSS_LVS L0 0 +.VS_Q m R K0 V_PEG_G +.VS:GM UF/0V GN: PM R 0.UF/0V K VSS_PEG_G +.VS L0 +.VS_PEGPLL U V_PEG_PLL /00Mhz Max: 00m +.V W V_SM_ V R +.V_LVS V_SM_ + U V_SM_ U +.V:GM V_SM_ U E0 0UF/0V UF/.V V_SM_ GN: PM 0.UF/0V T R 00uF/.V V_SM_ T V_SM_ T V_SM_ T V_SM_0 T +.VS V_SM_ R V_SM_NTF_ R V_SM_NTF_ UF/.V V_TV_ +.VS_TV_R +.VS_Q +.VS_PEGPLL +.V_LVS J 0 H N N U NH VSYN V_RT V_RT V G VSS G V_PLL V_PLL V_SM_K_ V_SM_K_ V_TV V_TV V_TV V_TV V_TV V_TV M V_RT L V_TV V_Q V_HPLL V_PEG_PLL J V_LVS_ H V_LVS_ POWER VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ U U U U U U U U U U T T T0 T T T T T T R R R V_X_ T V_X_ U V_X_ U V_X_ T V_X_ T V_X_ T0 V_X_NTF V_XF_ V_XF_ V_XF_ V_MI V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_TX_LVS V_HV_ V_HV_ R J0 K K J J 0 0 V_PEG_ V_PEG_ W0 V_PEG_ W V_PEG_ V V_PEG_ V0 V_RXR_MI_ V_RXR_MI_ VTTLF VTTLF VTTLF H0 H F H 0.UF/.V Max: 0m Max: 00m Max: 0m Max: 00m V_TX_V_LVS Max: 00m +VS_HV 0 UF/.V 0 0.UF/.V 0.UF/.V 0 0UF/0V EN-000,EN-000 0UF/0V R r00_h Max: 00m 0 0.UF/0V 0UF/0V Max: 0m R r00_h 0UF/0V 0.UF/0V R0 L0 Max: 0m /00Mhz +VP 0UF/0V 0.UF/.V 0 UF/.V + E0 00UF/V 0.UF/0V 0UF/0V R0 r00_h R0 + r00_h E0 00uF/.V +.VS 0UF/0V +VS +.VS +.VS R r00_h + E0 0UF/0V 00UF/V +VP +.V_GMH R L /00Mhz 0 T +VP +VP +.VS ES.ER +.VS_TV RESTLINE_PM 0.UF/.V 0.UF/.V 0 0.UF/.V R 0.UF/0V 0.UF/0V +VS L /00Mhz 0.UF/0V 0UF/.V + E0 00uF/.V +VS_TV <Variant Name> SUSTeK OMPUTER IN ustom ES PM--POWER () ate:,, 00 Sheet of.0

15 NI RESTLINE_PM MH_FG_ MH_FG_ MH_FG_ R0.KOhm R0.KOhm R0.KOhm FG : MI STRP HIGH = MI X (efault) LOW = MI X FG : PU STRP HIGH = Mobile PU (efault) LOW = Reserved FG : PIE GRPHI LNE LOW = REVERSE LNE HIGH = Normal Operation (efault) MH_FG_ MH_FG_ FG: V select LOW=.0V (default) HIGH=.V FG : MI LNE REVERSL LOW = NORML (default) HIGH = LNES REVERSE MH_FG_0 +VS +VS +VS R0 KOhm R0 KOhm R0 KOhm NJ RESTLINE_PM MH_FG_ MH_FG_ R0.KOhm R0.KOhm FG0 : SVO/PIE ONURRENT MOE LOW = ONLY SVO or PIE is Operational HIGH = SVO and PIE are operating simultaneously via the PEG port FG [:] : XOR/LL-Z 00 = Reserved 0= XOR Mode Enabled 0= ll-z Mode Enabled = Normal Operation (efault) MH_FG_ R0.KOhm FG : ynamic OT STRP Low = ynamic OT isabled HIGH = yanamic OT Enabled (default) SUSTeK OMPUTER IN ustom ES ate:, 0, 00 Sheet of GN/Strapping ().0

16 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

17 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

18 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

19 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

20 000 PF/0V 00 PF/0V.Khz X000 RT_X R000 0MOhm RT_X RT T ON000 TT_HOLER +RTT T000 TPT R UF/V T00 TPT KOhm +V +V_RT 000 T 00 UF/0V +V_RT Z_LK_U Z_SYN_U Z_RST#_U Z_SOUT_U Z_LK_M Z_SYN_M Z_RST#_M Z_SIN0 Z_SIN Z_SOUT_M R00 0KOhm % R00 R00 R00 R00 RT MOS LER Ohm Ohm Ohm Ohm R0 Ohm Place ap close to connector ST_LE# ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 LK_PIE_ST# LK_PIE_ST 00 UF/.V R0 Ohm R0 Ohm R0 Ohm JRST MM_OPEN_MIL Place R0 within 00 mils of IH RTRST# +V_RT IH_INTVRMEN,LN00_SLP: High = Internal VR Enabled +.VS 00PF/V 00PF/V 00PF/V 00PF/V R0 T00 T00 SIO_SMI# R00 T0 T0 T0 T0 R0 MOhm ST0RXN ST0RXP ST0TXN ST0TXP RT_X RT_X R00 KOhm % R0 KOhm % T0 TPT R00.Ohm Z_LK Z_SYN TPT TPT Z_RST# Z_SIN Z_SIN G F F H E S R00 IE_P0 IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P IE_P IE_P IE_P G G RTX RTX RTRST# INTRUER# F INTVRMEN LN00_SLP GLN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 E0 LN_TX 0 LN_TX GLN_OK#/GPIO GLN_OMPI GLN_OMPO J H_IT_LK J H_SYN H_RST# J H_SIN0 H H_SIN H H_SIN H_SIN Z_SOUT E R0 H_SOUT E0 H_OK_EN#/GPIO G T0 H_OK_RST#/GPIO TPT F0 STLE# TPT TPT TPT TPT R0.Ohm % F ST0RXN F ST0RXP H ST0TXN H ST0TXP G STRXN G STRXP J STTXN J STTXP F STRXN F STRXP E STTXN E STTXP ST_LKN ST_LKP STRIS# STRIS IH-M FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# E F G F LRQ0# G LRQ#/GPIO E TPT F 0GTE 0GTE 0M# G PRSTP# F PSLP# E FERR# PUPWRG/GPIO TP G IGNNE# F T00 INIT# ETPT INTR 0 RIN# H T00 NMI TPT SMI# G STPLK# T00 TPT THRMTRIP# E 0 V U V T V T T T R 0 T V V U V U 0 S# Y S# Y IOR# IOW# K# IEIRQ IORY REQ W W Y Y Y W LP_0 LP_ LP_ LP_ LP_FRME# LP_RQ#0 T00 0GTE 0 H_0M# H_PWRG H_IGNNE# H_INIT# H_INTR RIN# 0 H_NMI H_SMI# H_STPLK# T00 TPT IE_P0 IE_P IE_P IE_P[0..] IE_PS# IE_PS# IE_PIOR# IE_PIOW# IE_PK# IRQ, IE_PIORY IE_PREQ H_PRSTP#,,0 H_PSLP# +VP_IH R00 Ohm +VP_IH R0 Ohm H_FERR# R0 R0 %.Ohm lose to IH,w/o stub IE_P[0..] PM_THRMTRIP#, ST if it non-used, )ST[0:]RXpn STIS,STIS# and ST_LKpn should be P. )ST[0:]TXpn and STLE# NO connect. <Variant Name> SUSTeK OMPUTER IN ustom ES IH-M () ate:, 0, 00 Sheet 0 of.0

21 0 PI_[0..] PI_[0..] +VSPI US cross moat, add Stitching cap 0 +.VS 0.UF/0V 0.UF/0V 0.UF/0V PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_INT# PI_INT# PI_INT# PI_INT# Note: PLTRST# is in VccSUS_ well PLT_RST#_S 0 E 0 E G 0 F E E E E F 0 S V +V +V V PI_RST#_IH heck uffer/leakage U00 GN SNLV0PWR V PI Interrupt I/F PIRQ# PIRQ# PIRQ# PIRQ# IH-M V U00 GN SNLV0PWR REQ0# GNT0# REQ#/GPIO0 GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO U00 GN SNLV0PWR E F 0 E F E G F0 G 0 G F G F UF_PLT_RST#_ UF_PLT_RST#_ UF_PLT_RST#_ PLT_RST#_S PI_PME# PI_EVSEL#,0 PI_PERR#,0 PI_LOK# PI_SERR#,0 PI_STOP#,0 PI_TRY# PI_FRME#,0 LK_IHPI UF_PLT_RST#_ PI_REQ#0,0 PI_GNT#0 0 PI_REQ# PI_REQ# PI_REQ# PI_/E#0 0 PI_/E# 0 PI_/E# 0 PI_/E# PI_IRY# PI_PR 0 PI_INTE#,0 PI_INTF#,0 PI_INTG# PI_INTH# UF_PLT_RST#_ 0 UF_PLT_RST#_, +V T00 TPT T0 TPT T0 TPT miniard LN miniard NEW R 0:I/O :I/O :luetooth :Finger Print :New ard :I/O :amera :I/O :miniard :I/O PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP +V US_O#0 US_O# US_O# US_O# RN0 RN0 RN0 RN0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0KOhm 0KOhm T0 TPT 0KOhm 0KOhm US_O#0 US_O# US_O# US_O# US_O# US_O# US_O# US_O# RP0.KOHM 0 US_O# RP0.KOHM 0 US_O# RP0.KOHM 0 US_O# RP0.KOHM 0 US_O# RP0E.KOHM 0 US_O#0 RP0F.KOHM 0 US_O# RP0G.KOHM 0 US_O# RP0H.KOHM 0 O[..0]# not V tolerant +VSUS PI_PME# R0 0KOhm Internal PH with K~K P P N N M M L L K K J J H H G G S PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP F PERN F PERP E PETN E PETP PERN/GLN_RXN PERP/GLN_RXP PETN/GLN_TXN PETP/GLN_TXP SPI_LK SPI_S0# E SPI_S# SPI_MOSI F SPI_MISO J O0# G O#/GPIO0 G O#/GPIO E O#/GPIO F O#/GPIO G O#/GPIO O#/GPIO0 J O#/GPIO O# H O# IH-M US MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP V V U U Y Y W W T T Y Y USP0N G USP0P G USPN H USPP H USPN H USPP H USPN J USPP J USPN K USPP K USPN K USPP K USPN L USPP L USPN M USPP M USPN USPP USPN USPP USRIS# USRIS M M N N F F LP PI SPI Place within 00 mils of IH IH oot IOS select 0 0 USIS R0.Ohm % GNT#0 0 MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PIE_IH# LK_PIE_IH Place within 00 mils of IH % +.VS R00.Ohm US_PN0 US_PP0 US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP SPI_S# (default) 0 <Variant Name> PI_RST#_IH U00 V GN SNLV0PWR PI_RST# 0,, SUSTeK OMPUTER IN ustom ES IH-M () ate:, 0, 00 Sheet of.0

22 +VS +VSUS R00 0KOhm EXT_SMI# STP_PU# PIE_WKE# INT_SERIRQ PM_THRM# RN00 0KOhm SM_LINK0 RN00 0KOhm SM_LINK RN00 0KOhm EXT_SI# RN00 0KOhm SL_ R0.KOhm S_ R0.KOhm PM_RI# R 0KOhm T_LL# R.KOhm LINKLERT# R 0KOhm PIE_WKE# R KOhm SM_LERT# R 0KOhm PM_RSMRST# SL_ S_ PM_SUS_STT# PM_LKRUN#,, PIE_WKE# INT_SERIRQ 0 PM_THRM# WLN_LE_ON 0 EXT_SMI# 0 EXT_SI# WLN_ON# SM_LINK0 SM_LINK STP_PI# STP_PU# T_ET# TLE_ON T_ON 0 _S# S_SPKR MH_IH_SYN# PM_MUSY# R 0KOhm LINKLERT# SM_LINK0 SM_LINK PM_RI# SM_LERT# PM_LKRUN# VR_PWRG_LKEN T00 TPT T_ET# T0 TPT T0 TPT T0 TPT T0 TPT T TPT T TPT R 0KOhm +VSUS J G E F F G G E0 G H E F J0 J J J H EXT_SMI# E EXT_SI# G H E G0 H G P_I F P_I J 0 J J S IH-M from WW SMLK SMT LINKLERT# SMLINK0 SMLINK RI# SUS_STT#/LPP# SYS_RESET# MUSY#/GPIO0 SMLERT#/GPIO STP_PI#/GPIO STP_PU#/GPIO LKRUN#/GPIO WKE# SERIRQ THRM# VRMPWRG TP TH/GPIO TH/GPIO TH/GPIO GPIO GPIO TH0/GPIO GPIO GPIO0 SLOK/GPIO QRT_STTE0/GPIO QRT_STTE/GPIO STLKREQ#/GPIO SLO/GPIO STOUT0/GPIO STOUT/GPIO SPKR MH_SYN# TP ST0GP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO LK LK J J0 F G G G J E H0 G J GPIO GPIO GPIO P_I0 SUSLK T0 SUSLK TPT SLP_S# G PM_SUS# 0 SLP_S# F PM_SUS# 0 T0 SLP_S# R0 TPT H S_STTE#/GPIO PM_S_STTE# 0 E PM_PWROK_R PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# T_LL# R0 R0 R0 T K_PWRG E R0 LK_PWRG LPWROK E PM_PWROK_R R0 SLP_M# J T0 TPT L_LK0_R L_LK0 F L_LK0 R0 T0 L_LK E TPT F L_T0_R L_T0 L_T0 F R0 L_T T0 TPT L_VREF0_IH L_VREF0 H L_VREF_IH L_VREF L_RST# LGPIO0/GPIO J LGPIO/GPIO0 J LGPIO/GPIO F WOL_EN/GPIO G LK_IH LK_US PM_PRSLPVR,0 PM_PWRTN# 0 PM_RSMRST# 0 T T T T L_RST# PM_PWROK_R R 0KOhm r00 an be tied to Vss R 0, PM_PWROK,0 PI_TRY# PI_INT#,0 PI_INTE# PI_INTH# PI_INT#,0 PI_REQ#0 PI_INT#,0 PI_FRME#,0 PI_STOP#,0 PI_EVSEL# PI_REQ# PI_INT# PI_REQ# PI_INTG# PI_REQ#,0 PI_INTF#,0 PI_SERR#,0 PI_PERR# PI_LOK# PI_IRY# IRQ PM_LKRUN# RP00.KOHM 0 RP00.KOHM 0 RP00.KOHM 0 RP00.KOHM 0 RP00E.KOHM 0 RP00F.KOHM 0 RP00G.KOHM 0 RP00H.KOHM 0 T_ET# RP0.KOHM 0 RP0.KOHM 0 RP0.KOHM 0 RP0.KOHM 0 RP0E.KOHM 0 RP0F.KOHM 0 RP0G.KOHM 0 RP0H.KOHM 0 RP0.KOHM 0 RP0.KOHM 0 RP0.KOHM 0 RP0.KOHM 0 RP0E.KOHM 0 RP0F.KOHM 0 RP0G.KOHM 0 RP0H.KOHM 0 GPIO RP0.KOHM 0 PM_THRM# RP0.KOHM 0 INT_SERIRQ RP0.KOHM 0 GPIO RP0.KOHM 0 GPIO RP0E.KOHM 0 IRQ RP0F.KOHM 0 RP0G.KOHM 0 STP_PU# RP0H.KOHM 0 +VSUS +VS +VS +VS +V +VS R0 P I.0..0 P_I0 P_I P_I I0 I I R 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm L_VREF_IH 00 0.UF/0V R.KOhm R Ohm L_VREF0_IH 0 0.UF/0V R.KOhm R0 Ohm VR_PWRG_LKEN Q00 N00 0KOhm R G S LK_EN# E_LK_EN 0 <Variant Name> SUSTeK OMPUTER IN ustom ES IH-M () ate:, 0, 00 Sheet of.0

23 0 m E:EN-00 S:EN-000 EN-000,EN-000 ustom,, 00 SUSTeK OMPUTER IN IH-M ().0 ES <Variant Name> ate: Sheet of +VREFSUS +.VS_PIE_IH +VREFSUS +.VS +VS +VS +.VS +.VS_PIE_IH +VP_IH +.VS +.VS +.VS +V_RT +VP_IH +VS +VS +VSUS +VSUS +VS +VS +.VS +VP +VP_IH +VS +.VS +VSUS +VSUS 0.UF/0V UF/.V 0.UF/0V 0.0UF/V R0 r00_h 0.0UF/V 0.UF/0V R0 r00_h T00 TPT R0 r00_h JP00 MM_OPEN_MIL 0.0UF/V 0.0UF/V 0.UF/0V 0 0.UF/0V 0.0UF/V 0UF/.V R UF/V UF/.V T0 TPT + E00 0UF/V 0 UF/.V L00 /00Mhz 0.UF/0V 0 0.UF/0V.UF/.V 0 0.UF/0V 0 0.UF/0V 0UF/.V 0.0UF/V R0 r00_h R0 0.UF/0V R r00_h 0 0.UF/0V 0.0UF/V 0.0UF/V 0 0.UF/0V 0.UF/0V L0 /00Mhz 00 0.UF/0V 00 TW 0.0UF/V 0 0.0UF/V 0 UF/.V SF IH-M T G E E E F F G H H J J K K L L L M M N N N P P R R R R T T T T T U F R E F G H J J F G E F G L L L L L L M M P P T T F G0 U V W W W Y E0 E F G0 H P P N P P P P P R R R 0 G G J F0 F L L M M W U V V V U V V V F E R H J E E G G F0 W V U Y V V VREF[] VREF[] VREF_SUS V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V_[0] VMIPLL V [0] V [0] V [0] V [0] V [0] VSTPLL V_[0] V [0] V [0] V [0] V [0] V [0] VUSPLL VLN_0[] VLN_0[] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[0] VLN_[] VLN_[] VH VSUSH V_PU_IO[] V_PU_IO[] V_[0] V_[0] V_[0] V_[0] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VRT VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] V [] V [] V [] V [] V [] V [] VSUS_0[] VSUS_0[] V [0] V [] V [] V [] V [] VSUS_[0] V_[] V [] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ VGLNPLL V_[0] V_[0] V_[0] V_[0] VSUS_[] V [] VSUS_[] V [] V [] VSUS_[] V_MI[] V_MI[] VL_0 VL_[] VL_[] VL_ V [] V [] V [] V [] V [] V [] L0 /00Mhz R0 r00_h R0 r00_h 0.0UF/V 0UF/.V R0 r00_h 0UF/0V 0 0.UF/0V SE IH-M 0 E E E E E E E E F F F F F G G H0 H H H H F H H H H H H J 0 E E E E F E F F F G E G0 G G G G G G H H H H H J J J J J J K K K K K L L L L L L L M M M M M M M M M M N N N N N N N N N N N N N N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y H H J J J J U K W VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[] VSS_NTF[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[0] VSS[].UF/.V UF/.V 0.0UF/V R0 r00_h R0 r00_h 0 TW L0 /00Mhz 0 0.0UF/V 0 0UF/.V 0.0UF/V

24 heck IH-M IH-M SM_LINK0 SM_LINK SL_ S_ +VS Q00 UMKN onnect SMLINK and SMUS for SMus.0 compliance. Q00 UMKN Q0 UMKN +VS Q0 UMKN +VS R00.KOhm +VS R0.KOhm SL_S S_S SL_S,,,, S_S,,,, <Variant Name> SUSTeK OMPUTER IN ES LOK IGRM ate:, 0, 00 Sheet of.0

25

26 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

27 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

28 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

29 +VS_VPI +VS X00.Mhz PF/0V +VS 00 L00 /00Mhz 0.UF/0V 0 0.UF/0V PF/0V +VS 0 0UF/0V R UF/0V 0UF/0V +VS_LK 0 0.UF/0V +VS_V 0.UF/0V PWRSVE# 0 U00 VPIEX VPIEX VPIEX PWRSVE#* VPU V GN X V VREF PI/PIEX_STOP# PU_STOP# PUT_LF PU_LF PUT_L0 PU_L0 +VS_V +VS_VREF LK_MH Ohm LK_MH# Ohm LK_PU LK_PU# 0 0.UF/0V STP_PI# STP_PU# Ohm Ohm 0 0.UF/0V RN00 RN00 RN0 RN0 0 0UF/0V 0 0.UF/0V LK_MH_LK LK_MH_LK# LK_PU_LK LK_PU_LK# L0 /00Mhz 0 0UF/0V R0 R0 0.UF/0V 0 0.UF/0V +VS_VPI PEREQ# PEREQ# 0 = Enable control PIEX/ through I = isable PIEX/ ontrolled 0 = Enable control PIEX// through I = isable PIEX// ontrolled -->ISLE PIEX -->ISLE PIEX in pair LK_REFSS LK_REFSS# LK_VGSS LK_VGFIX LK_US 0 FSL LK_PI LK_SIOPI LK_TPMPI LK_GPI LK_IHPI LK_KPI +VS R KOhm R ES.ER Ohm Ohm Ohm Ohm Ohm.KOhm Ohm Ohm Ohm Ohm Ohm Ohm,,,,,,,, R0 R0 R R R R R R0 R0 R0 R0 R0 SL_S S_S PI PI PI PI0 PIF PIF0 L_SSGT L_SSG US FSL X FIX/L_SSGT/PIeT_L0 SS/L_SSG/PIe_L0 FSL/US_MHz FSL/TEST_MOE *SELPIEX0_L#PILK PILK PILK PILK0/REQ_SEL** *SELL_#/PILK_F ITP_EN/PILK_F SLK ST VREF GN GN GN GN GN GN GN ISLPRGLF_T PUITPT_L/PIeT_L PUITP_L/PIe_L PEREQ#/PIeT_L PEREQ#/PIe_L PIeT_L PIe_L PIeT_L PIe_L PIeT_L PIe_L PIeT_L PIe_L PIeT_L PIe_L PIeT_L PIe_L STLKT_L STLK_L PIeT_L/OTT_MHzL PIe_L/OT_MHzL *PEREQ# PEREQ#* VttPWR_G/P# REF/FSL/TEST_SEL REF LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# STKT STL OT OT# PEREQ# PEREQ# REF REF0 R0 R R FSL L_SSGT L_SSG US PI R R Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 0KOhm Ohm RN0 RN0 RN0 RN0 PF/0V PF/0V PF/0V PF/0V LK_PIE_LN LK_PIE_LN# LK_MH_GPLL LK_MH_GPLL# LK_PIE_NEWR LK_PIE_NEWR# LK_PIE_MINIR LK_PIE_MINIR# LK_PIE_PEG LK_PIE_PEG# LK_PIE_IH LK_PIE_IH# LK_PIE_MINIR0 LK_PIE_MINIR0# LK_PIE_ST LK_PIE_ST# LK_REF LK_REF# LK_REQ_MINIR# LK_NEWR_REQ# LK_PWRG LK_SIO LK_IH PWRSVE# PEREQ# PEREQ# PU_SEL0 PU_SEL PU_SEL R 0KOhm Latched Input Select R 0 = SR LK = PU_ITP LK REQ_SEL PIF0 0 = PIELK = PEREQ# REQ_SEL PI0 R R R0 0KOhm +VS R R0 R 0KOhm ecide pin. ecide pin 0. 0KOhm 0KOhm +VS 0 = LLK = PIEX Reserved for R.0 ebug R KOhm R KOhm +VP ecide pin... SELPIE0_L# PI R0 0KOhm SELL_# =0, ecide pin pin#/=piex_l;... pin#/=fix/ss, SELL_# =, pin#/=ot_mhzl; pin#/=l_ssg/pie_l0. PIF R KOhm R R R R KOhm R FSL FSL FSL R R R 0KOhm 0KOhm LK FS SEL SELSEL0 PU riven +VS KOhm KOhm KOhm / 0 MH_SEL0 MH_SEL MH_SEL / / ISLPRGLF-T INT-PU, INT-P resistor value is 0K ohm. PI PI PI0 PIF PIF0 WWN 0 PF/0V PF/0V PF/0V PF/0V PF/0V <Variant Name> SUSTeK OMPUTER IN ustom ES LOK GEN, 0, 00 ate: Sheet of.0

30 +V 000 0UF/.V +V_E GN 00 0UF/.V L000 /00Mhz 00 0.UF/V EXT_SI#,EXT_SMI# Page : 0K PH to +VSUS LP_0 LP_ LP_ LP_ +V_E 00 0.UF/V E_GN +V For Expreeard ebug ard T0 T0 TPT T00 TPT T0 TPT TPT R UF/V RN000 OHM RN000 OHM RN000 OHM RN000 OHM LK_KPI LP_FRME# UF_PLT_RST#_ INT_SERIRQ EXT_SMI# EXT_SMI# EXT_SI# EXT_SI# 0GTE 0 0GTE 0 RIN# E_RST# T000 T00 TPT FR# TPT FWR# FS# F0 F F F F F F F F0 F F/ R0 F/ R F/ PPEN F/ SHM F F F F F0 F F F F F F F F F KSI0 KSI KSI KSI KSI KSI KSI KSI KSO0 KSO KSO KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO E_XIN E_XOUT V/_ON# TV_ON# V_E E SERIRQ ESMI#/GPM0 ESI#/GP G0/GP KRST#/GP WRST# PWUREQ#/GPM FR# FWR# FS# F0 F F F F F F F F0 F F/R0 F/R F/PPEN F/SHM F F F F F0 F F F F F F/GPG0 F/GPG F/GPG F/GPG KSI0/ST# KSI/F# KSI/INIT# KSI/SLIN# KSI KSI KSI KSI KSO0/P0 KSO/P KSO/P KSO/P KSO/P KSO/P KSO/P KSO/P KSO/K# KSO/USY KSO0/PE KSO/ERR# KSO/SLT KSO KSO KSO ITTE E_GN +VPLL +V_E +VPLL +VS +V L0 L L L LPLK LFRME# LPRST#/WUI/GP KK KKE R UF/V PSLK0/GPF0 PST0/GPF PSLK/GPF PST/GPF 00 0.UF/V +VS GN, FORE_OFF# 0 SMLK0/GP SMT0/GP SMLK/GP SMT/GP 0/GPK0 /GPK /GPK /GPK /GPK /GPK 0 0/GPJ0 /GPJ 00 /GPJ 0 /GPJ 0 PWM0/GP0 PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP 0 PWM/GP RX/GP0 TX/GP GP RING#/PWRFIL#/LPRST#/GP S.SR GN GN GN lock start time:00ms t=0.*0^*cd (sec) = ms TSEL_P# FN_PWM LKOUT/GP0 PWRLIMIT# GP _IN_O# TMRI0/WUI/GP GP T_IN_O# TMRI/WUI/GP KKOUT/GP RI#/WUI0/GP0 RI#/WUI/GP GP GINT/GP TH0/GP TH/GP RFON_SW# OLOREN# LUETOOTH# /GPE0 /GPE MRTHON# /GPE 0 ISTP# /GPE PWRSW/GPE WUI/GPE LPP#/WUI/GPE LKRUN#/WUI/GPE PSLK/GPF PST/GPF PSLK/GPF INSTNT_ON# PST/GPF F0/GPG F/GPG LP0HL/GPG LP0LL/GPG GPH0 GPH GPH GPH GPH 0 GPH GPH GPH 0 PMTHERM# _PR_U# R0 0 PU_PWRG PM_PWRTN# K_I0 K_I T0 TPTPWR_SW# GPI0 GPI GPI GPI GPI GPI GPI OS#_O SUS_E0# T0 TPT R00 R00 00.UF/.V SM0_LK SM0_T SM_LK SM_T R0 K_I0 K_I U00 RST/OUT N V/V GN RNV +V_E +V_E E_RST# R0 00KOhm IT built-in level detection TSEL_P# UF/V L_L_PWM FN_PWM 0 HG_LE_UP# PWR_LE_UP# L_KOFF# P_LE THRO_PU J_LE# PWRLIMIT# ES.PR _IN_O# 0 OP_S# E_IE_RST T_IN_O# 0 T0 SLP_S#_R TPT SLP_S#_R T0 TPT PM_SLP_M# T0 TPT FN0_TH 0 OLOREN# LUETOOTH# WLN_SW# MRTHON# PWR_SW# PM_LKRUN# TP_LK TP_T INSTNT_ON# LI_SW# SS VSUS_ON SUS_PWRG, VRM_PWRG 0, PM_PWRTN# T00 SUS_E#, TPT PU_VRON 0 PM_RSMRST# PM_PWROK, LL_SYSTEM_PWRG HG_EN# PREHG E_LK_EN T_LERN 00 SS +V_E E_XIN heck GP0 function!! FingerPrinter power on/off# PWR_SW# INSTNT_ON# R00.KOhm SM0_LK R00.KOhm SM0_T R00 KOHM T_IN_O# R0 0KOhm _IN_O# R0 0KOhm LI_SW# R0 0KOhm PU_PWRG R0 0KOhm _PR_U# R0 KOHM PWRLIMIT# +VSUS +VS +VS R00 R00 PM_THRM# R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R0 R00 0 UF/V 0KOhm 0KOhm R0 0KOhm E_RST# 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0GTE 0KOhm RIN#.KOhm SM_LK.KOhm SM_T R0 SLP_S#_R R0 SLP_S#_R GN 00 PF/0V PM_PWRTN# K_I0 K_I TP_T TP_LK R0 GN GN 0KOhm LUETOOTH# 0KOhm WLN_SW# 0KOhm MRTHON# 0KOhm ISTP# 0KOhm OLOREN# ES.PR R0 R00 E_XOUT 0MOhm X000 R00.Khz +/-0ppm/.PF 00KOHM R0 E_GN 00KOHM 00 PF/0V PM_SUS# PM_SUS# _PR_U# Q000 N00 G S GN _PR_U, PM_S_STTE# R0 FP_PWR_ON T0 T0 TPT 0 VG_ETE# TPT 0 VG_ETE#, G_ON# IR_TX IR_RX E_GN SUS_E# signal definition: GPJ:PS_PPE# (reserve) GPJ:PS_SHN#(reserve) PWR_MON:(N) <Variant Name> SUSTeK OMPUTER IN ustom ES IT0/(/) ate:, 0, 00 Sheet 0 of.0

31 0:etermined by E +V_E +V_E F/ R F/ SHM GN R00 0KOhm R0 0KOhm +V_E R0 0KOhm R0 0KOhm WS R. GN SHM No pull up: disable shared memory with host IOS Ext 0K up: enable shared memory with host IOS F 0 F/ R0 F/ R F/ PPEN F/ SHM F 0 F 0 F 0 F F0 F F F F 0 F F F F F +V_E 00 UF/0V 0 F/ R0 F/ PPEN M TSOP U N0 0 N N N Vcc GN +V_E GN R0 0KOhm MXLV00TT R0 0KOhm R0 0KOhm R0 0KOhm Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q/- E# OE# WE# RESET# RY/Y# YTE# Vss Vss 0 0 R[:0] No pull up: The register pair to access PNPFG is 00Eh and 00Fh. Ext 0K up on R0: The register pair to access PNPFG is 00Eh and 00Fh. Ext 0K up on R: The register pair to access PNPFG is determined by E domain registers SWLR and SWHR. PPEN No pull up: Normal Ext 0K up: KS interface pins are switched to parallel port interface for in-system programming. KT KT0 Matrix US 0 UK 0 JP Touch Pad TP_SW_L R0 0KOhm F0 F 0 F F F F F 0 F 0 F0 FS# FR# FWR# E_RST# 0 TPN SIE 0 SIE FP_ON_P 0 G PF/0V KN SIE SIE FP_ON_P SW00 TT_SWITH_P 0 0.UF/V <Variant Name> KSI KSO KSI KSO0 KSI KSO KSI KSO KSI KSO KSI KSI KSO KSO KSI0 KSO KSO KSO KSO KSO KSO0 KSO KSO KSO L00 /00Mhz L0 /00Mhz L0 /00Mhz SUSTeK OMPUTER IN K_I0 K_I TP_SW_R +VS 0 KSI KSO 0 KSI KSO0 KSI KSO KSI 0 KSO KSI KSO 0 KSI KSI KSO 0 KSO KSI0 0 KSO KSO KSO KSO KSO 0 KSO0 0 KSO KSO 0 KSO 00PF/0V TP_SW_L TP_SW_R SW0 K_I0 K_I TT_SWITH_P TP_T TP_LK IT0/(/) GN GN GN ustom ES ate:, 0, 00 Sheet of.0

32 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

33 00 0.UF/0V VTRL.KOhm R00 +GV_LN XIN_LN XOUT_LN +V_LN +V_LN +V +V_LN verage supply current V 0m V+EV m V m 0 mil +VSUS L00 /00Mhz 0 0 mil 0 0 +V_LN +V_LN 0 0.UF/0V 0UF/.V 0.UF/0V 0.UF/0V +V_LN LN0 +V_LN L_TP L_TN L_RP L_RN L_TRP L_TRM L_TRP L_TRM,, PIE_WKE# UF_PLT_RST#_ SS without R0, 0u leakage when S EES EESK EEI EEO +V_LN VTRL +V_LN R0.KOhm +V_LN +EV_LN U0 S V SK I ORG O GN T R0 0 R0 VTRL V_ MIP0 MIN0 V_ MIN MIP Symbol:wrong pin definition V_ V_ MIP SPISK 0 0 MIN TS V_ V_ MIN V_ MIP ISOLTE V_ SPISI V_ SPISO RTL V_ +V_LN 0.UF/0V )S/PLTRST# and RTL are in VccSus_ well )PLTRST# will be low before PM_SUS# go low N be high after PM_SUS# go high )UF_PLT_RST# could be S or S0 pwr well R0 0KOhm EESK EEI/UX V_ EEO EES V_ SPIS V_ GN_GN_ PIE_RXN_LN PIE_RXP_LN GN_GN_ XIN_LN XOUT_LN R0 X00 Mhz EESK EEI EEO EES 0.UF/0V 0.UF/0V +VS R0 KOhm R0 KOhm PIE_RXN PIE_RXP LK_PIE_LN# LK_PIE_LN PIE_TXN PIE_TXP R0 KOhm VTRL +V_LN SUS_E# VTRL +V_LN Q00 S Q0 S 0 0UF/.V mil 0UF/.V 0 0.UF/0V 0mil mil mil L0 +V_LN +V_LN /00Mhz 0 0.UF/0V R0 0UF/.V 0 0.UF/0V +V_LN UF/V 0.UF/V +EV_LN 0.UF/0V 0.UF/0V +V 0 0.UF/V 0.UF/V 0.UF/V 0.UF/0V 0.UF/V 0.UF/0V PF/0V PF/0V <Variant Name> SUSTeK OMPUTER IN ustom ES GigaLN ate:, 0, 00 Sheet of.0

34 0S have issue after IR reflow, alternative part:lg-0s- TT U00 MTL_MT UF/0V PF/0V 0 0.0UF/0V PF/0V WWN L_TRM L_TRP L_TRM L_TRP L_RN L_RP L_TN L_TP 0 0.0UF/0V PF/0V 0 PF/0V T+ TT T+ TT T+ TT 0 T+ MX-L_TXP T- T- T- T- 0.0UF/0V LG_0S_ L_MT L_MT L_MT L_MT0 ZLI M onnector Transformer close ON Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 R00 MX+ L_TRLM 0 MX+ L_TRLM MX+ L_RXN MX+ L_TXN MX-L_TRLP MTL_MT MX-L_TRLP MTL_MT MX-L_RXP MTL_MT0 FGNS PF/0V 0 000PF/0V L_TXP L_TXN L_RXP L_RXN L_TXN L_TXP L_RXN L_RXP L_TRLP L_TRLP L_TRLP L_TRLM L_TRLP L_TRLM L_TRLM L_TRLM R0 R0 R0 R0 LTXN L00 0 LTXP +V LRXN L0 0 LRXP LTRLM L0 0 LTRLP LTRLM L0 0 LTRLP R0 R0 R0 R0 LTRLP FOR EMI o-layout o-layout MN R0 LTXP LTXN LRXP LRXN LTRLP LTRLM LTRLM LTRLM LTRLP LRXN LTRLM LTRLP LRXP LTXN LTXP TIP RING L0 KOhm/00Mhz L0 KOhm/00Mhz PF/KV ON00 SIE P_GN NP_N 0 NP_N P_GN SIE MOULR_JK_P ON0 SIE SIE WTO_ON_P S.SR ES.PR 0 000PF/KV Z_SOUT_M Z_SYN_M Z_SIN Z_RST#_M R0 Ohm UF/0V TO_ON_P Z_LK_M <Variant Name> SUSTeK OMPUTER IN ustom ES RJ+, M ate:, 0, 00 Sheet of.0

35 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

36 MI_VREFOUT MI_VREFOUT_L MI_VREFOUT VREF_OE MI_VREFOUT_L GN_UIO 00 UF/V c00_h 0 GN_UIO UF/V 0 GN_UIO UF/V GN_UIO 0 0UF/.V c00 GN_UIO 0 0.UF/V c00 ES.PR RER_L RER_R +VS GN +VS S/PIFO UF/V c00_h GN GN 0.UF/0V T00 LINE_VREFOUT TPT HP_J R00.KOhm LINE_J UF/V UF/V GN_UIO GN_UIO R0.KOhm GN_UIO R0 0KOhm % 0PF/0V +VS_OE GN R0.KOhm R0.KOhm EN-000 EN-000 E:EN R0 S:EN-0000.KOhm U00 +V_UIO T0 TPT T0 TPT Z_SOUT_U Z_LK_U Z_SIN0 Z_SYN_U Z_RST#_U EPOP# SHN# SET GN IN OUT G-0TUF 0G000 0 L0 Ver P_EEP R OE N V SURR-L(PORT--L) JREF SURR-R(PORT--R) VSS ENTER(PORT-G-L) LFE(PORT-G-R) N N N SPIFO L0-V-GR EPOP# R 0PF/0V R Ohm GN No symbol in data base, modify manually 000PF/0V GN diust able Vout=.*(+(00K/K)) +VS_OE R 00KOhm L00 UF/V c00_h GN_UIO +V_UIO /00Mhz 0 UF/V c00_h GN_UIO GN_UIO 0 0.UF/V c00 R.KOhm +V_UIO LINE-R(PORT--R) LINE-L(PORT--L) 0 MI-R(PORT--R) UF/0V 0 UF/0V MI_JK MI-L(PORT--L) 0 -R UF/0V _GN R -GN UF/0V UF/0V -L MI-R(PORT-F-R) UF/0V UF/0V MI-L(PORT-F-L) LINE-R(PORT-E-R) ERPHONE_R_0 LINE-L(PORT-E-L) ERPHONE_L_0 Sense +V_UIO % 0KOhm R EXTMI_J HP_J 0.UF/0V 0.UF/V c00 GN_UIO Sense MI Sense HP R R _GN R GN_UIO GN_UIO GN_UIO 0.UF/V c00 R.KOhm 000PF/0V S_SPKR 0 0.UF/V c00 MI_JK INTMI_P R KOHM R R R R R R0.KOHM /G /G /G GN_UIO 0.UF/V c00 P_EEP 00PF/V _R GN L_ EPOP# G_SPKP G_SPKN R 0KOhm R0 R0 R GN_UIO L0 /00Mhz 000PF/0V 0 000PF/0V UF/V UF/V GN GN GN GN <Variant Name> SUSTeK OMPUTER IN ustom ES OE-L0 ate:,, 00 Sheet of.0

37 Internal MI INTMI_P EXTMI_J MI_JK G_MI_P GN_UIO R PF/0V R0 R /G /ng R00 R0 ES.PR /ng /G 0 00PF/0V R0 0 00PF/0V /ng GN_UIO.KOhm GN_UIO GN_UIO.KOhm MI_VREFOUT INT_MI_JK ON00 SIE SIE Wto_ON_P To external JK MI_IN#_JK MI_VREFOUT_L EXT_MI_JK MI_VREFOUT_L MI_JK R0 +V_UIO R0 0KOhm R0 0KOhm /G 0 UF/V /G +V_UIO GN_UIO GN_UIO GN_UIO /G UF/V U00 LMMX /G GN_UIO U00 LMMX /G +V_UIO GN_UIO R 00KOHM /G 0 00PF/0V /G SUSTeK OMPUTER IN ustom + - R0 0KOhm /G ES R0 0KOhm /G 0 UF/V /G R0.KOhm /G EXT_MI_JK UIO-MI ate:, 0, 00 Sheet of.0

38 V_MP R00 0KOhm r00 JK_SW# LY_OP_SE# G S G S Q00 N00 Q0 N00 SE/TL# Z_RST#_U 0 OP_S# EPOP# +VS R0 MOhm r00_h +V R0 00KOhm +VS R0 00KOhm r00 LY_OP_SE# G S TW 0 R0 00 SS Q0 N00 ER_POP G S Q0 N00 00 UF/V ERPHONE_L_0 ERPHONE_R_0 Q0 N00 Q0 N00 ER_POP ER_POP FL FR Q0 Q0 EPOP N00 N00 R0 00KOhm JK_SW# V_MP V_MP Q0 PMS0 GIN0 GIN SE/TL V X X R0 RER_L GN_UIO +VS R0 00KOhm GN_UIO 0 0.UF/V 0 0.UF/V 0KOhm R0 V_MP GN_UIO Q0 R 0KOhm r00 PMS0 0.UF/V PV_MP GN_UIO V_SPIF GN_UIO GN_UIO PV_MP GIN INTSPKL+ 0.UF/V S/PIFO JK_SW# 0 0.UF/V GN_UIO 0 OPMP V_SPIF GN GIN0 GIN LOUT+ LLINEIN LHPIN PV RIN LOUT- LIN YPSS GN /00Mhz 0 0.UF/V c00 L0 JK_SW# L0 /00Mhz 0 UF/V c00_h TP0PWPRG L0 V_MP GN_UIO GN RLINEIN SHUTOWN# ROUT+ RHPIN V PV HP/LINE# ROUT- SE/TL# P-EEP GN 0 UF/V c00_h 0 mil width 0 0.UF/V c00 L0 /00Mhz 0 000PF/0V c00 +VS INTSPKR+ OPTI_V_JK SPIF_O_JK V_MP R MP_SHN# GN_UIO GN_UIO GN_UIO V_MP 0.UF/V R 0KOhm r00 FL FR E00 0UF/V RER_R 0UF/V E0 R0 0KOhm GN R0 0KOhm INTSPKL- INTSPKR- SE/TL# INTSPKR- INTSPKR+ INTSPKL- INTSPKL+ L0 L0 L0 L0 L0 /00Mhz L0 /00Mhz <Variant Name> SUSTeK OMPUTER IN /00Mhz /00Mhz /00Mhz /00Mhz ES 0 c00 0.0UF/V SPKR-_M_ON SPKR+_M_ON SPKL-_M_ON SPKL+_M_ON 0 0.0UF/V c00 SPKN Wto_ON_P UIO-OP ate:, 0, 00 Sheet of HP_JK_L HP_JK_R N N.0

39 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

40 +VS x : fter R Rev.R 000 0UF/.V UF/V UF/V UF/V heck ircuit for R and R +VS +VS 00 0UF/.V 00 0.UF/0V UF/V 0 V_PIV_ 0 V_PIV_ V_PIV_ V_PIV_ V_PIV_ V_PIV_ V_RIN V_V UF/V 00 0UF/.V PI_ R00 00KOhm +VS --> _GRST# ms < T < 00ms 0 0.UF/0V R UF/V PI_[0..] +VS _ISEL UF/V 0 0.UF/V PI_PR PI_/E# PI_/E# PI_/E# PI_/E#0, PI_REQ#0 PI_GNT#0, PI_FRME# PI_IRY# PI_TRY#, PI_EVSEL#, PI_STOP#, PI_PERR#, PI_SERR# _GREST#,, PI_RST# LK_PI 0 0.UF/V PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 _ISEL R0 V_ROUT V_ROUT V_ROUT V_ROUT 0 V_ROUT PR /E# /E# /E# /E0# ISEL REQ# GNT# FRME# IRY# TRY# EVSEL# STOP# 0 PERR# SERR# HWSPN# UIO UIO0/SRIRQ# INT# GN GN GN GN GN GN GN GN GN GN0 0 _SUSP# UIO UIO GRST# PIRST# PILK V_M GN GN 0 GN 0 GN 0 GN MSEN XEN UIO UIO UIO UIO INT# +VS R000 0KOhm 00 SS 0KOhm +VS R00 0KOhm R00 R00 0KOhm +VS R00 00KOhm ES.PR w/o Serial ROM: PH R00 00KOhm INT_SERIRQ PI_INTF#, PI_INTE#, _S# R00 0KOhm +VS Serial EEPROM 0 0.UF/0V U000 V WP SL S 0 GN T0N PM_LKRUN# TPT T000 R0 0 PME# LKRUN# TEST R0 00KOhm R heck USE R <Variant Name> SUSTeK OMPUTER IN ustom ES RIOH R/PI_ ate:, 0, 00 Sheet 0 of.0

41 +VS L00 /00Mhz as close as possible to R 00 PF/V PF/V 0 R : 0=0.0u R : 0= No stuff 0 0.0UF/V /HEK R00 0KOhm % 0 0.0UF/V X00.Mhz 0 00 XI XO FIL0 REXT VREF RSV R V_PHYV_ V_PHYV_ 0 V_PHYV_ 0 V_PHYV_ TPIS0 TPN0 TPP0 TPN0 TPP0 MIO MIO MIO MIO MIO MIO MIO MIO0 MIO0 MIO0 MIO MIO MIO0 MIO0 MIO00 MIO0 MIO0 MIO0 MIO0 MIO S LOSE S POSSILE TO R/ R0 Ohm ircuit area : s small as possible. SHIEL GN LOK OF MEMORY MOULE MIO0 R0 Ohm 0.0UF/V R0 Ohm 0 R0 Ohm T00 TPT 0.UF/0V 0 0.0UF/V 0.UF/0V MIO MIO MIO MIO MIO MIO MIO MIO0 MIO0 MIO0 MIO MIO MIO0 MIO0 MIO00 MIO0 MIO0 0 0PF/0V R0.KOhm 0UF/.V MIO0 TP0+ TP0- TP0- TP0+ MIO0--> xe# S LOSE S POSSILE TO ONNETOR. MIO0--> S Power ontrol / xwp MIO0--> x/ms/s LE ontrol MIO--> x ata MIO--> x ata MIO--> x ata MIO--> x ata MIO--> x LE MIO--> x LE R0 R0 L0 ommon hoke IEEE S.SR MIO0--> MS ard etect MIO0--> S Write Protect MIO0--> S ard Power0 ontrol/ MS Power ontrol MIO0--> S External lock/ MS External lock MIO0--> S ommand/ms us State MIO0--> S lock/ms lock MIO0--> S ata 0/MS ata 0 MIO--> S ata /MS ata MIO--> S ata /MS ata MIO--> S ata /MS ata <Variant Name> SUSTeK OMPUTER IN ustom R0 R0 ES TP0-_ TP0+_ TP0-_ TP0+_ TP0-_ TP0+_ TP0-_ TP0+_ RIOH R/PI_ ate:, 0, 00 Sheet of.0

42 +VS Q00 IRLML0PF To correct the problem when MS uo adaptor is in use. +VS Q0 MIO0 R00 0KOhm UF/V +V Place as close to card 0 reader socket 0.UF/0V as possible R0 0KOhm X_PWR_EN IRLML0PF 0 0.0UF/V XR +V Place as close to card reader 0 0.UF/0V socket as XR possible Solve MS uo daptor short issue. MIO0 0 0PF/0V MIO0 MIO0 ST MIO MIO0 MIO0 MIO MIO MIO0 MIO MIO0 MIO0 ST +V +V MIO0 MIO MIO MIO00 R0 0KOhm N00K_T_E Q0 heck hange other p/n!! INN NP_N S T S /T S M S VSS M0 VSS M V M SLK M Reserved M INS M Reserved M SIO M V M S M VSS S V S LK S VSS S T0 S T G G S S N00K_T_E Q0 Q0 N00K_T_E S GN X X0 R/- X -RE X -E X LE X LE X -WE X -WP X GN X 0 X0 X X X X X X X V X ST ST R0 0KOhm MIO0 MIO0 MIO0 MIO MIO MIO0 MIO0 MIO0 MIO MIO MIO MIO MIO MIO MIO ES.PR hange to 0G00000, KV ES 00 SS X_PWR_EN MIO00 MIO0 0 SS +VS +V MIO0 MIO0 MIO MIO MIO0 MIO0 MIO0 MIO MIO MIO MIO MIO MIO MIO MIO00--> S ard etect MIO0--> MS ard etect MIO0--> S Write Protect MIO0--> S ard Power0 ontrol/ MS Power ontrol MIO0--> S ommand/ms us State MIO0--> S lock/ms lock MIO0--> S ata 0/MS ata 0 MIO--> S ata /MS ata MIO--> S ata /MS ata MIO--> S ata /MS ata MIO0--> xe# MIO0--> S Power ontrol / xwp MIO0--> x/ms/s LE ontrol MIO--> x ata MIO--> x ata MIO--> x ata MIO--> x ata MIO--> x LE MIO--> x LE NP_N S_R_P +V MIO00 MIO00 MIO0 H00 EMI_SPRING_P WWN 0 0.0UF/V XR 0 0.0UF/V XR 0 0.0UF/V XR R0 0KOhm H0 EMI_SPRING_P <Variant Name> SUSTeK OMPUTER IN ustom ES ardreader ate:, 0, 00 Sheet of.0

43 heck +V R0 SUS_E# VSUS_ON U00 STY# O# 0 SHN#.VOUT_ PERST#.VOUT_ R0 +.VS_PE US_O# US_PN ES.PR USP- R00 KOhm,0, PI_RST# +VS +.VS +VSUS PI_RST#.VIN_.VIN_.VIN_.VIN_ UXIN SYSRST# GN GN R00 UXOUT.VOUT_.VOUT_ PPE# PUS# RLKEN N 0 PPE# PUS# +.V_PE +.VS_PE US_PP R0 USP+ R0 Put R close to U0 +VS +.VS_PE GN LK_GPI_R R 0.UF/0V 0.UF/0V 00 00PF/0V LK_GPI LP_ LP_0 LP_ LP_ LK_NEWR_REQ#,, PIE_WKE#,,,, SL_S,,,, S_S 0 0.UF/0V 0 0UF/0V R0 0KOhm.0V~.V ve= 000m Max= 00 m 0.0UF/V +V 00 T PE_EUGEN# R0 00KOhm GN PPE# +V GN +.V_PE R0 KOHM 0 0.UF/0V 0.UF/.V.UF/0V GN GN lock RN00 RN00 RN00 RN00 R U0 0 0 E# X 0 0.UF/0V R0 KOHM SNTPWR.0V~.V ve= 00m Max= m 0.0UF/V Q00 PMS0 E 0 0 V GN 0 0 PE_EUGEN# GN PPE#_ LKREQ#_ PIE_WKE#_ SM_LK_ SM_T_ lock GN +.VS +.VS_PE GN R0 +V 0 0.UF/0V 0.UF/.V.UF/0V U0 OE# V GN Y LVGGV If don't support Neward ebug ard,pls do (a) NI all components of block (b) Mount lock (RN0,R) 0 0.UF/0V.V~.V ve= 00 m Max= 0 m 0.0UF/V +V LP_FRME# TPT T00 R0 LK_GPI_R LP_0 LP_ LP_ LP_ LP_FRME# +VS 0 LP_FRME#_R LK_PIE_NEWR# LK_PIE_NEWR ON0 SIE 0 SIE FP_ON_P ottom ontact PIE_RXN PIE_RXP PIE_TXN PIE_TXP USP- USP+ PUS# SM_LK_ SM_T_ +.VS_PE PIE_WKE#_ +.V_PE +.VS_PE LKREQ#_ PPE#_ <Variant Name> SUSTeK OMPUTER IN ustom +.V_PE +.V_PE ES ON00 GN US_- US_+ PUS# RESERVE RESERVE SMLK SMT +.V_ +.V_ WKE# +.VUX PERST# +.V_ +.V_ LKREQ# PPE# REFLK- REFLK+ GN PERn0 PERp0 GN PETn0 PETp0 GN EXPRESS_R_P ON0 P_GN P_GN R_EJETOR_P VW_L VW_L GN NP_N NP_N GN 0 USP- USP+ Express ard ate:, 0, 00 Sheet of.0

44 SUSTeK OMPUTER IN lank ES ate:,, 00 Sheet of.0

45 E heck stub +VS +VSUS +VS +VS,,,,,,,,,,,0,,,,0,,,,,,,0,,,,,,,0,0, +VSUS +VS,,0, LVS_Y0P 0 LVS_Y0P_NV LVS_Y0N LVS_Y0N_NV LVS_YP LVS_YP_NV LVS_YN +VS LVS_YN_NV LVS_YP 0 LVS_YP_NV LVS_YN 0 LVS_YN_NV LVS_LKP 00 0 LVS_LKP_NV LVS_LKN 0 LVS_LKN_NV LVS_Y0P FootPrinter from UF/V LVS_Y0P_NV LVS_Y0N LN TO_ON_0P 0 LVS_Y0N_NV LVS_YP LVS_YP_NV LVS_YN +VS +L_V 0 LVS_YN_NV +L_V 0 LVS_YP 0 +L_V 0 LVS_YP_NV +VS LVS_YN EI_LK EI_T LVS_YN_NV LVS_LKP 0 LVS_LKP_NV LVS_LKN LVS_Y0N LVS_Y0N 0 LVS_LKN_NV R0 R00 LVS_Y0P 0 LVS_Y0P 0 0KOhm 0KOhm LVS_YN LVS_YN LVS_YP LVS_YP R0 EI_LK EI_LK_GM R0 EI_T LVS_YN LVS_YN RN00 LVS_Y0P LVS_YP LVS_YP RN00 LVS_Y0N 0 RN0 LVS_YP LVS_LKN LVS_LKN RN0 LVS_YN 00PF/0V LVS_LKP LVS_LKP RN0 LVS_YP RN0 LVS_YN EI_T_GM 0 0 LVS_Y0P_GM EI_LK_NV 0 LVS_Y0N_GM EI_T_NV LVS_YP_GM 00PF/0V LVS_YN_GM LVS_YP_GM LVS_YN_GM RN0 LVS_LKP LVS_LKP_GM RN0 LVS_LKN LVS_LKN_GM RN0 LVS_Y0P LVS_Y0P_GM RN0 LVS_Y0N LVS_Y0N_GM RN0 LVS_YP LVS_YP_GM RN0 LVS_YN LVS_YN_GM RN0 LVS_YP RN0 LVS_YN LVS_YP_GM LVS_YN_GM RN0 LVS_LKP LVS_LKP_GM RN0 LVS_LKN PF/0V PF/0V LVS_LKN_GM LVS_LKN LVS_LKN 0 SS +V +VS +VS R 0 L00 /00Mhz _T_SYS R R 00KOHM Q0 0 INVN 0KOhm R +L_V V 0.UF/V V S G GN PMNEN L0 KOhm/00Mhz GN 00KOHM 0 L_L_PWM L0 /00Mhz R0 00KOHML0 KOhm/00Mhz VREF +L_V KEN Q00 0 RF 0 0 PWM UMKN WTO_ON_P LI_SW# R 0.UF/V 0.UF/V L_V_EN_GM 00PF/0V 0 L_V_EN_NV 0 L_KOFF# Q00 0.UF/V 0.UF/V 0UF/0V 0UF/0V UMKN R R0 0F0JL L_KEN_GM L_KEN_NV 0KOhm LVS_LKP 0 WWN PF/0V PF/0V LVS_LKP PF/0V 0 PF/0V INVERTOR NT R 0KOhm <Variant Name> SUSTeK OMPUTER IN ustom ES LVS & Inverter ate:, 0, 00 Sheet of.0 E

46 +VS +VS 0 _HSYN_NV 0 _VSYN_NV RT_VSYN heck stub R R +VS V GN U00 T0SX_NL VSYN_RT +VS 00 0.UF/V V GN U00 T0SX_NL _R_RT _G_RT RT 0 Ohm 0 V GN U00 T0SX_NL +.VS +VS +V +VS +.VS 0, +VS,,,,,,,,,,,0,,,,0,,,,,,,0,,,,,,,0,0,, +V,,,,,0, +VS Ohm(ideally Ohm) Ohm/00Mhz L0 Ohm/00Mhz L0 L0 Ohm/00Mhz RE GREEN LUE +VS _ L0 /00Mhz 0 0 RT_HSYN _NV _NV _R_NV _G_NV NV GM _G_GM _R_GM _GM _GM +VS Zo= 0 ohm RN00.kOhm +VS +VS RN0 _R_RT RN0 _G_RT RN0 RT RN0 RN0 RT RN0 _G_RT RN0 _R_RT RN0 R0 R0 RN00.kOhm V GN U00 T0SX_NL 00 SS _NV _NV Q00 UMKN HSYN_RT RN00.kOhm RN00.kOhm Q0 UMKN HSYN_RT VSYN_RT _ +VS ES.ER 0 V RE 0 V GREEN LUE R00 R0 L0 0 R0 R0 R V 0PF/0V 0PF/0V 0PF/0V RTN HSYN VSYN _SU_PR lue:g000l 0 Ohm Ohm /00Mhz <Variant Name> SUSTeK OMPUTER IN ustom 0 ES PF/0V PF/0V PF/0V HSYN VSYN 0 PF/0V0PF/0V0PF/0V PF/0V RT & TV-Out ate:, 0, 00 Sheet of.0

47 dd VI hoke 0G0000 for EMI +VS_ 00 FSJTP ES.ER +VS +VS 0 VI_TXP_NV VI_TXN_NV VI_TXP_NV 0 VI_TXN_NV VI_TXP_NV VI_TXN_NV VI_TXP_NV VI_TXN_NV 0 VI_TX0P_NV VI_TX0N_NV R0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 VI_TXP_NV_R 0/0mVI_TXN_NV_R L0 FOR EMI VI_TXP_NV_R 0/0mVI_TXN_NV_R L FOR EMI VI_TXP_NV_R 0/0mVI_TXN_NV_R L FOR EMI VI_TXP_NV_R 0/0mVI_TXN_NV_R L FOR EMI VI_TX0P_NV_R 0/0mVI_TX0N_NV_R L FOR EMI VI_TXP_NV VI_TXN_NV 0 VI_LKP_NV 0 VI_LKN_NV VI_TXP_NV_R VI_TXN_NV_R VI_TXP_NV_R VI_TXN_NV_R VI_TXP_NV_R VI_TXN_NV_R VI_TXP_NV_R VI_TXN_NV_R VI_TX0P_NV_R VI_TX0N_NV_R VI_TXP_NV_R VI_TXN_NV_R R0 0 R 0 R 0 VI_LKP_NV_R VI_LKN_NV_R VI_TXP_NV_R 0/0mVI_TXN_NV_R L L FOR EMI VI_LKP_NV_R VI_LKN_NV_R R 0 0/0m FOR EMI 0 0 VIN TMS_T_+ TMS_T_- TMS_T_+ TMS_T_- TMS_T_+ TMS_T_- TMS_T_+ TMS_T_- TMS_T_0+ TMS_T_0- TMS_T_+ TMS_T_- TMS_LK+ TMS_LK- P_GN P_GN NP_N NP_N VI_ON_P _K _T HOT_PLUG_ETET V_SYN GN_for+V +V_POWER TMS_LK_Shield TMS_/_Shield TMS_T_/_Shield TMS_T_0/_Shield L0 KOhm/00Mhz L0 KOhm/00Mhz L0 KOhm/00Mhz L00 F00 /00Mhz 00 0.UF/V +VS R00 R0.KOhm.KOhm Q00 UMKN R0./V +VS_ Q00 UMKN 0 SS R0 0KOhm +VS R0 R0.KOhm.KOhm 0 V R0 00KOhm VI_LK_NV VI_T_NV +VS VI_HP_NV SUSTeK OMPUTER IN VI ES ate:, 0, 00 Sheet of.0

48 SUSTeK OMPUTER IN ES LNK ate:,, 00 Sheet of 0

49 0 Ohm Ohm(ideally Ohm) /00Mhz TV_ L HTV_EN# VS TV_VS_NV TV_Y_NV TV NV TV GM TV GM TV GM 0 V 0 V 0 V Zo= 0 ohm TV_ TV_Y TV_VS TV_VS RN00 TV_VS RN00 TV_Y RN00 TV_ RN00 RN0 TV_ RN0 TV_Y RN0 TV_VS RN0 R.PF/0V.PF/0V _ON /00Mhz TV_Y L Y_ON R R0.PF/0V /00Mhz L.PF/0V.PF/0V.PF/0V VS_ON GN GN0 N Y VS VS TVSN MINI_IN_P G00 SUSTeK OMPUTER IN TV ES ate:, 0, 00 Sheet of.0

50 +VS R00 R00 0KOhm 0KOhm OS#_O THEM_LERT# FN & THERML ONTROLLER SM_LK SM_T SM_LK SM_T Wto_ON_P SIE SIE ON000 ES.PR +VS_FN +VS +VS R000 0KOhm 000 SS R00 U00 V +VS /00Mhz Irat= 000 0uF/0V GN Y NSZPX_NL L000 Q000 N00 FN0_TH 0 FN_PWM 0 +VS G S R00 0KOhm T000 R00 0KOhm 00 OS#_O TW S.SR SM_LK SM_T THEM_LERT# heck Thermal policy U000 G-.0V~.V Max: m 0G0000 PU_THERM_ PU_THERM_ +VS_THM R UF/0V 00 ohm for MXIM SMLK V SMT XP LERT# XN GN THERM# VG_THERM_LERT# PU_THERM_ PU_THERM_ OS#_O 00 00PF/0V +VS PU_THERM_ PU_THERM_ OS#_O 0 heck heck: read TS G-(0x) 0G0000 G(0x) 0G000 <Variant Name> SUSTeK OMPUTER IN ES FN & THERML ate:, 0, 00 Sheet 0 of.0

51 E E PT -ROM ON ST H ON UJ0:VIH=.V, 0, 00 SUSTeK OMPUTER IN H & O.0 ES ate: Sheet of IE_P IE_P IE_P IE_P IE_P IE_PREQ IE_P IE_P IE_P0 IE_PREQ IERST#_ IE_PS# IE_PIOR# IE_P IE_P IE_PSP# IRQ IE_P IE_P IE_P0 IE_P IE_PIG _GN L_ IE_P0 IE_PS# IE_PSP# IE_SSEL IE_P IE_P IE_P IE_P IE_PIOW# IE_PIORY IE_PK# _R_ IE_PIORY IERST#_ IE_P IE_P[0..] IE_SSEL +VS +VS +VS +V +VS +VS +VS +VS +VS +VS +VS +VS +VS +VS +VS +VS 0 0.UF/V 0 0UF/0V R0 0KOhm 0 0.UF/V SHN ST_ON_P NP_N NP_N GN GN 0 0.UF/V R0.KOhm 0 0UF/0V 00 P0K Q0 UMKN R0 0KOhm 0 0UF/0V R0 0KOhm r00 T00 TPT Q0 UMKN R0 KOhm 00 0.UF/V R0 OHM R0 0KOhm r00 T0 TPT R00.KOhm PON TO_ON_0P UF/0V R0 0KOhm Q00 UMKN Q00 UMKN R0 R0 KOhm +VS H_LE# UF_PLT_RST# L_ +VS,,,,,,,,,,,0,,,,0,,,,,,,,0,,,,,,0,0,, IE_P 0 IE_PK# 0 IRQ 0, _R_ IE_PIOW# 0 IE_PS# 0 ST_LE# 0 IE_P 0 IE_PIORY _GN_ IE_PREQ 0 IE_P0 IE_PS# 0 +V,,,,,0, IE_P[0..] 0 IE_PIOR# 0 ST_RXP0 ST_TXP0 0 ST_RXN0 ST_TXN0 0

52 E E US-UP US-OWN US- US- US- SU-P: US//MI/ERPHONE EMI ES.ER ES.PR ES.PR Remove US commom choke co-lay ES.PR EMI ustom, 0, 00 SUSTeK OMPUTER IN US/SU P.0 ES <Variant Name> ate: Sheet of USP0+ USP+ USP- USP+ USP+ USP- USP0+ USP0- +VUS0 +VUS0 +VUS +VUS0 USP- USP0- USP- USP+ USP- USP+ +VUS USP+ +VUS USP- +VUS_ +VUS USP+ USP+ USP- +VUS +VUS_0 +VUS_ USP- +V_US0 +V +V +V +V_US +V +V +V +V +V_US 0 0.UF/V L00 /00Mhz ON00 HEER_X0P Q0 PMNEN R.KOhm R0 V T0- T0+ GN SIE_G SIE_G SIE_G SIE_G USN US_ON_XP 0 0UF/0V + E0 00U/.V F00./V R0 R00 00KOHM 0 0.UF/V 00 EG00V0 R0.KOhm R0 R.KOhm 0 0.UF/V H00 EMI_SPRING_P + E00 00U/.V F0./V R 0 0.UF/V R.KOhm R.KOhm R F0./V R L0 /00Mhz R 00KOHM L0 /00Mhz 0 0.UF/V Q00 PMNEN V T0- T0+ GN SIE_G SIE_G SIE_G SIE_G USN US_ON_XP 0 0.UF/V R0 L0 /00Mhz 00 0UF/0V + E0 00U/.V USUN US_ON_XP 0 V P- P+ GN V 0P- 0P+ GN GN GN GN GN R0 R0 R R0 R0 Q0 PMNEN R R 00KOHM H0 EMI_SPRING_P 0 0UF/0V 0 EG00V0 R0.KOhm R0 0 0.UF/V US_PP US_PN US_PN US_PP US_PN US_PP US_PP0 US_PN0 +V,,,,0, US_PN US_PP SPIF_O_JK EXT_MI_JK MI_IN#_JK OPTI_V_JK INT_MI_JK HP_J HP_JK_R HP_JK_L JK_SW# US_O#0 US_O# US_O# TP0+_ TP0+_ TP0-_ TP0-_