SS8 BLOCK DIAGRAM CPU PCH DIS. Codec Board. Nvidia N12P-GE (128bit) 29mm X 29mm BGA 973. Sandy Bridge 35W 31mm X 24mm BGA 1023 SV

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1 IS SS LOK IGRM PGE RIII-SOIMM0 H=.mm H=.mm PGE RIII-SOIMM PGE PGE RIII MT/s RIII MT/s ST 00M /S FI LINK.GT /s PU Sandy ridge W mm X mm G 0 SV PGE ~ MI LINK GT /s PIEx Nvidia NP-GE (bit) mm X mm G R x Mxx G Mxx G PG, PGE ~ PGE PGE PGE PGE PGE PGE PGE PGE ST0 00M /S ST 00M /S.KHz PGE PGE 0 SMUS LP SPI Mobile Intel Series hipset HM ouger Point.W PGE 0 PH FG mm X mm MHz PGE ~.KHz US.0 PI-E IH PGE PGE PGE MHz PGE PGE PGE PGE PGE PGE odec oard PGE 0 PGE 0 harger PGE /V PGE.V_SUS/0.V_R PGE 0.V_RUN PGE.0V_VTT/PH PGE VS PGE GFX_ORE PGE PGE PGE PGE PU_ORE PGE Quanta omputer Inc. PROJET : SS Size ocument Number Rev LOK IGRM ate: Monday, January 0, 0 Sheet of

2 power State S0 S S S/S S/S Only / No Exist Quanta omputer Inc. PROJET : SS Size ocument Number Rev Power Rails ate: Monday, January 0, 0 Sheet of

3 Quanta omputer Inc. PROJET : SS Size ocument Number Rev LNK ate: Monday, January 0, 0 Sheet of

4 Sandy ridge Processor (MI,PEG,FI) P & PEG ompensation +.0V_PH () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP () FI_FSYN0 () FI_FSYN () FI_INT () FI_LSYN0 () FI_LSYN ep_iompo mil ep_ompio mil EP_OMP INT_EP_HP U M MI_RX#[0] P MI_RX#[] P MI_RX#[] P0 MI_RX#[] N MI_RX[0] P MI_RX[] P MI_RX[] P MI_RX[] K MI_TX#[0] M MI_TX#[] N MI_TX#[] R MI_TX#[] K MI_TX[0] M MI_TX[] P MI_TX[] T MI_TX[] U FI0_TX#[0] W FI0_TX#[] W FI0_TX#[] FI0_TX#[] W FI_TX#[0] V FI_TX#[] Y FI_TX#[] FI_TX#[] U FI0_TX[0] W0 FI0_TX[] W FI0_TX[] FI0_TX[] W FI_TX[0] T FI_TX[] FI_TX[] FI_TX[] FI0_FSYN FI_FSYN U FI_INT 0 FI0_LSYN G FI_LSYN F ep_ompio ep_iompo G ep_hp G ep_ux# F ep_ux ep_tx#[0] ep_tx#[] E ep_tx#[] E ep_tx#[] ep_tx[0] ep_tx[] E0 ep_tx[] E ep_tx[] MI Intel(R) FI P PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] G G G H J 0 G H E K K K F H F K G F H K F F J H M0 F0 J F E G K G E K G K0 G0 K PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_TXN0_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN0_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXP0_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP0_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_OMP PEG_IOMPO mil PEG_IOMPI, PEG_ROMPO mil, PEG_RXN0 () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN0 () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXN () PEG_RXP0 () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP0 () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP () PEG_RXP () 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXN0 () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN0 () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXP0 () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP0 () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () EP_OMP./F_ PEG_OMP./F_ INT_EP_HP R +.0V_PH R ep Hot-plug (isable) R0 *0K N Note: Place PU resistor within inches of PU +.0V_PH HP PU/P resistor values based on R and different to G I,SN_G,P0 +.V_SUS R0 K_ Q SS--F R K_R_RMRST#_R (,) R_RMRST# PU_RMRST# () () R_HVREF_RST_PH () R_HVREF_RST_E +.V_SUS SR R R *SJ00 *0 N K_ 0.0U/0V/XR_ R.K/F_ Quanta omputer Inc. PROJET : SS Size ocument Number Rev Sandy ridge / ate: Monday, January 0, 0 Sheet of

5 Sandy ridge Processor (LK,MIS,JTG) () () (,) IMVP_PROHOT# () PM_THRMTRIP# +.0V_PH PEI_E H_PEI SJ *SJ00 () H_PWRGOO R0 R _ R PU_PLTRST# () H_PUET# H_PROHOT#_R */F N * N Over 0 degree will drive low SJ () H_PM_SYN SJ SR R T T R _ TP_TERR# H_PEI_R H_PROHOT# SM_RMPWROK F E U PRO_SELET# PRO_ETET# TERR# PEI PROHOT# THERMTRIP# PM_SYN *SJ00 H_PWRGOO_R UNOREPWRGOO T T *P/0V/NPO N *SJ00 PM_SYN_R 0K_ *SJ00 PU_PLTRST#_R RESET# SM_RMPWROK MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM LK LK# PLL_REF_LK PLL_REF_LK# LK_ITP LK_ITP# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PRY# PREQ# TK TMS TRST# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] J H G G N N T0 F E G N N L L J M0 L K G E E G G H0 J J LK_P_P_R LK_P_N_R SM_ROMP_0 R SM_ROMP_ R SM_ROMP_ R XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI XP_TO T T0 R R R R T T LK_PU_LKP () LK_PU_LKN () K_ *0 N *0 N K_ PU_RMRST# () 0/F_./F_ 00/F_ T T T T T T0 T XP_RST# () T T T0 T T T T T LK_P_P () LK_P_N () +.0V_PH Option for Prochot# function ohm for unused, ohm for used H_PROHOT# H_PROHOT#_R XP_TMS XP_TI XP_TO XP_PREQ# R R * N * N R0 _ R _ R _ R * N +.0V_PH XP_TLK XP_TRST# R _ R _ I,SN_G,P0 When MP, JTG PU/P resistor can be removed? (Yes Intel, TI, TO, TMS, TRST#, TK,PREQ#, PRY#) +.V_SUS () PM_RM_PWRG () SYS_PWROK +.V_SUS R 00_ U HG0GW 0.U/0V/XR_ SM_RMPWROK_R R +.V_PU R 00_ R 0_ Pin L L H H * N Q0 *N00W--F_N Pin L H L H SM_RMPWROK Pin L L L High-Z PS_SNTRL (,,) +.V_PU RM_PWRG SYS_PWROK SM_RMPWROK oot S S RSM 00 ns after +.V_PU reaches 0% (,,0,,,,,) U N V PLTRST# IN OUT IN OUT L L H High-Z PU_PLTRST# *LVG0GW_N R 0_ R.K_ Quanta omputer Inc. PROJET : SS Size ocument Number Rev Sandy ridge / *0.U/0V/XR N ate: Monday, January 0, 0 Sheet of

6 Sandy ridge Processor (R) U U () M Q[:0] () M S#0 () M S# () M S# () M S# () M RS# () M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q G J P L J0 J L L R P U V R P T U Y V R Y R U R W R T Y V Y U V P0 P V T P P N N G G N N G K F E T S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] U V Y T0 U0 0 Y0 L R V T V Y T K J R0 Y U W V T K G E T U T Y V E 0 0 W Y U M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 () M LKN0 () M KE0 () M LKP () M LKN () M KE () M S#0 () M S# () M OT0 () M OT () M QSN[:0] () M QSP[:0] () M [:0] () () M Q[:0] () M S#0 () M S# () M S# () M S# () M RS# () M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q L L N R K K N R U T V U R Y E F F 0 E F E E E E G G F 0 F F E E F E Y0 E G W W U N N U U N R K L G G M0 L F H0 G T V F0 S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] Y R F E E T G L V G G T0 K M V E E R K F E U0 0 V0 G0 E0 E T V T U M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 () M LKN0 () M KE0 () M LKP () M LKN () M KE () M S#0 () M S# () M OT0 () M OT () M QSN[:0] () M QSP[:0] () M [:0] () I,SN_G,P0 I,SN_G,P0 Quanta omputer Inc. PROJET : SS Size ocument Number Rev Sandy ridge / ate: Monday, January 0, 0 Sheet of

7 Sandy ridge Processor (POWER) Sandy ridge Processor (GRPHI POWER) UF UG PU ore Power SN: +V_ORE U/.V/XR_ 0 U/.V/XR_ U/.V/XR_ U/.V/XR_ 0 U/.V/XR_ U/.V/XR_ 0 U/.V/XR_ U/.V/XR_ U/.V/XR_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0 0U/V/XS_ U/.V/XR_ U/.V/XR_ 0 U/.V/XR_ 0 U/.V/XR_ 0 U/.V/XR_ U/.V/XR_ 0 U/.V/XR_ *U/.V/XR N U/.V/XR_ U/.V/XR_ *U/.V/XR N 0 U/.V/XR_ U/.V/XR_ 0 *U/.V/XR N 0 U/.V/XR_ 0 U/.V/XR_ *U/.V/XR N 0 U/.V/XR_ U/.V/XR_ *U/.V/XR N E E E E E E F F F F F F F F G H H H H H H H H H H0 J J J J J J J J J J0 J K K K K K K K K K L L L L L0 N N0 N N V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] ORE SUPPLY POWER PEG N R SENSE LINES SVI QUIET RILS VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO0 VIO VIO_SEL VPQE[] VPQE[] VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSS_SENSE_VIO F G G0 G J J J J J K0 K L L L L0 L L L L M M M M M N0 N N N 0 E E F F F0 G G G G0 G J J W W M N F G N N H_PU_SVILRT# H_PU_SVILK H_PU_SVIT R R R SJ R0 R V_PH +V_GFX_ORE.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ *SJ_00 U/.V/XR_ *00/F N *00/F N *0/F N *0/F N *0K N +V_ORE +.0V_PH +.V_RUN +.0V_PH VSENSE () VSSSENSE () () () VIO_SENSE () VSS_SENSE_VIO () +V_GFX_ORE V_XG_SENSE VSS_XG_SENSE +.V_RUN +VS_ORE U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ SN: 0 0 R.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_ *U/.V/XR N *U/.V/XR N R 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ T *0/F N *0/F N T U/.V/XR_ U/.V/XR_ 0U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ VS_VI0 VS_VI 0 0 E N P P P0 P P P P P P T T T T U V V V0 V V V V V V V W0 W W W W W W Y Y F G L L N N0 N P P0 R R R U V V V V W0 VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG_SENSE VSSXG_SENSE VPLL[] VPLL[] VPLL[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[0] VS[] VS[] VS[] VS[] VS[] VS[] I,SN_G,P0 R R0 R R GRPHIS *K N K_ *K N K_ POWER SENSE LINES.V RIL S RIL SENSE LINES R -.V RILS QUIET RILS SM_VREF VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[0] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[0] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ_SENSE VSS_SENSE_VQ VS_SENSE VS_VI[0] VS_VI[] +.0V_PH Y J J J J0 L0 L L L M M M0 N0 N N R R R0 R R R R0 V W 0 G U0 () M N +VR_REF_PU V_SUS PS_SNTRL_S R R R VS_VI0 VS_VI +R_VTTREF SN: 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ *00P/V/XR N U/.V/XR_ * N * N 00/F_ +VR_REF_PU Q FMS0 +.V_PU +.V_PU +VS_ORE +.V_PU +.V_PU SN_IV# N. at SN ES # 0.v S Power reduce R *0 N Q *N00W--F_N VS_SENSE () VS_VI0 () VS_VI () +VR_REF_PU PS_SNTRL (,,) If +.V_PU will be implemented, have to change the two divided resistor as K-ohm % (G.) Q *N00W--F_N +.V_PU R K/F_ I,SN_G,P0 Layout note: need routing together and LERT need between LK and T H_PU_SVILK SJ *SJ00 +.0V_PH SVI LK lose to VR R./F_ VR_SVI_LK () Place PU resistor close to PU +.0V_PH +.0V_PH +.0V_PH R 0_ H_PU_SVIT SJ *SJ00 SVI T lose to VR R 0_ VR_SVI_T () Place PU resistor close to PU H_PU_SVILRT# R0 _ R0 /F_ VR_SVI_LERT#_R SVI LERT SJ0 VR_SVI_LERT# () *SJ00 () PS_SNTRL_S Quanta omputer Inc. PROJET : SS Size ocument Number Rev Sandy ridge / R K/F_ 0.U/0V/XR_ Monday, January 0, 0 ate: Sheet of

8 UH Sandy ridge Processor () UI Sandy ridge Processor (RESERVE, FG) UE E E F F F F F F0 F F F F F F F G0 G G G G G G H H J J J0 J J J0 J J J J J J K K L0 L L L L L L L L0 L L L M M0 M M M0 M VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] M M M M M M N N N N N N N0 N N N0 N P0 P P P R R R R R R R T T T T T T T U U U U U U V V V V V0 V V W W W W Y Y Y0 Y Y Y Y Y Y Y Y 0 E G G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] VSS[] VSS[] 0 VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] 0 VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[] E VSS[] E0 VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F0 VSS[] F VSS[0] G VSS[] G VSS[] G VSS[] G VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L0 VSS[0] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[0] I,SN_G,P0 VSS NTF Processor Strapping FG (PI-E Static x Lane Reversal) VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[0] N VSS[] N0 VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R0 VSS[] R VSS[] R VSS[0] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[0] V0 VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[00] Y VSS[0] Y VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_ G VSS_NTF_ G VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E Normal Operation The FG signals have a default value of '' if not terminated on the board. 0 Lane Reversed FG FG FG FG FG FG FG T T0 T T R0 R 0 FG[0] FG[] FG[] FG[] FG[] FG[] FG[] H FG[] FG[] H FG[] K FG[0] K FG[] F FG[] G FG[] L FG[] F FG[] FG[] L FG[] H V_VL_SENSE K VSS_VL_SENSE I,SN_G,P0 FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled FG FG FG R0 RESERVE H VXG_VL_SENSE K VSSXG_VL_SENSE F V_IE_SENSE H RSV K RSV RSV V RSV T RSV0 RSV RSV Y RSV RSV Y RSV U RSV U RSV RSV RSV RSV0 RSV G RSV E RSV G RSV E RSV F RSV E RSV *K/F N *K/F N R R _TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_E E _TEST_E E _TEST_G G _TEST_G G _TEST_G G _TEST_G G _TEST_G G _TEST_E E _TEST_G G _TEST_E E _TEST_ K/F_ *K/F N *K/F N RSV E RSV G RSV0 N RSV L RSV L RSV L RSV M RSV M RSV U RSV W RSV P RSV T RSV0 K RSV H RSV G RSV M RSV M RSV N0 I,SN_G,P0 FG (PI-E Static x Lane Reversal) Normal Operation Lane Reversed FG (P Presence Strap) isable; No physical P attached to ep Enable; n ext P device is connected to ep Quanta omputer Inc. PROJET : SS Size ocument Number Rev Sandy ridge / ate: Monday, January 0, 0 Sheet of

9 ougar Point (MI,FI,PM) PH Pull-high/low(LG) U +.V_SUS () MI_RXN0 () MI_RXN () MI_RXN () MI_RXN () MI_RXP0 () MI_RXP () MI_RXP () MI_RXP () MI_TXN0 () MI_TXN () MI_TXN () MI_TXN () MI_TXP0 () MI_TXP () MI_TXP () MI_TXP +.0V_PH R R./F_ MI_OMP 0/F_ MIRIS E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRIS MI FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 J Y E H J G0 G G F G E G J0 H W V 0 V FI_TXN0 () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXP0 () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_INT () FI_FSYN0 () FI_FSYN () FI_LSYN0 () PM_RI# PM_TLOW# PIE_WKE# ME_SUS_PWR_K _PRESENT LKRUN# XP_RST# RSMRST# SYS_PWROK_R R R0 R R0 R R R R R R 0K_ 0K_ 0K_ 0K_ 0K_ +.V_RUN 0K_ 0K_ *K N 0K_ 00K_ FI_LSYN 0 FI_LSYN () () E_PWROK (,,) HWPG SYS_PWROK () PM_RM_PWRG () RSMRST# () ME_SUS_PWR_K () XP_RST# T SR R SR R SR *SJ00 *0 N *SJ00 ME_SUS_PWR_K XP_RST# PWROK_R SWVRMEN PIE_WKE# LKRUN# RSMRST# *0 N *SJ00 PWROK_R L0 PWROK +V_S SUSLK / GPIO N SUSLK T T T RMPWROK +V_S SLP_S# / GPIO 0 SIO_SLP_S# (,0) T RSMRST# ME_SUS_PWR_K K SYS_RESET# SYS_PWROK_R P SYS_PWROK L SUSK# PWROK RSMRST# System Power Management +V SWVRMEN PWROK WKE# LKRUN# / GPIO SLP_S# E K SUSWRN#/SUSPWRNK/GPIO0 +V_S SLP_S# F N +V_S SUS_STT# / GPIO G H RSMRST#_R SLP_S# SJ *SJ00 T PIE_WKE# (,) LKRUN# () T SIO_SLP_S# (,0) +RT_ELL R 0K_ SWVRMEN R *0K N On ie SW VR Enable High = Enable (efault) Low = isable () SIO_PWRTN# E0 PWRTN# SW SLP_# G0 () _PRESENT _PRESENT H0 PRESENT / GPIO SW SLP_SUS# G PM_TLOW# E0 TLOW# / GPIO+V_S PMSYNH P H_PM_SYN () PM_RI# 0 RI# +V_S SLP_LN# / GPIO K SIO_SLP_LN# T ougarpoint_rp0 S Power reduce +V_LW S Power reduce +V_LW SYS_PWROK(LG) +.V_SUS SIO_SLP_S# R0 *0K N R 0K_ PS_SNTRL Q N00W--F PS_SNTRL (,,) PS_SNTRL Q N00W--F R 00K_ PS_SNTRL_S () 0 *0.0U/V/XR N () SYS_PWROK U SYS_PWROK TSH0FU R *0.U/0V/XR N E_PWROK R 00K_ *0 N IMVP_PWRG (,) Quanta omputer Inc. PROJET : SS Size ocument Number Rev ougar Point / ate: Monday, January 0, 0 Sheet of

10 _IREF LVS_VG L_T L_LK IS_L_TRL_T IS_L_TRL_LK INT_P_HP INT_P_SL INT_P_S INT_P_HP IS_L_TRL_LK IS_L_TRL_T L_LK L_T ENV INT_P_SL INT_P_S LVS_IG +V_RUN +.V_RUN PNEL_KEN () L_PWM () L_LK () L_T () INT_P_HP_R () INT_P_SL () INT_P_S () INT_P_TXN_ () INT_P_TXP_ () INT_P_TXN_ () INT_P_TXP_ () INT_P_TXP_ () INT_P_TXN_ () INT_P_TXN0_ () INT_P_TXP0_ () INT_P_UXN_ () INT_P_UXP_ () INT_TXLLKOUTN () INT_TXLLKOUTP () INT_TXULKOUTN () INT_TXULKOUTP () INT_TXLOUTN0 () INT_TXLOUTP0 () INT_TXUOUTN0 () INT_TXUOUTP0 () INT_TXLOUTN () INT_TXLOUTP () INT_TXUOUTN () INT_TXUOUTP () INT_TXLOUTP () INT_TXLOUTN () INT_TXUOUTP () INT_TXUOUTN () ENV () Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ougar Point / Monday, January 0, 0 SS 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ougar Point / Monday, January 0, 0 SS 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ougar Point / Monday, January 0, 0 SS 0 ougar Point (LVS,I) ougar Point () Mini P LVS igital isplay Interface RT U ougarpoint_rp0 LVS igital isplay Interface RT U ougarpoint_rp0 L_KLTTL P L_KLTEN J L_TRL_LK T L_TRL_T P L LK T0 L T K L_V_EN M LVS_LK# K LVS_LK K0 LVS_T#0 N LVS_T# M LVS_T# K LVS_T# J LVS_T0 N LVS_T M LVS_T K LVS_T J LVS_LK# F0 LVS_LK F LVS_T#0 H LVS_T# H LVS_T# F LVS_T# F LVS_T0 H P_0N V P_N V LV_VREFH E LV_VREFL E P_N F P_N J P_N U P_N V P_0N Y P_N Y P_N P_N P_0N P_N F P_0P V0 P_P V P_P E P_P G P_P U P_P V LVS_T H LVS_T F LVS_T F LV_IG F LV_VG F P_P Y P_0P Y P_P P_P P_0P P_P E RT_LUE N RT LK T RT T M0 RT_GREEN P RT_HSYN M RT_IRTN T RT_RE T RT_VSYN M _IREF T SVO_TRLLK P SVO_TRLT M P_TRLLK P P_TRLT P P_TRLLK M P_TRLT M P_UXN T P_UXN P P_UXN T P_UXP T P_UXP P P_UXP T P_HP T0 P_HP T P_HP H SVO_TVLKINP P SVO_TVLKINN P SVO_STLLP M0 SVO_STLLN M SVO_INTP P0 SVO_INTN P R0.K/F_ R0.K/F_ T T R.K_ R.K_ T T R0 00K_ R0 00K_ UI ougarpoint_rp0 UI ougarpoint_rp0 VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] F0 VSS[00] F VSS[0] F VSS[0] F0 VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[0] F0 VSS[0] F VSS[0] F0 VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] K VSS[] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] M VSS[] P VSS[] M VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P0 VSS[] P VSS[] P VSS[0] T VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] W VSS[0] T VSS[0] T VSS[0] T VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] VSS[] VSS[0] VSS[] VSS[] E VSS[] E VSS[] G VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] H VSS[] H VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] N VSS[0] J VSS[] N VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] H VSS[] F VSS[] K VSS[] K VSS[] H VSS[0] K VSS[] K VSS[] VSS[] VSS[] E0 VSS[] G VSS[] G VSS[] H VSS[0] T VSS[] G VSS[] G VSS[] VSS[] P VSS[] F VSS[] H0 VSS[] M VSS[] P VSS[] P VSS[] E VSS[0] VSS[] G VSS[] J R.K_ R.K_ R.K_ R.K_ R *00K N R *00K N UH ougarpoint_rp0 UH ougarpoint_rp0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] F0 VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[0] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[0] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[0] P VSS[0] P VSS[] P VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U0 VSS[] V VSS[] V0 VSS[] V VSS[] V0 VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[0] W VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] V VSS[] Y VSS[] Y VSS[] Y VSS[0] VSS[] E VSS[] VSS[] P VSS[0] H VSS[] F VSS[] VSS[] VSS[] J VSS[] J VSS[] E VSS[] T VSS[0] T VSS[0] M VSS[] L VSS[] L R *00K N R *00K N R.K_ R.K_ R.K_ R.K_ Q SS--F Q SS--F R0 K_ R0 K_ R.K_ R.K_ T T

11 ougar Point (H,JTG,ST) +.V_RUN P/0V/0G_ P/0V/0G_ +RT_ELL () Z_ITLK_UIO () Z_SPKR (,) Z_RST#_UIO () Z_SIN0 () PH_MELOK () Z_SOUT_UIO Y.KHZ R () WWN_RIO_IS# R 0M_ T T T R M_ R _ T T 0 RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INTVRMEN P/0V/NPO_ Z_SYN_R Z_SPKR Z_RST#_R Z_SOUT WWN_RIO_IS# PH_JTG_TK PH_JTG_TMS PH_JTG_TI PH_JTG_TO P/0V/NPO_ K R _ Z_ITLK_R N R _ T0 T K_ T G L T0 K E G N J H K H U RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# RT IH JTG ST LP ST G FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# +V LRQ# / GPIO ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP H_SIN0 STRXN STRXP H_SIN STTXN STTXP H_SIN STRXN H_SIN STRXP STTXN STTXP H_SO STRXN STRXP H_OK_EN# / GPIO +V STTXN STTXP H_OK_RST# / GPIO +V_S STRXN STRXP STTXN JTG_TK STTXP JTG_TMS JTG_TI JTG_TO SERIRQ STIOMPO STIOMPI STROMPO STOMPI E K V M M P P M0 M P P0 H H 0 F F Y Y Y Y Y Y0 LP_LRQ0# LP_LRQ# IRQ_SERIRQ ST_OMP ST_OMP T T R R LP_L0 (,) LP_L (,) LP_L (,) LP_L (,) LP_LFRME# (,) IRQ_SERIRQ ()./F_./F_ +.0V_PH ST_RXN0 () ST_RXP0 () ST_TXN0 () ST_TXP0 () ST_RXN () ST_RXP () ST_TXN () ST_TXP () ST_RXN () ST_RXP () ST_TXN () ST_TXP () ST H/SS ST O EST IRQ_SERIRQ R ST_ET0# R WWN_RIO_IS# R PH JTG ebug (LG) PH_JTG_TMS PH_JTG_TI PH_JTG_TMS PH_JTG_TI PH_JTG_TK PH_JTG_TO RT_RST# SRT_RST# U/.V/XR_ 0K_ 0K_ 0K_ R 00_ R 00_ R 00_ R 00_ R _ R 00_ R 00_ 0K_ 0K_ U/.V/XR_ R R +.V_SUS +.V_SUS +RT_ELL (0) PH_SPI_LK (0) PH_SPI_S0# SJ PH_SPI_LK_R T *SJ00 Y SPI_LK SPI_S0# STRIS H ST_RIS R 0/F_ (0) PH_SPI_SI (0) PH_SPI_SO T SPI_S# V SPI_MOSI U SPI_MISO ougarpoint_rp0 SPI +V +V STLE# ST0GP / GPIO STGP / GPIO P V P ST_ET0# S_IT0 () Take care while using GPIO for Hot Plug function PH Strap Table Pin Name Strap description Sampled onfiguration note SPKR No reboot mode setting PWROK 0 = efault (weak pull-down 0K) = Setting to No-Reboot mode +.V_RUN R *K N Z_SPKR H_SO Flash escriptor Security PWROK 0 = efault (weak pull-down 0K) = Override +.V_SUS R0 *K N Z_SOUT INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up H_SYN On-ie PLL VR Volatge Select RSMRST 0 = Support by.v (weak P) = Support by.v +RT_ELL R () Z_SYN_UIO 0K_ R _ PH_INTVRMEN K_ R Z_SYN_R +.V_SUS Quanta omputer Inc. PROJET : SS Size ocument Number Rev ougar Point / ate: Monday, January 0, 0 Sheet of

12 PI/USO# Pull-up(LG) ougar Point-M (PI,US,NVRM) PLTRST#(LG) +.V_RUN 0K_ 0K_ 0K_ *0K N 0K_ 0K_ 0K_ 0KX 0K_ US_O# US_O# US_O# US_O# +.V_SUS () GPU_HOL_RST# () K_LE_ET () GPU_PWR_EN () PIE_MR_ET# () H_FLL_INT () ST_O_# (,) EXT_HMI_HP_Q () LK_M_LP () LK_M_K () LK_PI_F R R R R R R R R0 RP RP0 0 0KX PI_PIRQ# PI_PIRQ# PIE_MR_ET# GPU_PWR_EN PH_GPIO ST_O_# H_FLL_INT PI_PIRQ# PI_PIRQ# GPU_PWR_EN US_O# US_O0# SIO_EXT_WKE# US_O# T T R _ R _ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# GPU_PWR_EN S_IT PIE_MR_ET# PI_GNT# H_FLL_INT ST_O_# PH_GPIO PI_PME# PI_PLTRST# LK_M_K_R LK_PI_F_R UE G TP J TP H TP J TP G TP H TP H TP K TP K TP TP0 N0 TP H TP H TP M TP M TP Y TP K TP L TP TP TP0 TP M0 TP Y TP G TP E TP 0 TP E TP J TP TP E0 TP0 F TP G TP V TP TP U TP Y0 TP U TP Y TP V TP W0 TP0 RSV K0 PIRQ# +V K PIRQ# +V H PIRQ# +V G PIRQ# +V REQ# / GPIO0 +V REQ# / GPIO +V E0 REQ# / GPIO +V GNT# / GPIO +V E GNT# / GPIO +V F GNT# / GPIO +V G PIRQE# / GPIO +V G0 PIRQF# / GPIO +V PIRQG# / GPIO +V PIRQH# / GPIO +V K0 PME# PLTRST# H LKOUT_PI0 H LKOUT_PI J LKOUT_PI K LKOUT_PI H0 LKOUT_PI ougarpoint_rp0 PI US +V_S +V_S +V_S +V_S +V_S +V_S +V_S +V_S RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS O0# / GPIO O# / GPIO0 O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO0 O# / GPIO Y V U G T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 G0 E0 0 0 L K G E US_IS K0 US_O0# US_O# US_O# US_O# L US_O# US_O# US_O# SIO_EXT_WKE# R USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ ()./F_ US_O0# () SIO_EXT_WKE# () US &EST RIGHT WLN WWN amara GNT# / GPIO GPIO PI_PLTRST# Top-lock Swap Override +.V_SUS oot IOS Selection [bit-] oot IOS Selection 0 [bit-0] PI_GNT# PWROK PWROK PLTRST# Pin Name Strap description Sampled onfiguration GNT# / GPIO ESI strap (Server only) PWROK GNT# / GPIO R U0 *TSH0FU_N *K N SR0 *SJ00 PWROK 0 *0.U/0V/XR N R *00K N PLTRST# (,,0,,,,,) Should not be pull-down (weak pull-up 0K) 0 = "top-block swap" mode = efault (weak pull-up 0K) it 0 0 it 0 oot Location SPI LP * *0P/0V/0G N LK_M_LP *0P/0V/0G N LK_M_K () S_IT S_IT0 R R *K N *K N efault weak pull-up on GNT0/# [Need external pull-down for LP IOS] Quanta omputer Inc. PROJET : SS Size ocument Number Rev ougar Point / ate: Monday, January 0, 0 Sheet of

13 ougar Point-M (PI-E,SMUS,LK) U SMus/Pull-up(LG) () PIE_RXN () PIE_RXP WWN () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP WLN () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN US.0 () PIE_TXP (0) PIE_RXN (0) PIE_RXP ard Reader (0) PIE_TXN (0) PIE_TXP () PIE_RXN () PIE_RXP LN () PIE_TXN () PIE_TXP 0 0 () LK_PIE_WLNN WLN () LK_PIE_WLNP () PIE_LK_REQ# (0) LK_PIE_RN ard Reader (0) LK_PIE_RP () LK_PIE_WWNN WWN () LK_PIE_WWNP () PIE_LK_REQ# () LK_PIE_US0N US.0 () LK_PIE_US0P () PIE_LK_REQ# () LK_PIE_LNN LN () LK_PIE_LNP () PIE_LK_REQ# 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_LN_ PIE_TXP_LN_ PIE_LK_REQ0# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ# PEG LKRQ# PIE_LK_REQ# PIE_LK_REQ# G J V U E F Y G J V U F E Y G H Y J G U V G0 J0 Y0 0 E W Y Y0 Y J M V0 Y Y Y Y L V V L 0 E V0 V T V V K K K PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP PI-E* PIELKRQ0# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO0 PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO +V_S +V +V +V_S +V_S +V_S LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIO +V_S LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_ITPXP_N LKOUT_ITPXP_P +V_S +V_S +V_S +V_S +V_S SMLLERT# / PHHOT# / GPIO +V_S +V_S SMLLK / GPIO SMLT / GPIO LOKS SMUS ontroller Link +V_S +V +V +V FLEX LOKS +V SMLERT# / GPIO SMLK SMT SML0LERT# / GPIO0 SML0LK SML0T L_LK L_T L_RST# PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N LKOUT_P_P LKIN_MI_N LKIN_MI_P LKIN N LKIN P LKIN_OT_N LKIN_OT_P LKIN_ST_N LKIN_ST_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0 / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO E H G E M M T P0 PH_SM_LERT# SMLK SMT SML0LK SML0T PH_GPIO SM_LK_ME SM_T_ME M0 PEG LKRQ# V U M M F LK_MI E J0 LK_ G0 G LK_UF_REFLK E K LK_UF_REFSSLK K K LK_PH_M H LK_PI_F V XTL_IN V XTL_OUT Y XLK_ROMP R K F LK_FLEX0 LK_FLEX H LK_FLEX K LK_FLEX T T T T T R R R R0 R R_HVREF_RST_PH () 0./F_ 0K_ 0K_ 0K_ 0K_ 0K_ LK_PI_F () +.0V_PH PEG LKRQ# () LK_PIE_VGN () LK_PIE_VGP () LK_PU_LKN () LK_PU_LKP () LK_P_N () LK_P_P () R M_ Y MHz P/0V/NPO_ P/0V/NPO_ SMLK +.V_RUN SMT SM_LK_ME SM_T_ME Q MN0LW- RP.KX Q MN0LW- RP.KX Q MN0LW- PIE_LK_REQ0# PIE_LK_REQ# PIE_LK_REQ# PEG LKRQ# PH_GPIO R PH_SM_LERT# R SMLK R0 SMT R0 SML0LK R SML0T R WLN_SLK (,,,) WLN_ST (,,,) +.V_SUS SMLK () SMT () LK_REQ/Strap Pin(LG) PIE_LK_REQ# R PIE_LK_REQ# R PEG LKRQ# R PIE_LK_REQ# PIE_LK_REQ# R0 R PIE_LK_REQ# R Q MN0LW- R R R R R +.V_SUS 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ +.V_RUN 0K_ 0K_ +.V_SUS 0K_ *0K N 0K_ 0K_.K_.K_.K_.K_ +.V_SUS ougarpoint_rp0 Quanta omputer Inc. PROJET : SS Size ocument Number Rev ougar Point / ate: Monday, January 0, 0 Sheet of

14 ougar Point (GPIO,VSS_NTF,RSV) GPIO Pull-up/Pull-down(LG) UF () SIO_EXT_SMI# () SIO_EXT_SI# () SMI (0) PPE_N (,) GPU_PWROK () GPU_VREN () PIE_MR_ET# () US_MR_ET# () US_MR_ET# () MER_L_ET# () WLN_RIO_IS# () T_RIO_IS# () H_FLL_INT () MO_EN S_GPIO SIO_EXT_SMI# PH_GPIO SIO_EXT_SI# SMI PPE_N HOST_LERT# PH_GPIO R *0 N GPIO PIE_MR_ET# ROUSH_PI_TS_ET# PLL_OVR_EN US_MR_ET# US_MR_ET# MER_L_ET# FI_OVRVLTG WLN_RIO_IS# T_RIO_IS# H_FLL_INT MO_EN GPIO T H E 0 G U 0 T E E P K K V M N M V V MUSY# / GPIO0 +V TH / GPIO +V TH / GPIO +V TH / GPIO +V GPIO +V_S LN_PHY_PWR_TRL / GPIO GPIO +V_S STGP / GPIO +V TH0 / GPIO +V SLOK / GPIO +V GPIO / MEM_LE+V_S GPIO SW GPIO +V_S STP_PI# / GPIO +V GPIO +V STGP / GPIO +V STGP / GPIO +V SLO / GPIO +V STOUT0 / GPIO +V STOUT / GPIO +V STGP / GPIO +V GPIO +V_S GPIO +V +V +V +V +V_S PU/MIS TH / GPIO TH / GPIO TH / GPIO0 TH / GPIO 0GTE PEI RIN# PROPWRG THRMTRIP# INIT_V# F_TVS TS_VSS TS_VSS TS_VSS TS_VSS N_ VSS_NTF_ VSS_NTF_ VSS_NTF_ 0 0 P U P Y Y0 T Y H K H0 K0 P G G H PH_GPIO PH_GPIO PH_GPIO0 PH_GPIO SIO_0GTE SIO_RIN# PH_THRMTRIP# R 0_ R.K_ SIO_0GTE () H_PEI () SIO_RIN# () H_PWRGOO () PM_THRMTRIP# () +.V_RUN SMI PPE_N GPIO PH_GPIO SIO_EXT_SMI# SIO_EXT_SI# MO_EN SIO_0GTE SIO_RIN# H_FLL_INT US_MR_ET# US_MR_ET# T_RIO_IS# S_GPIO PH_GPIO PIE_MR_ET# WLN_RIO_IS# PH_GPIO PH_GPIO PH_GPIO0 PH_GPIO R0 R R0 R R R0 R R R0 R R R R R R R0 R0 R0 R0 R0 R0 ROUSH_PI_TS_ET# R0 GPIO R *0K N 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ *0K N 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ +.V_SUS +.V_RUN VSS_NTF_ H VSS_NTF_ VSS_NTF_ J VSS_NTF_ VSS_NTF_0 J VSS_NTF_ VSS_NTF_ J VSS_NTF_ VSS_NTF_ NTF VSS_NTF_ VSS_NTF_ J J VSS_NTF_ VSS_NTF_ J VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ E VSS_NTF_ VSS_NTF_ E E VSS_NTF_ VSS_NTF_0 E F VSS_NTF_ VSS_NTF_ F F VSS_NTF_ VSS_NTF_ F ougarpoint_rp0 +.V_RUN R0 *K/F N FI_OVRVLTG R 00K_ Pin Name Strap description Sampled onfiguration FI TERMINTION VOLTGE OVERRIE LOW - Tx, Rx terminated to same voltage GPIO On-die PLL Voltage Regulator RSMRST# 0 = isable = Enable (efault) R *K N PLL_OVR_EN +.V_RUN R MI TERMINTION VOLTGE OVERRIE 00K_ MER_L_ET# Low = Tx, Rx terminated to same voltage ( oupling Mode) (EFULT) GPIO Intel ME rypto Transport Layer Security (TLS) cipher suite HOST_LERT# R RSMRST# K_ 0 = isable (efault) = Enable +.V_SUS Quanta omputer Inc. PROJET : SS Size ocument Number Rev ougar Point / ate: Monday, January 0, 0 Sheet of

15 +.0V_VIO +.0V_PH VccORE =.(0mils) need 0? L0 +.0V_PH +.V_RUN +.0V_VIO VccIO =. (0mils) +.0V_VIO +VFI_VRM +.V_V_MI +.V_RUN V_V_EXP +VFI_VRM +.0V_PH_V +.0V_VPLL_EXP Near to N, P, N SJ VccVRM(.V) =0. (0mils) R 0 SJ *uh/m N *0U/.V/XR N VccMI =0.0 (0mils) 0.U/0V/XR_ *0 N 0U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ *SJ_00 *SJ_0 +.0V_VPLL_FI F F G G G G G G J J J J J N J N N N N N P P P P T N N H P G P U0 OUGR POINT (POWER) UG VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[0] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VccFIPLL VIO[] VMI[] ougarpoint_rp0 POWER V ORE VIO FI RT LVS FT / SPI MI HVMOS V VSS VLVS VSSLVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] VVRM[] VMI[] VLKMI VFTERM[] VFTERM[] VFTERM[] VFTERM[] VSPI U U K K M M P P V V T T0 G G J J V Vcc =m(mils) +V R SJ VccLVS=m (mils) VccTX_LVS=0m (0mils) +V_V_GIO +VFI_VRM +.V_V_MI SJ +.V_V_MI_I +VP_NN SJ L +V_VME_SPI *0 N +VLVS +VFI_VRM 0U/.V/XR_ 0.U/0V/XR_ 0.0U/V/XR_ 0U/.V/XR_ 0.0U/V/XR_ 0.0U/V/XR_ SJ SJ V_RUN +V_TX_LVS *SJ_00 SJ SJ *SJ_00 0.U/0V/XR_ *SJ00 U/.V/XR_ *SJ_00 +.V_RUN +.0V_PH 0uH/00m_ U/.V/XR_ 0.U/0V/XR_ +.V_RUN +.V_RUN +.V_RUN Vcc_ = 0. (mils) VccMI = 0m (0mils) +.0V_PH VccLKMI = 0m (mils) +.V_RUN VSPI = 0m(mils) *SJ_00 +.0V_PH U/.V/XR_ *SJ00 *SJ_00 +.0V_PH VPNN = 0 m(mils) SJ SJ SJ 0 +.0V_PH +.V_SUS +.0V_VIO L *SJ_00 *SJ_00 U/.V/XR_ U/.V/XR_ *SJ_00 U/.V/XR_ R VccSW_= m(mil) SJ0 *0uH/00m N 0 +.0V_PH 0.U/0V/XR_ *0.U/0V/XR N *0U/.V/XR N SJ +VPLL_PY_PH *U/.V/XR N VccSW =.0 (0mils) 0 +VFI_VRM U/.V/XR_ U/.V/XR_ U/.V/XR_ 0m(0mils) 0m(0mils) 0U/.V/XR_ 0U/.V/XR_ +VLK +VPSW PH_VSW +V_SUS_LKF +VSUS +.0V_VEPW +VRTEXT +VFI_VRM +.0V_V PL +.0V_V PL +VIFFLK +VIFFLKN VIFFLKN= m(mils,pg) +V.0V_SSV VSS= m(0mils) *0 N *SJ00 *SJ_0 0.U/0V/XR_ 0.U/0V/XR_ +VSST ougar Point (POWER) T V T H L L W W W W W W W N Y F F F F G G V UJ VLK VSW_ PSUSYP V_[] VPLLMI VIO[] PSUS[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] PRT VVRM[] VPLL VPLL VIO[] VIFFLKN[] VIFFLKN[] VIFFLKN[] VSS PSST POWER lock and Miscellaneous ST PI/GPIO/LP US VIO[] VIO[0] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VIO[] VREF_SUS PSUS[] VSUS_[] VREF VSUS_[] VSUS_[] VSUS_[] VSUS_[] V_[] V_[] V_[] V_[] VIO[] VIO[] VIO[] VIO[] VPLLST VVRM[] VIO[] VIO[] VIO[] N P P T T T T V V P T M N N P N0 N P0 P W T J F H H F K F +V_VPUS +V_VUG +V_PH_VREFSUS +V_USSUS +V_VPSUS +V_PH_VREF +V_VPSUS +V_VPORE +V.LN_VPLL +VFI_VRM 0 VSUS_ = m (mils) SJ0 R L R 0 SJ SJ 0.U/0V/XR_ 0.U/0V/XR_ 0 U/.V/XR_ SJ +.0V_VIO +.V_RUN +.V_RUN +.0V_VIO VVRM= m(mils) U/.V/XR_ +.0V_VIO *SJ_00 0.U/0V/XR_ 0.U/0V/XR_ +.V_SUS +.0V_VIO VREFSUS=m(mil) 0/F_ +V_SUS R00V-0 0.U/0V/XR_ *U/.V/XR N 0/F_ R00V-0 U/.V/XR_ U/.V/XR_ *SJ_00 *SJ_00 U/.V/XR_ +.V_SUS VREF= m(mil) +V_RUN +.V_RUN VSUS_ = m (mils) +.V_SUS VPORE = m(0mils) *SJ_00 +.V_RUN 0.U/0V/XR_ *0uH/00m N *0U/.V/XR N +.0V_PH SJ *SJ_00 +.0V_PH SJ *Short Jump_0 +VFI_VRM +.0V_VIO +.0V_PH R *0 N +V.0M_VSUS *U/.V/XR N m(mils) +.0V_PH SJ *SJ00 +VTT_VPPU.U/.V/XR_ 0.U/0V/XR_ *0.U/0V/XR N VRT<m(mils) +RT_ELL U/.V/XR_ 0.U/0V/XR_ *0.U/0V/XR N T PSUS[] V PSUS[] J V_PRO_IO VRT ougarpoint_rp0 PU RT MIS H VSW[] VSW[] VSW[] VSUSH T +.0V_VEPW V T VSUSH= 0m(mils) P +V._._H_IO SJ *SJ00 +.V_SUS 0.U/0V/XR_ +.V_RUN +.0V_PH L L 0uH/00m_ 0uH/00m_ 0U/.V/XR_ +.0V_V PL U/.V/XR_ +.0V_V PL R R *0 N /F_ +V_SUS_LKF_L L 0uH/00m_ 0U/.V/XR_ +V_SUS_LKF U/.V/XR_ 0U/.V/XR_ U/.V/XR_ Quanta omputer Inc. PROJET : SS Size ocument Number Rev ougar Point / Monday, January 0, 0 ate: Sheet of

16 Quanta omputer Inc. PROJET : SS Size ocument Number Rev LNK ate: Monday, January 0, 0 Sheet of

17 M 0 M M M M M M 0 M M M M M M M M M M QSP0 M QSN0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q IMM0_S0 IMM0_S M Q M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN +SMR_VREF_Q0 +SMR_VREF_IMM0 +.V_SUS +.V_RUN +0.V_R_VTT +.V_RUN +.V_RUN +.V_SUS +0.V_R_VTT +SMR_VREF_IMM0 +SMR_VREF_Q0 +.V_SUS +0.V_R_VTT +SMR_VREF_IMM0 +SMR_VREF_Q0 +.V_SUS +R_VTTREF +SMR_VREF_IMM0 +.V_SUS +R_VTTREF +SMR_VREF_Q0 +0.V_R_VTT M S#0 () M S# () M S# () M S#0 () M S# () M LKP0 () M LKP () M LKN0 () M LKN () M KE0 () M KE () M S# () M RS# () M WE# () M [:0] () M Q[:0] () WLN_SLK (,,,) WLN_ST (,,,) M OT0 () M OT () M QSP[:0] () M QSN[:0] () R_RMRST# (,) PS_SNTRL (,,) Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Monday, January 0, 0 SS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Monday, January 0, 0 SS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Monday, January 0, 0 SS SO-IMM SP ddress is 0X0 SO-IMM TS ddress is 0X0 Place these aps near So-imm0. For RF noise For RF noise M VREF S Power reduce *0.U/0V/XR N *0.U/0V/XR N 0.U/0V/XR_ 0.U/0V/XR_ P00 R SRM SO-IMM (0P) JIM SUY_000F0G0ZL GMK0000 ddr--00-rvs-0p P00 R SRM SO-IMM (0P) JIM SUY_000F0G0ZL GMK0000 ddr--00-rvs-0p V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 G 0 G 0 H 0 H 0 0 U/.V/XR_ 0 U/.V/XR_ R K/F_ R K/F_ R0 K/F_ R0 K/F_ 0 0U/.V/XR_ 0 0U/.V/XR_ *P/0V/NPO N *P/0V/NPO N RP 0KX RP 0KX *P/0V/NPO N *P/0V/NPO N *P/0V/NPO N *P/0V/NPO N 0U/.V/XR_ 0U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ *P/0V/NPO N *P/0V/NPO N U/.V/XR_ U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ *P/0V/NPO N *P/0V/NPO N 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ R *0 N R *0 N 0U/.V/XR_ 0U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ *0.U/0V/XR N *0.U/0V/XR N.U/.V/XR_.U/.V/XR_ 0 0.U/0V/XR_ 0 0.U/0V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ *P/0V/NPO N *P/0V/NPO N *0U/.V/XR N *0U/.V/XR N Q N00W--F Q N00W--F 0.U/0V/XR_ 0.U/0V/XR_ U/.V/XR_ U/.V/XR_ R K/F_ R K/F_ R K/F_ R K/F_ *P/0V/NPO N *P/0V/NPO N 0U/.V/XR_ 0U/.V/XR_ *0.U/0V/XR N *0.U/0V/XR N R *0 N R *0 N R *0K N R *0K N P00 R SRM SO-IMM (0P) JIM SUY_000F0G0ZL ddr--00-rvs-0p GMK0000 P00 R SRM SO-IMM (0P) JIM SUY_000F0G0ZL ddr--00-rvs-0p GMK /P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q.U/.V/XR_.U/.V/XR_ R _ R _ U/.V/XR_ U/.V/XR_ *.U/.V/XR N *.U/.V/XR N

18 M Q M Q M Q M Q M M Q M Q M Q M Q M QSN0 M 0 M M M M Q M Q M Q M Q M Q M Q IMM_S0 M M Q M Q M Q M Q M Q M Q0 M M M Q M M M Q M Q M Q M Q0 M M 0 M Q M Q M M Q M Q M Q M Q M Q M Q M Q M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M QSP0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q0 M Q M IMM_S M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN +SMR_VREF_IMM +SMR_VREF_Q +.V_RUN +.V_SUS +.V_RUN +0.V_R_VTT +.V_RUN +.V_RUN +SMR_VREF_Q +.V_SUS +0.V_R_VTT +SMR_VREF_IMM +.V_SUS +0.V_R_VTT +SMR_VREF_IMM +SMR_VREF_Q +.V_SUS +R_VTTREF +SMR_VREF_IMM +.V_SUS +R_VTTREF +SMR_VREF_Q M [:0] () M WE# () M S#0 () M LKP () M LKN0 () M S# () M S#0 () M KE () M S# () M LKN () M S# () M RS# () M S# () M LKP0 () M KE0 () WLN_SLK (,,,) WLN_ST (,,,) M OT0 () M OT () M QSP[:0] () M QSN[:0] () R_RMRST# (,) M Q[:0] () Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Monday, January 0, 0 SS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Monday, January 0, 0 SS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Monday, January 0, 0 SS SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X Place these aps near So-imm. For RF noise For RF noise M VREF.U/.V/XR_.U/.V/XR_ *P/0V/NPO N *P/0V/NPO N 0U/.V/XR_ 0U/.V/XR_ 0 0.U/0V/XR_ 0 0.U/0V/XR_ 0 U/.V/XR_ 0 U/.V/XR_ U/.V/XR_ U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ *0.U/0V/XR N *0.U/0V/XR N *P/0V/NPO N *P/0V/NPO N 0.U/0V/XR_ 0.U/0V/XR_ 0U/.V/XR_ 0U/.V/XR_ *0.U/0V/XR N *0.U/0V/XR N R *0 N R *0 N *0.U/0V/XR N *0.U/0V/XR N *P/0V/NPO N *P/0V/NPO N R K/F_ R K/F_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ *P/0V/NPO N *P/0V/NPO N U/.V/XR_ U/.V/XR_ R *0 N R *0 N U/.V/XR_ U/.V/XR_.U/.V/XR_.U/.V/XR_ 0 *0U/.V/XR N 0 *0U/.V/XR N 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ R K/F_ R K/F_ P00 R SRM SO-IMM (0P) JIM S0-JR-H P00 R SRM SO-IMM (0P) JIM S0-JR-H V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 G 0 G 0 H 0 H 0 R0 K/F_ R0 K/F_ P00 R SRM SO-IMM (0P) JIM S0-JR-H GMK000 ddr-as0a-urn-f-0p-ruv P00 R SRM SO-IMM (0P) JIM S0-JR-H GMK000 ddr-as0a-urn-f-0p-ruv 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 00 *.U/.V/XR N 00 *.U/.V/XR N *P/0V/NPO N *P/0V/NPO N R 0K_ R 0K_ *P/0V/NPO N *P/0V/NPO N 0U/.V/XR_ 0U/.V/XR_ 0 0.U/0V/XR_ 0 0.U/0V/XR_ R K/F_ R K/F_ R *0K N R *0K N 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ R 0K_ R 0K_ *P/0V/NPO N *P/0V/NPO N 0 0.U/0V/XR_ 0 0.U/0V/XR_

19 +.0V_GFX PEX_IOV+PEX_IOVQ >. +.0V_GFX +.0V_GFX +V_GFX ~ mils width 0m 0.u under GPU Others Near GPU V_GFX ~ 00m 00m 0.u * under GPU Others Near GPU 0.u under GPU Others Near GPU 0 0 +V_GFX_ORE L LMGSN (0,00M) 0.U/0V/XR_ U/.V/XR_.U/.V/XR_ *0.U/0V/XR N 0.U/0V/XR_ U/.V/XR_ U/.V/XR_.U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ +.0V_GFX 0m ~ mils width *0.U/0V/XR N *0.U/0V/XR N 0.U/0V/XR_ 0.U/0V/XR_ U/.V/XR_ U/.V/XR_.U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_.U/.V/XR_ U/.V/XR_ 0.u under GPU Others Near GPU U NP-GE K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_0 G PEX_IOVQ_ G PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_0 K PEX_IOVQ_ K0 PEX_IOVQ_ K PEX_IOVQ_ K PEX_IOVQ_ L PEX_IOVQ_ J0 V_ J V_ J V_ J V_ J V_ 0 V_SENSE N_/ V_SENSE P N_/ V_SENSE _SENSE E N_0/ _SENSE R N_/ _SENSE +PEX_PLLV G PEX_PLLV PI EXPRESS L 0_ +PEX_SV_V G 0.U/0V/XR_ PEX_L_P_VQ/ PEX_SV_V F.U/.V/XR_ N_/ PEX_SV_V 0.U/0V/XR_ G0 PEX_PLL_HV_N N_ N_ N_ F N_ G N_ J N_ K N_ L N_ E N_ H N_ P N_ U N_ V N_ PEX_RX0 PEX_RX0* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX0 PEX_RX0* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_TX0 PEX_TX0* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX0 PEX_TX0* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_REFLK PEX_REFLK* PEX_TSTLK_OUT PEX_TSTLK_OUT* PEX_RST* PEX_LKREQ* PEX_TERMP TESTMOE P PEG_TXP N PEG_TXN N PEG_TXP P PEG_TXN R PEG_TXP R0 PEG_TXN P0 PEG_TXP N0 PEG_TXN N PEG_TXP P PEG_TXN R PEG_TXP0 R PEG_TXN0 P PEG_TXP N PEG_TXN N PEG_TXP P PEG_TXN R PEG_TXP R PEG_TXN P PEG_TXP N PEG_TXN N PEG_TXP P PEG_TXN R PEG_TXP R PEG_TXN P PEG_TXP N PEG_TXN N PEG_TXP P PEG_TXN R PEG_TXP R PEG_TXN R PEG_TXP0 P PEG_TXN0 L PEG_RXP_ M PEG_RXN_ M PEG_RXP_ M PEG_RXN_ L PEG_RXP_ K PEG_RXN_ L0 PEG_RXP_ M0 PEG_RXN_ M PEG_RXP_ M PEG_RXN_ L PEG_RXP0_ K PEG_RXN0_ L PEG_RXP_ M PEG_RXN_ M PEG_RXP_ M PEG_RXN_ L PEG_RXP_ K PEG_RXN_ L PEG_RXP_ M PEG_RXN_ M PEG_RXP_ M PEG_RXN_ L PEG_RXP_ K PEG_RXN_ K PEG_RXP_ L PEG_RXN_ M PEG_RXP_ M0 PEG_RXN_ M PEG_RXP_ M PEG_RXN_ N PEG_RXP0_ P PEG_RXN0_ R R LK_PIE_VGP LK_PIE_VGN J PEX_TSTLK R J PEX_TSTLK# M GPU_RST# R PEX_LKREQ# G PEX_TERMP P TESTMOE R R PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP0 () PEG_TXN0 () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP0 () PEG_TXN0 () 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ *00 N R.K/F_ 0K_ GPU all PWROK +.V_GFX Q: H(sat), L(cut-off) PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP0 () PEG_RXN0 () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP0 () PEG_RXN0 () LK_PIE_VGP () LK_PIE_VGN () 0K_ +V_GFX Q PTTT +.V_RUN R 00K_ +V_GFX R 0K_ 00P/V/XR_ Q N00W--F GPU_PWROK (,) Power up sequence V +V_GFX PEX_V +.0V_GFX NVV +V_GFX_ORE IFP_IOV +.V_GFX FVQ +.V_GFX NVV GPIO PEX_RST NM: VGORE +0.0V (Normal), +.0V I/O.V t>0 tsnvv<= us Trise >= us t>0 t>0 Tfail <=00nS for Nvidia request add transition cap +V_GFX 0.U/0V/XR_ +V_GFX GPU_RST# R 00K_ U0 TSH0FU R 00K_ PLTRST# (,,0,,,,,) GPU_HOL_RST# () PEX_LKREQ# Q N00W--F PU in PH PEG LKRQ# () Quanta omputer Inc. PROJET : SS Size ocument Number Rev NP-GE (PIE I/F) / ate: Monday, January 0, 0 Sheet of

20 VM_Q VM_M VM_M F_L_P_VQ F_L_PU_ F_L_TERM_ +F_VREF VM_M VM_M0 VM_M VM_M0 VM_M VM_M VM_M VM_M0 VM_M0 VM_M F_EUG F_EUG VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_LKN VM_LKP0 VM_LKN0 VM_LKP +F_PLLV +F_PLLV VM_RQS VM_RQS VM_RQS VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_WQS VM_WQS VM_WQS VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_M VM_M VM_M VM_M0 VM_M VM_M VM_M VM_M VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_LKN VM_LKP0 VM_LKN0 VM_LKP VM_RQS VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_WQS VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_M VM_M VM_M VM_M VM_M VM_M VM_M F_EUG0 F_EUG0 VM_M0 VM_M VM_M VM_M VM_M +.V_GFX +.V_GFX +.0V_GFX +.0V_GFX +.V_GFX +.V_GFX +.V_GFX +.V_GFX VM_M0 () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M0 () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M0 () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M0 () VM_Q[..0] () VM_M[..0] () VM_WQS[..0] () VM_RQS[..0] () VM_Q[..0] () VM_M[..0] () VM_WQS[..0] () VM_RQS[..0] () VM_M0 () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M0 () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M0 () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M () VM_M0 () VM_LKP0 () VM_LKN0 () VM_LKP () VM_LKN () VM_LKP0 () VM_LKN0 () VM_LKP () VM_LKN () Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : NP-GE (MEMORY I/F) / Monday, January 0, 0 SS 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : NP-GE (MEMORY I/F) / Monday, January 0, 0 SS 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : NP-GE (MEMORY I/F) / Monday, January 0, 0 SS 0 mils width For ebug only ll need stuff for NP 0.u * under GPU Others Near GPU mils width 00m 00m Follow Mode E ommand Mapping (OTX, KE*, RST) 00m T T U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ R 0K_ R 0K_ MEMORY I/F F_M F_M F_M F_M0 F_M0 F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 N/ F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M GF0 GTX U NP-GE MEMORY I/F F_M F_M F_M F_M0 F_M0 F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 N/ F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M GF0 GTX U NP-GE F_WK_N G F_WK G F_WK_N G F_WK G F_WK0_N G F_WK0 G F_WK_N G F_WK G F_QS_RN F_QS_RN F_QS_RN F_QS_RN F F_QS_RN0 F_QS_RN E F_QS_RN 0 F_QS_RN F_QS_WP F_QS_WP F_QS_WP F_QS_WP E F_QS_WP0 F_QS_WP F_QS_WP 0 F_QS_WP E0 F_QM F_QM F_QM F_QM F_QM0 F_QM F_QM 0 F_QM F F_L_TERM_ M F_L_PU_ L F_L_P_VQ K F_EUG0_S G F_LK* E F_LK F_LK0* F_LK0 E FVQ_ Y FVQ_ W FVQ_ V FVQ_ V FVQ_ V FVQ_ U FVQ_ U FVQ_ T FVQ_0 R FVQ_ P FVQ_ N F_ F_ E F_ F0 F_ F_ F F_ F F_ E F_0 F F_0 F_0 F_ F_ F_ F_ F_0 F_ 0 F_ F_ E F_ F F_ F F_0 F F_ E F_ F F_ F F_0 F_0 F_00 F_0 F_0 F_0 F_0 F_0 F_ F_ F_ E F_ F F_ F F_ E F_ F F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ E F_ F F_ 0 F_ E F_ F_ F_ F F_0 E F_ F_0 F_ F_ F_ F_ F_ F_ F_M F_M F_M F_M F F_M F_M F_M F_M E0 F_M G F_M F0 F_M F F_M F F_M F_M F_M F_M F F_M F_M E F_M 0 F_M F_M0 F_M F_M 0 F_M E F_M F_M0 F F_M F_M F F_M0 F_M 0 F_M0 0 F_M G0 F_EUG G R 0./F_ R 0./F_ U/.V/XR_ U/.V/XR_ R 0K_ R 0K_ R 0K_ R 0K_ R *0./F N R *0./F N 0.U/0V/XR_ 0.U/0V/XR_ R 0K_ R 0K_ R 0K_ R 0K_ 0.U/0V/XR_ 0.U/0V/XR_ R *0K N R *0K N 0.U/0V/XR_ 0.U/0V/XR_ R 0K_ R 0K_ R *0K N R *0K N T T 0 0U/.V/XR_ 0 0U/.V/XR_ T T R 0./F_ R 0./F_ T T R *0./F N R *0./F N R 0K_ R 0K_ R 0K_ R 0K_ R 0K_ R 0K_ T T L0 PY00T-00Y-N L0 PY00T-00Y-N 0 0.U/0V/XR_ 0 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ T T L PY00T-00Y-N L PY00T-00Y-N.U/.V/XR_.U/.V/XR_ R 0K_ R 0K_ T T 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_.U/.V/XR_.U/.V/XR_ U/.V/XR_ U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ MEMORY I/F RUF RUF GTx GF0 F_M F_M F_M F_M0 F_M0 F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 N/ F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M GF0 GTX GTx GF0 F_VREF U NP-GE MEMORY I/F RUF RUF GTx GF0 F_M F_M F_M F_M0 F_M0 F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 N/ F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M GF0 GTX GTx GF0 F_VREF U NP-GE F_VREF_N J F_WK_N H F_WK G F_WK_N E F_WK F_WK_N M F_WK L F_WK0_N R F_WK0 P F_QS_RN J F_QS_RN J F_QS_RN F_QS_RN F_QS_RN G F_QS_RN H F_QS_RN0 L F_QS_RN N F_QS_WP J F_QS_WP J F_QS_WP F_QS_WP E F_QS_WP H F_QS_WP J F_QS_WP0 L F_QS_WP N F_QM L F_QM L F_QM F F_QM F F_QM H F_QM J0 F_QM0 P F_QM P0 F_PLLV0 F F_LLV0 G F_EUG0_S T0 F_LK* 0 F_LK F_LK0* T F_LK0 T F_ R0 F_0 R F_ P F_ N0 F_ L F_ M F_ M0 F_ L0 F_0 P F_0 P F_0 N F_0 P F_0 N F_0 L F_00 L F_0 N F_ K F_0 K0 F_ G0 F_ K F_ G F_ H0 F_ F0 F_ G F_ H F_0 K F_0 K F_ G F_0 K F_ E F_ E F_ G F_ G0 F_ H F_ G F_ F F_ F0 F_ 0 F_ F_ E0 F_ E F_ F F_ F F_ E F_ E F_0 E F_ F_ F_0 N F_ K F_ L F_ M F_ L F_ K0 F_ J0 F_ H0 F_ M F_ H F_ H F_ H F_0 H F_ M F_ L F_ J F_M V F_M W F_M U F_M Y F_M F_M F_M W F_M W F_M W0 F_M T F_M T F_M F_M Y0 F_M Y F_M W F_M 0 F_M F_M Y F_M U F_M Y F_M0 U F_M Y F_M W F_M V0 F_M U F_M0 U0 F_M U F_M 0 F_M0 F_M T F_M0 W FVQ_ J FVQ_ J FVQ_ J FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ E FVQ_ J FVQ_0 FVQ_ E FVQ_ G FVQ_ G FVQ_ G FVQ_ G FVQ_ G FVQ_ H FVQ_ J FVQ_ J FVQ_0 J FVQ_ J FVQ_ J0 FVQ_ J FVQ_ J F_EUG T F_LLV J F_PLLV J F_M Y 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ R 0./F_ R 0./F_