Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09
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1 Table of ontents Notes F & PL MRM, S & SFLSH OPTIONL PORT Rev X0 escription onvert into FSL template Revisions X ll parts FL //0 X Replaced U with the correct part //0 X X Replaced some components with similar per Micetek suggestion dded a Jumper on S WR per U request ate //0 //0 //0 pproved ESIGNER X Replaced S part with shorter one //0 X Replaced S/MM connector 0/0/0 Released to Fab 0//0 dd J, J and J per customer req Released to fab 0//0 Replace with alternate part LEs //0 Microcontroller Solutions Group 0 William annon rive West ustin, TX - This document contains information proprietary to Freescale Semiconductor and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale Semiconductor. IP lassification: FP: _ PUI: _ esigner: rawing Title: Rodolfo G rawn by: Rodolfo G Table of contents pproved: Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
2 . Unless Otherwise Specified: ll resistors are in ohms, %, / Watt ll capacitors are in uf, 0%, 0V ll voltages are ll polarized capacitors are aluminum electrolytic. Interrupted lines coded with the same letter or letter combinations are electrically connected.. evice type number is for reference only. The number varies with the manufacturer.. Special signal usage: _ enotes - ctive-low Signal <> or [] enotes - Vectored Signals. Interpret diagram in accordance with merican National Standards Institute specifications, current revision, with the exception of logic block symbology. IP lassification: FP: PUI: rawing Title: NOTES Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
3 Pg F_[:0] F_[:0] U F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 0 IO IO IO IO IO IO IO IO IO IO IO IO IO 0 IO IO IO IO IO IO 0 IO IO IO IO IO IO IO IO 0 IO IO IO IO IO IO 0 IO F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_0 F_0_ F_R/W_ R 0K F_[:0] F_0_ Pg F_R/W_ Pg F_LE/F_S_ F_[:0] Pg efault: Shunted F_S0_ Pg Pg J HR X TH EPM0GT00N HR TH X J U IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 0 0 IO IO IO 0 IO IO IO IO IO IO F_IOR_ IO F_IOWR_ IO IO IO IO IO IO IO IO IO IO IO IO IO IO 0 IO IO IO IO IO IO IO IO F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_OE_ F_WIT_ F_REG_ F_E_ F_WE_ F_ F_ F_REY F_RST_ F_[0:0] + 0.UF 0uF F_ F_ F_E_ F_OE_ F_WE_ F_REY F_RST_ F_REG_ J V V E E OE WE RY/SY SEL RESET REG F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_[0:0] EPM0GT00N J IO IO IO IO IO 0 IO IO 0 IO IO GLK 0 IO IO IO IO IO IO IO IO IO GLK0 F_IOR_ F_IOWR_ F_WIT_ 0 0 IOR IOWR V V VS 0 VS WIT INPK 0 F ONNETOR 0 F_ F_ F_ F_ F_ F_ F_ F_0 F_[:0] F_[:0] Pg HR_X 0.UF NP PL ONNETIONS F HEER Pg Pg F_LK GLK0 GLK F_LK U GLK0/IO GLK/IO GLK/IO GLK/IO INT INT 0 IO IO 0 IO IO IO IO VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VINT VINT 0 _ TO_ TI_ TK_ IO /EV_OE IO /EV_LR TO TI TK F_OE_ RST_ 0.UF F_OE_ RST_ 0.UF 0.UF 0.UF + 0.UF 0.UF 0uF Pg Pg UF 0.UF 0uF U VV VOUT VIN T + 0uF 0.UF LS 0.UF J F_ F_ F_ F_0 0 F_IOR_ F_IOWR_ F_WE_ F_REY F_ 0 F_RST_ F_WIT_ F_ F_0 F_ 0 F_ F_ F_ F_E_ F_OE_ F_ F_ F_ F_ F_ F_ F_ F_REG_ F_0 F_ F_ EPM0GT00N 0.UF J 0 HR X R K R K TK TO TI TO TI TK HR_X JTG[:] J JTG[:] Pg JTG JTG JTG JTG PL EOUPLING & JTG HR_X NP OPTIONL WIRE WRP HEERS IP lassification: FP: PUI: rawing Title: F & PL Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
4 00 0.UF UF 0uF efault: Open F_S0_ HR X TH F_R/W_ S_R_ET S ET J HR X TH J0 F_[:0] S_PU R 0K J HR X TH S ET_J R 0K R 0K F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_OE_ F_0 F_0_ R 0K R0 0K S_PU R0 0K S_M/MOSI S_[0]/MISO S_[] S_[] R0 R0 0K R0 0K 0K U 0 0 E G W U L J0 P_ P_ V V mraa VSS VSS S/MM SKT QL0 QL QL QL QL QL QL QL QU QU QU0 QU QU QU QU QU U? MRYS F_0 F_ F_ F_ F_ F_ F_ F_ S_PU S_PU S_PU S_PU S_SEL S_[] S_SEL S_[] _IRQ _IRQH S_R_ET LK M T0 T T T V 0 0 N S_LK/SLK S_M/MOSI S_[0]/MISO S_[] S_[] S_[]/S F_[:0] MRM J 0 JTG GPIO IRQ IRQH HR_X efault:, R00 00K efault: Open Pg F_[:0] S_LK/SLK S_[]/S J HR TH X efault:, JTG GPIO JTG F_LK Pg F_LK LKOUT0 J efault:, HR TH X Pg F_LE/F_S_ F_S0_ Pg F_S0_ F_ F_ F_ F_ F_ F_R/W_ Pg F_R/W_ F_OE_ F_ Pg F_OE_ F_[:0] F_ F_ F_ F_ F_ F_ F_0 S_M/MOSI S_[0]/MISO LKOUT SF_MISO SF_MOSI SF_S SF_S SF_LK GPIO IRQH IRQ J00 V.V_ ELE_PS_SENSE _ SPI_LK/SH_LK SPI_S_/SH_ SPI_S0_/SH_ SPI_MOSI/SH_M SPI_MISO/SH_0 ETH_OL_ ETH_RXER_ ETH_TXLK_ ETH_TXEN_ ETH_TXER_ ETH_TX_ ETH_TX_ ETH_TX_ ETH_TX0_ GPIO/RTS GPIO/SH_ GPIO LKIN0 LKOUT _ N N N N _ TMR TMR GPIO.V_ PWM PWM PWM PWM NRX0 NTX0 WIRE SPI0_MISO SPI0_MOSI SPI0_S0_ SPI0_S_ SPI0_LK _ SL S GPIO/S_R_ET US0_P_POWN US0_M_POWN IRQ_H IRQ_G IRQ_F IRQ_E IRQ_ IRQ_ IRQ_ IRQ_ EI_LE/EI_S_ EI_S0 EI_ EI_ EI_ EI_ EI_ EI_R/W_ EI_OE_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 _.V_ V.V_.V 0 _ SL0 S0 GPIO/TS GPIO/SH_ GPIO/S ET ETH_RS ETH_M_ ETH_MIO_ ETH_RXLK_ ETH_RXV_ ETH_RX_ ETH_RX_ ETH_RX_ ETH_RX0_ SSI_MLK SSI_LK SSI_FS SSI_RX SSI_TX _ N N N N0 _ 0 TMR GPIO.V_ PWM PWM PWM PWM0 RX0 TX0 RX TX GPIO0 GPIO GPIO GPIO _ GPIO GPIO GPIO GPIO US0_M US0_P US0_I US0_VUS TMR TMR TMR TMR RSTIN_ RSTOUT_ LKOUT0 _ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 _.V_ JTG JTG S ET RST_ LKOUT0 RST_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 JTG JTG JTG JTG Pg VV F_[:0] F_ F_ F_ Pg F_ F_ R0.0K JTG[:] GREEN F_[:0] R0 0 JTG[:] Pg R 0 RE LE Q00 MMT0LTG Pg PI EXPRESS X uF J HR TH X S SOKET 0.UF SF_ R0 R 0K 0K HOL 0.UF V U S SO SI SK R 0K SF_MISO SF_MOSI SF_LK Note: While using GPIO control for HOL, ascertain to free up other GPIO connections on other Stories. SF_ GPIO efault:, J HR X SF_S SF_S HR TH X J Pg F_0_ F_0_ U V N Y 0.UF SNLVG0 F_0 PRIMRY PORT ONNETIONS TF0-SU IP lassification: FP: PUI: rawing Title: MRM, S & SFLSH Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
5 0 J00 V.V_ ELE_PS_SENSE _ SPI_LK SPI_S_ SPI_S0_ SPI_MOSI SPI_MISO V.V_.V _ SL S GPIO ULPI_STOP ULPI_LK ETH_OL_ GPIO ETH_RXER_ ETH_M_ ETH_TXLK_ ETH_MIO_ ETH_TXEN_ ETH_RXLK_ GPIO ETH_RXV_ GPIO/SH_ GPIO/SH_ GPIO0/SH_ GPIO/SH_ ETH_TX_ ETH_RX_ 0 ETH_TX0_ ETH_RX0_ ULPI_NEXT/US_M ULPI_T0/US_M ULPI_IR/US_P ULPI_T/US_P ULPI_T/US_M ULPI_T/US_M ULPI_T/US_P ULPI_T/US_P ULPI_T ULPI_T _0 _ L_HSYN/L_P N L_VSYN/L_P N0 N N 0 N N L_LK/L_P GPIO TMR TMR TMR GPIO GPIO0.V_.V_ PWM PWM PWM PWM0 PWM PWM 0 PWM PWM NRX RX/TSI0 NTX TX/TSI GPIO RTS/TSI L_OE/L_P TS/TSI L_0/L_P0 RX/TSI L_/L_P TX/TSI L_/L_P RTS/TSI L_/L_P TS/TSI 0 0 GPIO L_/L_P GPIO L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P IRQ_P/SPI_S_ L_/L_P IRQ_O/SPI_S_ L_0/L_P0 IRQ_N L_/L_P IRQ_M TMR IRQ_L TMR 0 IRQ_K TMR IRQ_J TMR IRQ_I L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P EI_0/L_P EI_E/L_P EI_/L_P EI_E /L_P EI_/L_P EI_E /L_P0 EI_/L_P EI_E 0_/L_P 0 EI_/L_P EI_TSIZE0/L_P EI_/L_P EI_TSIZE/L_P EI_/L_P EI_TS_/L_P EI_/L_P EI_TST_/L_P EI_/L_P0 EI_T_/L_P EI_/L_P EI_S_/L_P EI_0/L_P EI_S_/L_P EI_/L_P EI_S_/L_P L_0/L_P0 EI_S_/L_P0 L_/L_P GPIO/L_P 0 L_/L_P L_/L_P.V_0.V_ TP PI EXPRESS X SEONRY PORT IP lassification: FP: PUI: rawing Title: OPTIONL PORT Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
Table of Contents 1 TITLE PAGE
Table of ontents TITLE PGE NOTES S0/RS0 MU OSM & PWR PERIPHERLS ELEVTOR ONNS Revisions Rev escription ate pproved X Initial -January- X Revise -January- X Revise -January- X Revise -January- X Revise -January-
ADC_1_AN[5]/SIUL_GPIO[64]/E[0] 49 ADC_0_AN[5]/SIUL_GPIO[66]/E[2] ADC_0_AN[7]/SIUL_GPIO[68]/E[4] ADC_0_AN[8]/SIUL_GPIO[69]/E[5]
![ADC_1_AN[5]/SIUL_GPIO[64]/E[0] 49 ADC_0_AN[5]/SIUL_GPIO[66]/E[2] ADC_0_AN[7]/SIUL_GPIO[68]/E[4] ADC_0_AN[8]/SIUL_GPIO[69]/E[5]](/thumbs/94/118080352.jpg "ADC_1_AN[5]/SIUL_GPIO[64]/E[0] 49 ADC_0_AN[5]/SIUL_GPIO[66]/E[2] ADC_0_AN[7]/SIUL_GPIO[68]/E[4] ADC_0_AN[8]/SIUL_GPIO[69]/E[5]")
U V_SYS ETIMER0_ET0 ETIMER0_ET SPI_S0* SPI_SK SPI_SOUT SPI_SIN FLEXPWM0_FULT0 SPI_S0* SPI_SK FLEXN_TX FLEXN_RX FLEXN0_TX FLEXN0_RX LIN0_TX LIN0_RX LK_OUT0 0_N0 0_N GPIO GPIO GPIO GPIO, _N0, _N, _N, _N
Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11
Table of ontents Notes lock iagram isplay and Tower onnectors MU & apacitive Touch kt Rev X X escription Revisions Initial Release ate -JUL- pproved hanged Power L colours-jul- Removed J and J dded J &
Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA
Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive
2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM
Table of ontents Notes MS0LGLK Touch Sensors Touch Sensors Power OSM US OM L Revisions Rev escription X First raft X Replaced, M RN with sigle resistors Updated Power section Swapped LE_ER, with ER, to
Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:
Table of ontents Notes lock iagram FXL000L / MU ircuit Power and attery harger ircuit Rev escription Revisions Original Release Remove signal line U- pin and add additional signal line between J-pin0 and
X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies
Table of ontents lock iagram Type- onnector US/US PTN0 P TP Shield Headers P Source and Sink LS V, V0, V Supplies Rev escription ate pproved Prototype Release -Mar- K ring up to NL and make updates requested
S08P-LITE. 1 Title Page 2 Block Diagram 3 MCU & Arduino Headers 4 OSBDM & Power Supply 5 On-board Peripherials S08P-LITE. 23-Jun-17. V3.
Title Page lock iagram MU & rduino Headers OSM & Power Supply On-board Peripherials Revisions Rev escription ate -Jun- V.0 -Feb- pproved Microcontroller Product Group 0 William annon rive West ustin, T
FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M.
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Revisions Initial raft ate 0/0/ pproved M. NORMN Release to production 0/0/ M. NORMN X hanges made
FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate
FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13
Table of ontents Title lock iagram KEZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Initial raft Revisions. Remove Motor ontrol onnector J. Remap J, J, J, J pinout. dd one series resister
3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)
NXP VKIT-SZV Table of ontents 0 LOK IGRM N NOTS 0 I/O Headers 0 Power/MU 0 Peripherals 0 US/OSM Revisions Rev escription esigner ate X Initial raft 00 Release 0/0/ X hanged MU to SZV 0// U T I O N : This
FREEDOM KL26Z. Table of Contents 1 Title 2 Block Diagram 3 KL26Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply FRDM-KL26Z.
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev Revisions & hange Log escription ate Initial raft Feb// pproved listair * MU Pin assignments changed for Feb// listair
01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES
Table of ontents 0 TITLE PGE 0 MU 0 EUG INTERFE 0 SUPPLY 0 POWER RIGE 0 MOSFET RIVERS / VI SENSING utomotive Product Group 0 William annon rive West ustin, T 9 esigner:. ZUZEK rawn by:. ZUZEK pproved:
+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:
+V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R0 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V 0.uF U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V
+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:
+V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V SHN 0
NXP Automotive S12ZVMBEVB C U S T O M E R E V B
NXP utomotive SZVMEV U S T O M E R E V Table of ontents 0 PWR SUPPLY / LIN INTERFE 0 ZZVM MU 0 MOTOR ONTROL 0 NLOG SENSE 0 USER PERIPHERLS 0 OSM Revisions Rev escription X Initial raft 00 Release Prototype
Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page
Intel Edison reakout Sept/0 V to V rick Power Supply V power supply and battery recharger SPI GPIO Intel Edison PWM I S URT 0 0" header US 0TG URT Level Shifter URT US FTI P P lient US Micro Type- lient
Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz
V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion
AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115
PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.
L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE
LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE
FREEDOM KL26Z. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft. * MCU Pin assignments changed for Feb/18/13 Alistair Pins 57-64
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev X X Revisions & hange Log escription ate pproved Initial raft Feb// listair * MU Pin assignments changed for Feb//
Revisions Rev Description X1 A. Designer J.Sanchez J.Sanchez B Initial Release J.Sanchez. Prototype C A U T I O N :
SKEV-Q U S T O M E R E V Table of ontents TITLE N NOTES Notes and lock iagram SK MU OPEN S Power Supply/SW I/Os HEERS Revisions Rev escription X Prototype esigner J.Sanchez J.Sanchez Initial Release J.Sanchez
TABLE OF CONTENTS AND REV HISTORY
TLE OF ONTENTS N REV HISTORY PGE# TITLE PGE# TITLE PGE# TITLE 0 OVER_PGE Power Supply 0 lock iagram OSM IRUITS 0 MP - Power and ecaps UIO N S 0 MP - onfiguration 0 Reset onfiguration Jumpers 0 MP - LP
XO2 DPHY RX Resistor Networks
PHY_0_P_RX PHY_0_N_RX [] [] R R LP_0_P_RX HS_0_P_RX HS_0_N_RX LP_0_N_RX PHY_LK0_P_RX PHY_LK0_N_RX PHY_LK_P_RX PHY_LK_N_RX [] [] [] [] R R6 R8 R0 LP_LK0_P_RX HS_LK0_P_RX HS_LK0_N_RX LP_LK0_N_RX LP_LK_P_RX
ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B
IS_IRQ V._0._0._0 O NOT IS_IRQ R K_0._0.0_0 J J.0_0 0 RV_RESET V RV_RESET V TP J IS TEST._0 TP V X [0..] [0..] GN GN -I/O H K RESRV V 0 IRQ V -V REQ -V U 0WS 0 0 V 0 -IO_HRY._0 GN -I/O H RY 0 -SMEMW EN
Revisions. Prototype Release J.H. 21 May 12
Table of ontents Notes lock iagram MP MU in SKT MP MU Power, RST, LIN, N JTG & NEXUS M onnections M onnections Rev X escription Prototype Release Revisions Update from VT - hange shunt on J to pins - -
RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7
Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM
FX2-CLKIN FX2-CLKIO FX2-CLKOUT LAN_PORT4-5 LAN_PORT7-8 LAN_GND. +5V_PoE. PoE_GND
IF_ONNETOR SiTP FX-IO[:6] LN_GN LN_GN SiTP POWER +V_PoE PoE_GN +V_PoE PoE_GN IF_ONNETOR POWER SiTP-Flex Size ocument Number Rev Ucir-008-00 0. ate: Friday, November, 008 Sheet of L +.Vd +.Vd LM8PGSN VIO
0603/15p/10v L R/100MHz. 100nF/50V. 100nF/16V. 100nF/50V C105 C106 C108 C107 GND GND GND GND
+V +V 00nF/0V 00nF/0V 00nF/0V 00R/00MHz.µF/0V 00nF/V 00nF/V 0K K n.b. 0k 0k 00/p/0v 00/p/0v MHZ-.X. 00nF/V 0R 0R µ/v MK0XVLK MK0XVLK 00nF/0V 00nF/0V µ/v 00R/00MHz 0R 0 0 0 L0 0 0 R0 R0 R0 R0 L0 L0 Y0 0
AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
DP CoiNel Technology Solutions LLP GND GND GND GND. ETH_RST is connected to P1.28 GND GND GND GND GND GND GND GND GND ED 1. Vcc O 3 GND IOGND 35
V K R L FR nf nf Vcc E O MHZ_LK ENET_REF_LK ENET_MIO ENET_M MHZ_LK.K R Y OS_MHz LE_LK LE_SPEE LE_T nf is connected to P. ENET_TX ENET_TX ENET_RS ENET_RX ENET_RX ENET_REF_LK ENET_M ENET_MIO nf ENET_TX ENET_TX
CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2
VUS R V_IN V TO.V SETION.V SI_RX SI_TX 0E R PINOUT HEK MINISM00F- Resettable Fuse F 00m WHITE 00nF U GN EN IN IN TPS PG nc OUT OUT 0k R 0.V 00nF Power_Good MIRO US IS INITE S ON TX RX 0.uF VUS TR RI GN
PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]
![PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]](/thumbs/87/96361917.jpg "PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]")
V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH
Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header
esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use
KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power
KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO
HF SuperPacker Pro 100W Amp Version 3
HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project
B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History
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THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia
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Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.
Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT
REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK
REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown
VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD
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Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode
Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
MPC5777C-416DS. 2 Notes 3 Power 5 CONTROLLER I/O 6 RESET, JTAG, NEXUS & UART 7 MB CONNECTOR 4 CONTROLLER POWER. Rev. Description Date Approved
Table of ontents Notes Power ONTROLLER POWER ONTROLLER I/O RESET, JTG, NEUS & URT M ONNETOR Rev Revisions escription ate pproved Initial raft // avid Erazmus..uF cap @ V_US power properties changed //
COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT
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SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:
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AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.
lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January,
EFM8BB3 USB Type-C 60 W Charger. Revision History. Board Function. Rev. Description. Title Page. A00 Prototype version. EFM8BB3 & User Interface
EFM US Type- 0 W harger History oard Function Title Page EFM & User Interface oard Power Page Rev. escription 00 Prototype version. 0 Initial release version. VUS Voltage Regulator ebug MU ebug Misc. P
NOTE: please place R8 close to J1
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THAT Corporation. QSC Digital Cinema Monitor DCM-2/DCM-3 Processor Board
anyone without the written permission of THT orporation. escription ate 00 Released // pproved L/ -000.SH ataport I -00.SH Glue Logic and RS -000.SH UNLESS OTHERWISE NOTE: R/SW -000.SH L/R -000.SH ataport
PCB NO. DM205A SOM-128-EX VER:0.6
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1. Changes made as per TRD (Reference Design-27514) 2. Added a Filter Bead L209 to VSS_LV_NEXUS. Initial PPL Release. 15 Mar 13.
Table of ontents Notes lock iagram MP MU PRT MP MU PRT Power, RST, LIN, N, SIPI JTG & NEUS M onnections Revisions Rev hange escription ate pproved. hanges made as per TR (Reference esign-). dded a Filter
MT9V128(SOC356) 63IBGA HB DEMO3 Card
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Channel V/F Converter
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#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N
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core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103
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Quickfilter Development Board, QF4A512 - DK
Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U
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SEGMENT LE ISPLY R MUX MUX MUX MUX R nf SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ U R xt P P P P P P P P MX MX ss SL S P P P P P P P P nf S SEG_SL SEG_S SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_I_SL_
VCC 21 VCC 52 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD
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TWR-VF65GS10 VYBRID TOWER SYSTEM MODULE
Table of ontents REVISION ISTORY NOTES & REV MOIFITIONS LOK IGRM VYRI MIS PIN POWER ISTRIUTION SERIL INTERFE PERIPERLS ELEVTOR ONNETORS TWRPI & POT & & SS R & NN FLS US Revisions Rev escription ate pproved
MSP430F16x Processor
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SVS 5V & 3V. isplsi_2032lv
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TWR-MPC8309 Schematic
TWR-MP0 Schematic SHEMTI PGE ESRIPTION: 0: over 0: Reset, lock and Switch 0: R and NOR Flash Memory 0: el, Latch, uffer and Logics 0: isplay, S ard and N 0: Ethernet Interface and lock 0: Ethernet PHYs
Stellaris Family Development Board
Stellaris Family evelopment oard USER S MNUL M-LMSFM-0 opyright 00 Luminary Micro, Inc. Legal isclaimers and Trademark Information Legal isclaimers and Trademark Information INFORMTION IN THIS OUMENT IS
CONTENTS: REVISION HISTORY: NOTES:
ONTENTS: PGE - ONTENTS PGE - POWER, XOS PGE - SI, SI, JTG PGE - S/eMM, US, HMI, GPIO, OMPOSITE PGE - SOIMM REVISION HISTORY: V.0 - /0/0 NOTES: These reduced schematics omit core SMPS and LPR circuitry
THAT Corporation. QSC Digital Cinema Monitor DCM-2/DCM-3 Monitor Board
anyone without the written permission of THT orporation. escription ate 00 Released // 0 Per EO # /0/ pproved ataports,,, -00.SH VMON & IMON Input Select of -00.SH UNLESS OTHERWISE NOTE: ataports E,F,G,H
Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0
Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP
2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2.
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FUNCTION. Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers Digital Audio Interface - Test pin header. Regulator 1.2V.
[K-] K- K Evaluation oard Rev.0 GENERL ESRIPTION The K- is an evaluation kit for the K; a digital signal processor (SP) with channels digital data interface. It realizes an easy evaluation of the audio
Calypso Customer EVB 324 BGA Daughter Card (X-MPC574XG-324DS)
alypso ustomer EV G aughter ard (X-MPXG-S) Table Of ontents: Power - alypso power pins footprint Power - alypso ecoupling apacitors GPIO - alypso GPIO pins of GPIO - alypso GPIO pins of locks us Termination
PCIextend 174 User s Manual
PIextend 7 User s Manual Preliminary M6- February Sycard Technology 8-F Miraloma Way Sunnyvale, 98 (8) 79- (8) 79- FX PIextend 7 User s Manual Page. Introduction Sycard Technology's PIextend 7 PI extender
PTN3356 Evaluation and Applicaiton Board Rev. 0.10
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Desired Part Placement. Max current set to 3A (motor Drive is 2.5A) SCI-DRV8814-MVK Mike Claassen B1 Dawn Ritz 40V. VDC_In GND. Board Test Points TP1
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EDP-AM-DIO54 Digital IO Module User Manual. This document contains information on the DIO54 digital IO module for the RS EDP system.
P-M-IO igital IO Module User Manual This document contains information on the IO digital IO module for the RS P system. Version v.0, 0/0/00 P-M-IO Manual ontents. igital IO Module. igital Outputs.... Using
Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI
AKD4554-E Evaluation board Rev.0 for AK4554
SHI KSI [K4554] K4554- valuation boar Rev.0 for K4554 GNRL SRIPTION K4554- is an evaluation boar for the portable igital auio 6bit / an / converter, K4554. The K4554- can evaluate / converter an / converter
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Generated by Foxit PDF Creator Foxit Software For evaluation only.
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Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.
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Reference Schematic for LAN9252-HBI-Multiplexed Mode
Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
Revision History. EFR32 Mighty Gecko Dual PHY Radio Board. 2.4 GHz 13dBm / MHz 14 dbm, DCDC to PAVDD. Board Function Page. Rev.
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XR21B1422/1424 POWER & USB 1.0 Date: Thursday, February 13, 2014
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Renesas Starter Kit for RL/G PU oard Schematics REV REF TE RWN Y 0.0 raft.0.0 TES.00 Release.0.0 YOI.0 Release 0.0.0 YOI PGE ESRIPTION INEX RL/G Microcontroller Switches, LEs, RESET, PSU E, Serial Port
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J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET
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R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H
8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1
isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty
XBee Interface Board XBIB-U-DEV TH/SMT Hybrid
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Virtex 5 FF1738 DUT. Single Ended Socket Clocks 2X. Differential SMA Clocks 2X. Differential SMA MGT Clocks 2X D. Upstream Connector.
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3JTech PP TTL/RS232. User s Manual & Programming Guide
JTech PP-00 TTL/RS User s Manual & Programming Guide Revision. J Tech o., Ltd. Fu-Hsing N. Rd., F Taipei, Taiwan Tel: +--00 9 info@jtech.com.tw JTech (J Eng.), Inc. E. Valley lvd., Suite ity of Industry,