VCC 21 VCC 52 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD

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1 POWER ELETRONIS **- Switching Power Regulation** V and.v outputs are isolated from High Voltage, but not each other Isolated Power Supply power.sch FTI US URT FTI US URT ftdi_uart.sch SLOOP_TRL HRG_TRL FN_TRL NTX NRX Safety Loop Wiring SFETY_TRL HRGE_TRL FN_TRL safety_loop.sch N Transceiver NTX NRX can_xcvr.sch EXTERNL ONNETORS S SL TX RX SFETY LOOP WIRING N TRNEIVER ONNETORS External onnectors connectors.sch S SL RX TX _VR 0p VR MIROONTROLLER Maximum Frequency atasheet (Page ) Vsafe =./*(F-)+. X 0MHz 0.u 0.u _VR 0 0p RX TX VR ecoupling apacitors (U) +.V +.V +.V 0.u I PULLUP S SL +.V 0 TK TMS TO TI 0k R +.V 0k R 0.u XTL XTL PF0(0) 0 PF() PF() PF() PF(/TK) PF(/TMS) PF(/TO) PF(/TI) REF PG0(WR) PG(R) PG(LE) PG(TOS) PG(TOS) PE0(RX0/PI) PE(TX0/PO) PE(XK0/IN0) PE(O/IN) PE(O/INT) PE(O/INT) PE(T/INT) PE(IP/INT) V V SWI PULLUP SW_S SW_SL +.V 0k R VR Reset Switch Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: / File: pacman-main.sch Title: attery Pack Management omputer Size: USLetter ate: Mon Nov 0 Kiad E... kicad (after 0-may- ZR unknown)-product +.V +.V 0k R V U (0)P0 ()P 0 ()P ()P ()P ()P ()P ()P (SS)P0 0 (SK)P (MOSI)P (MISO)P (O)P (O)P (O)P (O0/O)P ()P0 ()P (0)P ()P ()P ()P 0 ()P (/LK0)P (SL/INT0)P0 (S/INT)P (RX/INT)P (TX/INT)P (IP)P (TXN/XK)P 0 (RXN/T)P (T0)P T0N-M +.V 0k R P0 P P SL S NTX NRX SW WTHOG SW_S SW_SL SLOOP_TRL HRG_TRL FN_TRL 0k R P0 P P P P P P P _VR +.V SW_S SW_SL Open rain reset pull-up resistor SYSTEM STTUS LES P0 P P k R k R k R k R EXTERNL WTHOG _VR GROUNE LOW VOLTGE +.V POWER FULT REQUEST LOW VOLT RST V +.V U M0 WTHOG MR WI Threshold:. V Timeout: 00 ms Reset: 0 ms +.V +V +.V +V _VR LUE RE YELLOW YELLOW Rev: 0. Id: / _VR

2 HIGH VOLTGE INTERFES PK VOLTGE SENSOR PK+ PK+ PK- PK- PK- HRG_ET HV_ 0u HRG_ET MS_ PK- PK+ HRG_ET M % R 00K % R 0 S_HV SL_HV PF P0 P P P P P P P - + HV_ HIGH VOLTGE IGITL I/O V VSS V + - O VSS U 0u U SL S 0 INT HV_ PK+ HV_ MP0 Pack Voltage Sensor Scaling (:0) This I/O expander is responsible for relaying digital signals accross the HV-LV isolation barrier via the I bus. S_HV SL_HV 0.u 0k R0 ypass apacitor (U) HV_ PWR_FLG PWR_FLG ypass apacitor (U) I ddress 0x0 (see datasheet page ) SL_HV S_HV HV_ HV_ HV_ HIGH VOLTGE POWER This power supply is responsible for delivering non-isolated V power to the high voltage electronics. ll MS bus connected devices are powered from this regulator. Maximum current draw 0m. This Switcher was selected for its high efficiency even at light load. SK0-LTP 0.u 0.u _PK HV_PWR ypass apacitor (U) HV_ HV_PWR HV_ 0u 0 0u PWR_FLG 0u I ddress 0x (see datasheet page ) IN0 IN IN IN V U S0 M % R 00K % R u 0 % R0 R 0 % R RY S SL 0 HV_ 0u HV_ S_HV SL_HV 0u HIGH VOLTGE S_HV 0.u SL_HV SK0-LTP + Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /Isolated Power Supply/ File: power.sch Title: attery Pack Management omputer Size: USLetter ate: Mon Nov 0 Kiad E... kicad (after 0-may- ZR unknown)-product +V +.V VI VO Vin VPRG This flyback converter has been simulated in LTSpice 0M % EN/UVLO INTV R Vin LT0 SW RUN U VF LT OVLO SS 0 U SW RF RREF T VPRG I PULLUP PTZTE SK0-LTP m S_HV SL_HV K % R R 0k K % R 0K R 0K R R0 0k 0p SK0-LTP MS_ L 0u HIGH VOLTGE HV_ 0u HV_ I ISOLTOR WURTH_0 : T m V S SL LOW VOLTGE MS_ ISO U Si00 OPTO 0u +V LOW VOLTGE V S SL m PWR_FLG.V Linear Regulator U NPSTTG PWR_FLG S SL +.V S SL This flyback regulator is responsible for delivering V isolated power to low voltage systems. This includes: PMN computer, charge relays, and charge fans. The LT0 requires a minimum current draw for stable voltage regulation. If this current draw is not met, the +V rail can go as high as 0% over voltage. It is not recommended to run any digital logic, or sensitive Is from this source. Mimum urrent raw: 0m Maximum urrent raw:. 0.u 0.u Rev: 0. Id: / +V S SL +.V

3 GROUNE LOW VOLTGE SFETY LOOP RELY +.V +V SFETY_TRL HRGE_TRL FN_TRL SLOOP_TRL HRGE_TRL FN_TRL SFETY_TRL HRG_TRL FN_TRL This relay is responsible for switching the PMN safety loop connection ON/OFF. The lights show the user at a glance if the safey loop is open or closed. This relay is capable of switching in configuration. +.V +V SLOOP_TRL k R U0 RELY_VOT onfiguration ( Max urrent) SLOOP_ SLOOP_ SLOOP_ pins are shorted together only when the safety loop is closed SLOOP_ pins are always shorted together SL_V SL_ SLOOP_ SLOOP_ SLOOP_ FN+ HRG+ SL_V SL_ SLOOP_ SLOOP_ SLOOP_ FN+ HRG+ HIGH SIE P-FET RIVER SLOOP_TRL SLOOP_TRL k R k R 0 SFE ERROR GREEN RE +.V HRGE ONTROL N-FET This device is responsible for driving the high side p-fet switches. FN ONTROL N-FET This MOSFET is responsible for connecting the HRGE relays when the pack charger has been connected. Power is supplied from either the pack terminals, or US connector. +.V U V This MOSFET is responsible for switching the charge fan ON/OFF. The fan will not come on automatically when charging begins, it is controlled by the software. Fan Output Voltage: V oil Output Voltage: V HRG_TRL +V k R GREEN HRGE HRG_TRL Y HRG_TRL +V FN_TRL LVG0 Y FN_TRL FN_TRL R 0k Q SIS SK0-LTP FN+ HRG_TRL R 0k Q SIS SK0-LTP HRG+ PPLITION NOTE: The V line is not tightly regulated in low load scenarios. ll devices attached to the V rail should be tolerant to voltage spikes of around 0%. Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /Safety Loop Wiring/ File: safety_loop.sch Title: attery Pack Management omputer Size: USLetter ate: Mon Nov 0 Kiad E... kicad (after 0-may- ZR unknown)-product Rev: 0. Id: /

4 GROUNE LOW VOLTGE +.V +V +.V +V NTX NTX NRX NRX N TRNEIVER +V +V 0.u NTX NRX k R U RX TX Vref Rs VSS V NH NL MP-I/SN 0 R NH NL NTX NRX NTX NRX RE YELLOW k R k R +V +V NOTE: Population of R is optional. R should only be populated if you intend to use this board as a terminating N node. (R should usually be unpopulated). Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /N Transceiver/ File: can_xcvr.sch Title: attery Pack Management omputer Size: USLetter ate: Mon Nov 0 Kiad E... kicad (after 0-may- ZR unknown)-product Rev: 0. Id: /

5 GROUNE LOW VOLTGE +.V +V +.V +V VUS VUS US+ US+ US- US- US URT This is an FTI US Serial onverter I, it can be used to upload code, configure the device, or transfer debugging information if the software is configured properly. TX RX TX RX rivers available for Windows, Mac OS & Linux US OOTSTRP POWER This diode is used to power the PMN computer board when the battery pack has been fully discharged. If voltage is not present between PK+ and PK-, then this diode will allow the US port to supply up to 00m of sustained current. For periods less than 0. seconds, can be drawn. +V F VUS VUS US- US+ 0 VIO V US- US+ OSI OSO VOUT U TX RX RTS TS TR R RI US0 US US US US 0 TX RX TR TXLE RXLE URT LES These LEs light when US serial data is being transmitted. TXLE RXLE TX RX YELLOW FTI Reset onnection RE k R k R VUS VUS TR SK0-LTP 00m 0 0.u TEST FTRL 0.u Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /FTI US URT/ File: ftdi_uart.sch Title: attery Pack Management omputer Size: USLetter ate: Mon Nov 0 Kiad E... kicad (after 0-may- ZR unknown)-product Rev: 0. Id: /

6 HIGH VOLTGE GROUNE LOW VOLTGE TTERY P PK+ PK- US URT US J +.V +V +.V +V ETET EXT I P P P0 P P P P P P P R R HRG_ET PK- PK- S_HV PK- SL_HV MS_ GPIO HEER 0." I onnector External User Interface oard P 0 GPIO This connector contains pins which can be used for SPI. If, at a later time, more complicated Ls, or more I/O is required this feature can be utilized. +V V VUS VUS Vbus SLOOP_ pins are shorted together only when the safety loop is closed Shield_ SFETY LOOP / SLOOP_ pins are always shorted together GLV HRNESS HRGE / + - Shield_ L HEER/SWI US+ US+ US- US- PK WIRING HRNESS PPLITION NOTE Port J is a - backplane connector, which will be connected to the pack wiring harness via solder pot connections. The wiring of this connector, and its inputs/outputs are described in more detail in the pack wiring diagram. This device only uses pins from the GLV connector: NH, NL, and GLV_. harge Relay output, up to V &. can be used. solid state or P-mount relay is recommended to keep current draw within specification. This wire connector is used to interface with an optional I L such as the F-Robot 0x0 character display, or the dafruit L ackpack. NOTE: This port is software I only. SFETY LOOP SFETY LOOP IRS IRS HRGE HRGE FN L HEER/SWI GLV HRNESS SL_V SLOOP_ SLOOP_ SL_ SL_V SLOOP_ SLOOP_ SL_ SL_V SL_ SL_V SL_ HRG+ HRG+ FN+ +V SW_SL SW_S NH NL J KPLNE ONNETOR VR EUGGING JTG Programming/ebug Header P TK TK TO +.V TO TMS _VR TMS _VR TI TI 0 JTG Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /External onnectors/ File: connectors.sch Title: attery Pack Management omputer Size: USLetter ate: Mon Nov 0 Kiad E... kicad (after 0-may- ZR unknown)-product Rev: 0. Id: /