XO2 DPHY RX Resistor Networks

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1 PHY_0_P_RX PHY_0_N_RX [] [] R R LP_0_P_RX HS_0_P_RX HS_0_N_RX LP_0_N_RX PHY_LK0_P_RX PHY_LK0_N_RX PHY_LK_P_RX PHY_LK_N_RX [] [] [] [] R R6 R8 R0 LP_LK0_P_RX HS_LK0_P_RX HS_LK0_N_RX LP_LK0_N_RX LP_LK_P_RX HS_LK_P_RX HS_LK_N_RX LP_LK_N_RX PHY P_RX PHY N_RX PHY P_RX PHY N_RX PHY P_RX PHY N_RX [] [] [] [] [] [] R R R7 R9 R R LP P_RX HS P_RX HS N_RX LP N_RX LP P_RX HS P_RX HS N_RX LP N_RX LP P_RX HS P_RX HS N_RX LP N_RX Place resistor networks as close to ank 0 pins as possible and trace match all diff signals between P and N as well as between pairs LP_* Signals are only needed if you intend on monitoring LP signals from within the FPG. If monitoring LP signals from within the FPG is not needed 00 ohm parallel termination can be used in place of the resistor network for those pairs. It is recommended to use the ohm resistor network on at least the clock lanes and data lane 0 for SI. For SI- 00ohm termination is sufficient for all data and clock lanes in most cases. XO PHY RX Resistor Networks MIPI XO Schematic Example Size ocument Number Rev <oc> ate: Friday, September 0, 0 Sheet of

2 LP_0_P_TX R HS_0_P_TX R 0 PHY_0_P_TX [7] HS_0_N_TX R 0 R6 PHY_0_N_TX [7] LP_0_N_TX LP_LK0_P_TX LP P_TX R7 R8 HS_LK0_P_TX R9 0 PHY_LK0_P_TX [7] HS P_TX R0 0 PHY P_TX [7] HS_LK0_N_TX LP_LK0_N_TX R 0 R PHY_LK0_N_TX [7] HS N_TX LP N_TX R 0 R PHY N_TX [7] LP_LK_P_TX LP P_TX R R6 HS_LK_P_TX R7 0 PHY_LK_P_TX [7] HS P_TX R8 0 PHY P_TX [7] HS_LK_N_TX R9 0 R PHY_LK_N_TX [7] HS N_TX R0 0 R PHY N_TX [7] LP_LK_N_TX LP N_TX LP P_TX R HS P_TX R 0 PHY P_TX [7] HS N_TX R 0 R6 PHY N_TX [7] LP N_TX Place resistor networks as close to ank 0 pins as possible and trace match all diff signals between P and N as well as between pairs If LP mode is not needed the LP_* signals can be removed with the ohm resistors connected to ground XO SI TX Resistor Networks MIPI XO Schematic Example Size ocument Number Rev <oc> ate: Friday, September 0, 0 Sheet of

3 VP VP UF UF HS_* signals must be trace length matched between P and N of a pair as well as HS P_RX HS N_RX HS P_RX HS N_RX HS_LK0_P_RX HS_LK0_N_RX HS_LK_P_RX HS_LK_N_RX HS P_RX HS N_RX HS_0_P_RX HS_0_N_RX between the individual pairs U VP MHX0-000 NK M6 N VIO_ P VIO_ VIO_ P N P_T P_ P M SSPIN_P_T P_ N P P7_T P7_ M N MLK_LK_P9_T SO_SPISO_P9_ N M P0_T P0_ N6 P6 P_PLKT_0_T P_PLK_0_ P7 N7 P_T P_ M7 N8 P0_PLKT T P0_PLK P8 M8 P_T P_ P9 N9 P_T P_ M9 N0 P_T P_ M0 P P7_T P7_ M P P9_T P9_ N P SN_P0_T SI_SISPI_P0_ MachXO-000 HE csbga HS P_TX HS N_TX HS_LK_P_TX HS_LK_N_TX HS_0_P_TX HS_0_N_TX HS_LK0_P_TX HS_LK0_N_TX HS P_TX HS N_TX HS P_TX HS N_TX VP 8 0 HS_* signals must be trace length matched between P and N of a pair as well as U between the individual pairs MHX0-000 NK 0 VIO0_ VIO0_ VIO0_ PT9_T_LVS PT9 LVS PT_T_LVS PT LVS 6 PT_T_LVS PT LVS 7 7 PT8_PLKT0 T_LVS PT8_PLK0 LVS 9 9 PT_T_LVS PT LVS 0 PT_T_LVS PT LVS PT_T_LVS PT LVS PT7_T_LVS PT7 LVS 9 0 JTGEN_PT_T PROGRMN_PT_ INITN_PT8_T ONE_PT8_ 8 8 SL_PLKT0_0_PT0_T S_PLK0_0_PT0_ MachXO-000 HE csbga XO MIPI HS TX Signals XO MIPI HS RX Signals MIPI XO Schematic Example Size ocument Number Rev <oc> ate: Friday, September 0, 0 Sheet of

4 VP8 9 UF VP8 7 UF VP8 UF VP8 L J K K K L M M VP8 G F F G H H H J J VP8 E E E F U MHX0-000 NK VIO PL6_T PL6_ PL7_PLKT_0_T PL7_PLK_0_ PL9_ PL0_T PL0_ MachXO-000 HE csbga UE MHX0-000 NK VIO PL9_T PL9_ PL0_PLKT_0_T PL0_PLK_0_ PL_T PL_ PL_T PL_ MachXO-000 HE csbga UF MHX0-000 NK VIO PL_L_GPLLT_F_T PL_L_GPLL_F_ PL_L_GPLLT_IN_T PL_L_GPLL_IN_ PL6_PLKT_0_T PL6_PLK_0_ PL7_T PL7_ PL8_T PL8_ VP UF 6 LP_LK_P_TX LP_LK_N_TX LP_LK0_P_TX LP_LK0_N_TX LP_0_P_TX LP_0_N_TX LP P_TX LP N_TX LP P_TX LP N_TX LP P_TX LP N_TX LP_LK_P_RX LP_LK_N_RX LP_LK0_P_RX LP_LK0_N_RX LP_0_P_RX LP_0_N_RX LP P_RX LP N_RX LP P_RX LP N_RX LP P_RX LP N_RX U VP MHX0-000 NK H VIO_ L VIO_ VIO_ PR_R_GPLLT_F_Q0_T PR_R_GPLL_F_Q0_ PR_R_GPLLT_IN_Q0_T PR_R_GPLL_IN_Q0_ E E PR_Q0_T PR_Q0_ E F PR6_Q0_T PR6_Q0_ F F PR8_Q0_T PR8_Q0_ G G PR9_QS0_T PR9_QS0N_ G H PR0_PLKT_0_Q0_T PR0_PLK_0_Q0_ J J PR_QS_T PR_QSN_ J K PR_Q_T PR_Q_ K K PR_Q_T PR_Q_ L M PR6_Q_T PR6_Q_ M M PR8_Q_T PR8_Q_ N N PR9_Q_T PR9_Q_ MachXO-000 HE csbga MachXO-000 HE csbga For XO-00 compatibility, VIO = VIO = VIO XO MIPI LP RX and TX Signals Extra anks MIPI XO Schematic Example Size ocument Number Rev <oc> ate: Friday, September 0, 0 Sheet of

5 VP8 00nF 0uF/6V/X7R R 6 00K ms R VP R7 R uF U LT0 IN EN IS PWP 7 LT0 OUT J R8 0K R00 R 0_0K R00 7 0uF/6V/X7R VP R9 NI TP TP_LOOP_RE VP VP VP8 LE LE PRT_NUMER = HSMG-90 PRT_NUMER = HSMH-90 LE Manufacturer = VGO LE Manufacturer = VGO R0 80 R060 % R 80 R060 % Vout = 0.*(+R/R6) =.00V G H L L P P0 UG MHX0-000 Power V V V V N VP N P 7 VP 9 UF 0 MachXO-000 HE csbga ore Voltage VP8 UH R.7k J VP8 V TO TI ispen_n N 6 TMS 00nF 8 TK 9 ONE 7 0 INITN R.7k R6.7k 6 6 MHX0-000 JTG TK_TEST_LK_PT_T TI_PT_ TO_PT_T TMS_PT_ NI JTG Header R7 k MachXO-000 HE csbga JTG MIPI XO Schematic Example Size ocument Number Rev <oc> ate: Friday, September 0, 0 Sheet of

CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2

CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2 VUS R V_IN V TO.V SETION.V SI_RX SI_TX 0E R PINOUT HEK MINISM00F- Resettable Fuse F 00m WHITE 00nF U GN EN IN IN TPS PG nc OUT OUT 0k R 0.V 00nF Power_Good MIRO US IS INITE S ON TX RX 0.uF VUS TR RI GN