OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP
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- Norman Barnett
- 5 years ago
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1 MU ROOTIS / ORO MU_NRESET R_[0..] R_[0..] R_ R_ R_ R_ R_ R_0 R_0 R_ R_ R_ R_ R_ R_ OTG_S_VUS OTG_S_N OTG_S_P OTG_S_I OTG_S_O OTG_S_PWR OTG_S_I OTG_S_N OTG_S_P OTG_S_O OTG_S_VUS UT_USER UT_USER SW_USER SW_USER N_RX N_TX N_TX N_RX MPU_SPI_INT OTG_S_PWR JTMS_SWIO JTK_SWLK JTO_SWO JTI JTMS_SWIO JTK_SWLK JTI JTO_SWO XL_RX XL_TX XL_IR USER_URT_TX USER_URT_RX TEST_PIN R_ R_ UT_USER SW_USER R_ R_ SYS_STS_LE SYS_USER_LE R_ R_ SYS_USER_LE UT_USER R_ R_ R_0 SW_USER SYS_USER_LE SYS_USER_LE OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 OLLO_S MU_NRESET OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 XL_RX XL_TX XL_IR USER_URT_RX USER_URT_TX SYS_STS_LE MPU_SPI_S MPU_SPI_LK MPU_SPI_SI MPU_SPI_SO MPU_SPI_INT TEST_PIN TEST_PIN TEST_PIN TEST_PIN TEST_PIN TEST_PIN[..] MPU_SPI_S MPU_SPI_LK MPU_SPI_SO MPU_SPI_SI TEST_PIN TEST_PIN TEST_PIN TEST_PIN0 TEST_PIN TEST_PIN UZZER_SIG XL_PWR_EN UZZER_SIG XL_PWR_EN TEST_PIN TEST_PIN TEST_PIN TEST_PIN _T_PWR_IN _T_PWR_IN SYS_USER_LE SYS_USER_LE SYS_USER_LE SYS_USER_LE OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 USER_URT_RX USER_URT_TX OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 OLLO_S TEST_PIN TEST_PIN USER_URT_RX USER_URT_TX OLLO_SLEEP OLLO_SLEEP VoV_MU VoV VoV VoV_MU VoV VoV V_RE+ VoV RT_T OTG_S_O N_TX JTMS_SWIO JTK_SWLK JTO_SWO JTI MU_NRESET N_RX OLLO_S OLLO_S OLLO_S OLLO_S0 XL_TX XL_RX XL_IR USER_URT_RX USER_URT_TX SYS_STS_LE MU_NRESET UT_USER UT_USER SW_USER SW_USER MPU_SPI_SO MPU_SPI_INT MPU_SPI_LK MPU_SPI_S MPU_SPI_SI OTG_S_PWR OTG_S_P OTG_S_VUS OTG_S_N OTG_S_I R_[0..] R_[0..] TEST_PIN[..] UZZER_SIG XL_PWR_EN TT_HRGE_LE _T_PWR_IN SYS_USER_LE SYS_USER_LE SYS_USER_LE SYS_USER_LE OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 OLLO_S OLLO_S USER_URT_RX USER_URT_TX OLLO_SLEEP Size ocument Number R e v ate: Sheet o f MU(STMZGT) OpenR riday, pril, 0 Size ocument Number R e v ate: Sheet o f MU(STMZGT) OpenR riday, pril, 0 Size ocument Number R e v ate: Sheet o f MU(STMZGT) OpenR riday, pril, 0 Y SP0E-.000M RY GN RY GN 00-0.u-V R R00-0K 00-0.u-V 00-0.u-V R R00-0R 00-0.u-V U STMZGT V V 0 V V V V V V 0 V_US V0 V V VT V VRE+ VSS VSS VSS VSS VSS VSS VSS 0 VSS 0 VSS 0 VSS VP VP 0 R0 R00-0R 00-0.u-V 00-0.u-V 00-p-V 0-.u-0V 00-0.u-V LMPGSN LMPGSN 00-0.u-V R R00-00R 00-p-V U STMZGT P0-WKUP P P P P 0 P P P P 00 P 0 P0 0 P 0 P 0 P 0 P 0 P 0 P0 P P P P P P P P P 0 P0 P 0 P P P P P-OS_IN P-OS_OUT PH0-OS_IN PH-OS_OUT NRST OOT0 PR_ON P0 P P P P P P P P P P0 P P P-NTI_TMP R00 R00-N 0 0-u-V 0-u-V R0 R00-0R Y STL00-.K RY RY u-V R0 R00-0K 00-0.u-V SW ST-S R R0-0R R R00-0R 00-p-V U STMZGT P0 P P P P P P P P P P0 P 0 P P P P PE0 PE PE PE PE PE PE PE PE PE 0 PE0 PE PE PE PE PE P0 0 P P P P P P P P 0 P P0 P P 0 P P P PG0 PG PG PG PG PG 0 PG PG PG PG PG0 PG PG PG PG PG R R00-0R R0 R00-0R 0-.u-V R R00-.K M0K-0T0 0-.u-0V 00-0.u-V R R00-.K 00-0.u-V 00 0-u-V 0 0-.u-V R R00-0K 0 00-p-V R0 R00-0R
![R_[0..] R_[0..] R_[0..] R_[0..] RUINO UNO MU_NRESET R_ R_ R_ R_ R R0 VoV Vo0V V_R_IN R_0 R_ R_ R_ R00-0R R R00-N R00-0R R R00-N JP EMLE-_.](/docs-images/93/112138861/images/2-0.jpg "JP EMLE-_. JP 0 EMLE-0_. JP EMLE-_. 0 R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R R0-0R V_RE+ 0-N VoV R R00-0R LE0-GREEN VoV Vo0V V_R_IN 00-0.u-V 00-0.")
2 R_[0..] R_[0..] R_[0..] R_[0..] RUINO UNO MU_NRESET R_ R_ R_ R_ R R0 VoV Vo0V V_R_IN R_0 R_ R_ R_ R00-0R R R00-N R00-0R R R00-N JP EMLE-_. JP EMLE-_. JP 0 EMLE-0_. JP EMLE-_. 0 R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R R0-0R V_RE+ 0-N VoV R R00-0R LE0-GREEN VoV Vo0V V_R_IN 00-0.u-V 00-0.u-V 00-0.u-V R_ Q0 KR0S ROOTIS / ORO OpenR Size ocument Number Rev RUINO SHIEL ate: riday, pril, 0 Sheet o f
3 VoV R R00-0R VoV Vo0V R R00-K LE0-ORNGE OTG_S_PWR R R R00-0K R00-0R U IN ULT# EN# OUT GN STMPSSTR 0-.u-V R R00-0R OTG_S_O Vo0V_US US_G OTG_S_VUS OTG_S_N OTG_S_P OTG_S_I R LMPGSN R00-0R R R U Vbus +out -out z Pup R00-0R R00-0R I +in -in Pd Pd Vo0V_US M-MSM00- J US Micro- VUS M P I GN ZX--P SHIEL SHIEL SHIEL SHIEL Micro- US_G GN EMI0-US0 R R00-0R R R0-0M 0-.n/00V LE0-GREEN OTG-S US.0 ROOTIS / ORO OpenR Size ocument Number Rev OTG-S(US.0 Micro-) ate: riday, pril, 0 Sheet o f
4 VoV VoV SW ST-S SW ST-S UT_USER UT_USER R R00-0K UT_USER UT_USER R R00-0K 00-0.u-V R0 R00-0K 00-0.u-V R R00-0K UTTON SWITH VoV SW_USER SW_USER VoV VoV R R R00-0K R00-0K SW SHK-0 UZZER_SIG UZZER_SIG LS TN-0 Q KR0S IP SWITH UZZER VoV SYSTEM RESET SW JT-0 R R00-0K 00-0.u-V R U V MR RESET GN MRKS 00-0.u-V R00-0K MU_NRESET MU_NRESET ROOTIS / ORO OpenR Size ocument Number Rev PUSH/SIIE SW ate: riday, pril, 0 Sheet o f
5 VoV VoV R R00-0K R R00-0K R R00-0K R R00-0K U MPU_SPI_LK MPU_SPI_S MPU_SPI_SO MPU_SPI_SI MPU_SPI_INT MPU_SPI_LK MPU_SPI_S MPU_SPI_SO MPU_SPI_SI MPU_SPI_INT VoV R R R R R00-0R R00-0R R00-0R R00-0R 0 SL/SLK N ns N S0/S0 N S/SI N N INT N N SYN N N UX_L UX_ 0 REGOUT RESV RESV VIO RESV V GN_TM MPU-0 GN 00-0.u-V u-V VoV VoV 00-0.u-V MPU Sensor ROOTIS / ORO OpenR Size ocument Number Rev MPU SENSOR ate: riday, pril, 0 Sheet o f
6 XL_TX XL_RX XL_IR XL_TX XL_RX XL_IR XL_RX Vo0V 00-0.u-V U Y V GN NSZ0PX RX_TTL RX_ R R00-0K Vo0V XL_TX XL_IR Vo0V R R00-0K RO RE I E XL_I+ U V GN MXES+ R XL_I+ XL_I- R-0R Vo0V 00-0.u-V R R J HEER X.0MM R0-0R R0-0R Vo0V XL_I- XL_+ XL_- XL T XL_TX RX_TTL Vo0V 00-0.u-V U0 OE Y V NWZKX OE Y GN R R00-0K TTL_T S XL_PWR J XL_PWR J XL_PWR J TTL_T TTL_T TTL_T u-V -EH u-V -EH u-V -EH- TTL onnector XL_PWR J XL_PWR J XL_PWR J0 XL_+ XL_- XL_+ XL_- XL_+ XL_ u-V -EH u-V RS onnector -EH u-V -EH- ROOTIS / ORO OpenR Size ocument Number Rev RS/TTL XL ate: riday, pril, 0 Sheet o f
7 VIN R -u-0v XL_PWR_EN XL_PWR_EN R00-K 00-0.u-V Q KR0S Q IR0SPb SS SS R R00-K XL_PWR RS/TTL Power ontrol ROOTIS / ORO OpenR Size ocument Number Rev RS/TTL PWR ONTROL ate: riday, pril, 0 Sheet o f
8 N_TX N_RX N_TX N_RX VoV VoV R0 R0 R N_TX N_RX R00-N R00-0K VoV R00-0K 00-0.u-V U TX NH RX NL S V VIO GN TJ0T/ Vo0V 00-0.u-V 00-0n-V 00-00p-V R0 R00-0R R R00-0R 00-00p-V I/O U I/O GN SM Vo0V 00-0.u-V J N 000WS-0 VoV R USER_URT_TX USER_URT_RX R00-0K USER_URT_RX USER_URT_TX U I/O I/O GN SM USER_URT_TX USER_URT_RX R R VoV R00-R R00-R 00-0.u-V J 000WS-0 Vo0V VoV SYS_STS_LE SYS_USER_LE SYS_USER_LE SYS_USER_LE SYS_USER_LE R R SYS_STS_LE SYS_USER_LE SYS_USER_LE SYS_USER_LE SYS_USER_LE R00-0R R00-0R LE0-GREEN LE0-GREEN SYS_STS_LE VoV R R00-0R LE0-GREEN SYS_USER_LE VoV R USER_URT_TX USER_URT_RX R00-0K USER_URT_RX USER_URT_TX U I/O I/O GN SM USER_URT_TX USER_URT_RX R0 R VoV R00-R R00-R u-V J 000WS-0 VoV VoV VoV R R R R00-0R R00-0R R00-0R LE LE0-RE LE0-ORNGE LE0-ORNGE SYS_USER_LE SYS_USER_LE SYS_USER_LE URT ROOTIS / ORO OpenR Size ocument Number Rev N/URT/LE ate: riday, pril, 0 Sheet o f
9 MU_NRESET R_ R_ R_ MU_NRESET R_ R_ R_ Vo0V [MISO] [SK] [RST] R_ R_ MU_NRESET J R_ [MOSI] HEER X.MM RUINO ISP TEST_PIN[..] TEST_PIN TEST_PIN TEST_PIN TEST_PIN TEST_PIN TEST_PIN TEST_PIN TEST_PIN TEST_PIN R R R R R0 R R R R TEST_PIN[..] VoV R00-0R R00-0R R00-0R R00-0R R00-0R R00-0R R00-0R R00-0R R00-0R J HEER 0X.MM VoV 0 0 R R R R R R R R R GPIO R00-0R R00-0R R00-0R R00-0R R00-0R R00-0R R00-0R R00-0R R00-0R TEST_PIN TEST_PIN TEST_PIN TEST_PIN TEST_PIN0 TEST_PIN TEST_PIN TEST_PIN TEST_PIN JTMS_SWIO JTK_SWLK JTO_SWO JTI MU_NRESET VoV 0-u-V JTMS_SWIO JTK_SWLK JTO_SWO JTI MU_NRESET VoV J R R00-0K 0 HEER X.MM R R00-0K VoV R0 R00-0K R R00-0K JTG/SW JTMS_SWIO JTK_SWLK JTO_SWO JTI MU_NRESET 0-u-V 0-u-V ROOTIS / ORO OpenR Size ocument Number Rev JTG/SW/OLLO/GPIO ate: riday, pril, 0 Sheet o f
10 VIN VOUT Vo0V VIN VOUT E XJ(/L0), u, 0V + HRV HRV + E XJ(/L.), u, V + SW SW LRV SS LRV Q SQ Q S0Q E + E XJ(/L.), u, V XJ(/L.), u, V Q SNQ Q SQ SS L XL00-ME S R R0-00R 00-p-0V R R-0.0R SG R0 R0-00R uck-oost Power VIN R0 R0-0R VIN SS 0-0n-0V R R00-.K VIN R R00-.K 00-n-V 00-.n-V R R00-.K 00-0p-0V R R0-.K R R00-.K U VIN VINSNS EN SS OMP MOE RT_SYN ITH V IS VOSNS HRV OOT SW LRV PGOO HRV 0 OOT R R 00-0.u-V VOUT HRV LRV Rfu Rfd R0-0K R0-0K HRV OOT R SS 00-0.u-V SW R0-0R 0 SS OOT u-V VOUT -u-0v R R0-0K 00-00p-V S SG SW LRV SLOPE ISNS S ISNS+ SG GN 0 PGN P LMPWPR LRV VOUT VOUT SW uck-oost ontroller Rfu = ((Vout - 0.)/0.) * Rfd ROOTIS / ORO OpenR Size ocument Number R e v UK-ST POWER ate: riday, pril, 0 Sheet 0 o f
11 J JK SMPS Power Input R R00-00K R V ~ V Power Input attery Power Input R00-00K R R00-00K Q0 MMT0/SOT R R00-00K R R00-K QM0 G ENS ONNETOR (MLE) Q Q MMT/SOT S J SS + E POWER_IN use_00_r(v0)_sm POWER_IN XJ(/L0), u, 0V SS Vo0V_US 0 SS Vo0V_R SS Vo0V 00-0.u-V Vo0V_MP VIN U R0 R00-0K R R00-0K Vo0V_ST + POWER_SEL VoV R R00-0K - LMVIGKR Vo0V_ST Vo0V U S S S POWER_SEL G R R00-0K P-MOSET SQS0EN System V Out Vo0V VoV_OUT J J J 00-0.u-V Molex u-V SMW WS-0 V OUT V OUT V OUT POWER_IN SW VIN J0 MSSMQE SMW0-0 SMPS, attery Output RT_T J u-V Molex 0-00 RT TTERY INPUT VIN R R R00-K R00-0K Power Output M0K-0T0 _T_PWR_IN _T_PWR_IN Main Power In -u-0v attery Power Measurement Vo0V Vo0V_MP Vo0V VoV Vo0V -0u-V V_R_IN U IN OUT GN TM IL-.0ET -0u-0V Vo0V_R -0u-V 00-0.u-V Vo0V U0 IN OUT GN TM IL-.ET -0u-0V VoV_OUT 00-0.u-V Vo0V E + XJ(0/L0), 0u, V R R00-K U VIN EN XL00 -u-0v R0 R00-0.K SW TM GN R R00-0R L uh,, TSL-0M E + N XJ(0/L0), 0u, V 0-u-V 00-0.u-V -0u-V U IN OUT GN TM IL-.0ET -0u-0V -0u-V 00-0.u-V System Power ivide U IN OUT GN TM IL-.ET -0u-0V 00-0.u-V V/ OUT ROOTIS / ORO OpenR Size ocument Number R e v INPUT POWER ate: riday, pril, 0 Sheet 0 o f
12 OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 R0 R R R R R R00-0K R00-N R00-0K R00-0K R00-N R00-0K OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S OLLO_S0 R R R R R R R00-0K R00-N R00-0K R00-0K R00-N R00-0K OLLO_SLEEP OLLO_SLEEPR R00-0K u-V OLLO_SLEEP OLLO_S OLLO_S 00-0.u-V U P GN SLEEP IN IN 0 0 P P P VP OUT IN IN L L OUT u-V R 0.0 SENSE OUT V OUT SENSE Vo0V OLLO_S_OUT OLLO_S_OUT OLLO_S0_OUT R 0.0 VoV J OLLO_S_OUT 0 OLLO_S0_OUT 0 OLLO_S OLLO_S OLLO_S_OUT OLLO_S_OUT VoV HEER X.0MM VoV u-V 0-u-V OLLO_S OLLO_S0 0 0SESTR-T, QN0 OLLO_S_OUT 00-0.u-V 0 Vo0V OLLO_S_OUT VoV J OLLO_S_OUT 0 0 OLLO_S OLLO_S_OUT HEER X.0MM OLLO_S0_OUT OLLO_S OLLO_S_OUT VoV 00-0.u-V OLLO_SLEEP OLLO_S OLLO_S OLLO_S OLLO_S0 U P GN SLEEP IN IN 0 P P P VP OUT IN IN L L OUT u-V R 0.0 SENSE OUT V OUT SENSE 0SESTR-T, QN0 OLLO_S_OUT OLLO_S0_OUT R 0.0 OLLO_S_OUT OLLO VoV u-V 0-u-V ROOTIS / ORO OpenR Size ocument Number Rev OLLO ate: riday, pril, 0 Sheet 0 o f
Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.
Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT
J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET
GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP
AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
LED POWER STAGE1 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE2 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE3 NOT_EN LED+ PWM
MU LE POWER STGE MU MX LI LI_TX LI_RX THERMISTOR- MX_RX MX_TX MX_E MX_/RE EN_ EN_ EN_ EN _ V LE Power Stage LE POWER STGE LE+ LE- LE+ LE- R R 0 J 0 Way 0 LI_TX LI_RX MX_RX MX_TX MX_E MX_/RE V LE Power
C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.
Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P
Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page
Intel Edison reakout Sept/0 V to V rick Power Supply V power supply and battery recharger SPI GPIO Intel Edison PWM I S URT 0 0" header US 0TG URT Level Shifter URT US FTI P P lient US Micro Type- lient
CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2
VUS R V_IN V TO.V SETION.V SI_RX SI_TX 0E R PINOUT HEK MINISM00F- Resettable Fuse F 00m WHITE 00nF U GN EN IN IN TPS PG nc OUT OUT 0k R 0.V 00nF Power_Good MIRO US IS INITE S ON TX RX 0.uF VUS TR RI GN
LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND
R White R Red _TX_Q_P J 0-0 0 _TX_I_P _TX_I_N _TX_Q_P _TX_Q_N L _TX_I_P _TX_I_N.R -d ttenuator.r.r 00pF_0V JP SM _TX_Q_P _TX_Q_N _TX_Q_P _TX_Q_N GN VV VV VV_TX VV VV VV_TX Modulator L L PowerSupply J POWER
Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz
V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion
LED_POWER_STAGE1 PWM GND ADJ LED- -12V R2 RA. LED Power Stage LED_POWER_STAGE2 PWM GND ADJ LED- -12V R4 RB. LED Power Stage LED_POWER_STAGE3
MU THERMISTOR- MU LI_RX LI_TX LI_RX LI_TX MX_TX MX_RX MX_/RE MX_E MX_TX MX_RX MX_/RE MX_E MX_LI +.V_MU R 0K R 0K R R R R LE_POWER_STGE - Out GN J LE- -V LE Power Stage LE_POWER_STGE - Out GN J LE- -V LE
AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD
POWER ELETRONIS **- Switching Power Regulation** V and.v outputs are isolated from High Voltage, but not each other Isolated Power Supply power.sch FTI US URT FTI US URT ftdi_uart.sch Safety Loop Wiring
Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header
esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use
0603/15p/10v L R/100MHz. 100nF/50V. 100nF/16V. 100nF/50V C105 C106 C108 C107 GND GND GND GND
+V +V 00nF/0V 00nF/0V 00nF/0V 00R/00MHz.µF/0V 00nF/V 00nF/V 0K K n.b. 0k 0k 00/p/0v 00/p/0v MHZ-.X. 00nF/V 0R 0R µ/v MK0XVLK MK0XVLK 00nF/0V 00nF/0V µ/v 00R/00MHz 0R 0 0 0 L0 0 0 R0 R0 R0 R0 L0 L0 Y0 0
CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-
SPST SW L 0uH.uF TP HEER NO STUFF TP 0 HEER NO STUFF TP TP pf Y.uF.uF 0 HEER NO STUFF 0 HEER NO STUFF MHz, 0ppm pf.uf (OUT) (IN) R 0K /W % 0uF OUT OUT OUT OUT KLT L 0 L_MISO L_MOSI L_SK S_S- L_S- L_- L_
KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power
KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO
VCC 21 VCC 52 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD
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0 [] [] [] [] [] [] [] [] [] [] [] [] MOSI MISO SK 0 H H N_MS TMS RX TX SL J P_MOSI P_MISO P_SK P_ P_IO0 P_IO P_IO P_ P_ 0 P0_GN P_NT P_GN/NT P_RXL/SS P_TXL P_IO P_(SL) P_(S) P_ P_0 0 P0_ P_ P_IO P_R+
THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia
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P&E Embedded Multilink Circuitry
MP PWM_LE MP PWM_LE.Sch MP Power MP Power.Sch MP USER_LE MP USER_LE.Sch P&E Embedded Multilink ircuitry MP MU MP MU.Sch MP_9_Temp_Sensor MP_9_Temp_Sensor.Sch RESET KG RESET_TO_TGT_PSS GN_TO_TGT_PSS TGT_TX
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nrf0-mk V.0 n Open-Source, Micro evelopment Kit for IoT pplications using the nrf0 So Revision History Function escription Page Rev. escription Title Sheet V.0 The First Release Power Supply US.0 Hub PLink
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Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0
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FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13
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HF SuperPacker Pro 100W Amp Version 3
HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project
Audio Mod RF-04-N-10 PC13 BAS85 56 PG1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PG0 57 PG2 87 PG3 88 PG4 89 PG5 90 PG6 91 PG7 92 PG8
LC0,uF,uF R R 0uF 0uF uf R uf uf uh FOX_.000 uh 0uF 0uF R k DFU mode k 0uF KRMR SSSM TCM0 P0DT0G S PN0-S STMFX_ZIT C C0 C C C C C C C R R C C C C R C0 C C C L R0 IC L C C RD C0 C0 R0 P R C C0 C C C C TP
FREEDOM KL26Z. Table of Contents 1 Title 2 Block Diagram 3 KL26Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply FRDM-KL26Z.
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev Revisions & hange Log escription ate Initial raft Feb// pproved listair * MU Pin assignments changed for Feb// listair
NOTE: please place R8 close to J1
Sheets, & /M_RESET PST T T0 +.V_MU R 0K /M_RESET PST T T0 +.V_MU 0.uF NOTE: please place J close to the edge of the P so that the debug cable is clear of the P when attached to the board J 0 0 M Header
Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.
PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional)
POSWD0SWO POKBD0ROW0A GND POSDIO0D3 POLCD0NOE
L_LIGHT = P = TIM_H L_SX = P = FSM_NE L_TINS = P = FSM_0 LE_RE = P = TIM_H LE_GREEN = P = TIM_H LE_LUE = P0 = TIM_H POK0ROW0 K_ROW_ PIU0 POK0ROW0PIU0 K_ROW_ PIU0 POK0ROW0E K_ROW_E PIU0 POK0ROW0F K_ROW_F
XIO2213ZAY REFERENCE DESIGN
XIOZY REFERENE ESIGN XIOZY Reference Size ocument Number Rev ate: Wednesday, September, 00 Sheet of TP+ TP- TP+ TP- TPIS TP+ TP- TP+ TP- TPIS TP0+ TP0- TP0+ TP0- TPIS0 REFLK+ REFLK- V_ V_ V_ORE PLLV_ORE
DO NOT POPULATE FOR 721A-B ASSY TYPE
V R 0 R 0 R 0 R 0 R 0 R 0 TP TP pf 000pF 000pF 000pF R R R R R K % 0.0uF R.0K % 000pF IFFOUT pf R K % R 0 0 UVJ R K % U LTUH PLLIN PLLFLTR F IFF IFFOUT SENSE SENSE SENSE RUN/ UVJ SGN LKOUT OOST TG G OOST
REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK
REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown
ALEX +12VBUS PTC 1A J17 PTT U1B. 126 IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR. IO_VB1N1_9/DIFFIO_L7p/DQS2L/CQ3L/CDPCLK0 RUP3
F PT VUS J J HEER X V_LEX V LEX LEX_SPI_SO LEX_SPI_SO R R LEX_SPI_SK LEX_SPI_SK LEX_SPI_RX_LO LEX_SPI_RX_LO R LEX_SPI_TX_LO LEX_SPI_TX_LO R FW_PWR REV_PWR 0 LEX HR 0P LEX J HR P R PWR IN THRU FW_PWR REV_PWR
XO2 DPHY RX Resistor Networks
PHY_0_P_RX PHY_0_N_RX [] [] R R LP_0_P_RX HS_0_P_RX HS_0_N_RX LP_0_N_RX PHY_LK0_P_RX PHY_LK0_N_RX PHY_LK_P_RX PHY_LK_N_RX [] [] [] [] R R6 R8 R0 LP_LK0_P_RX HS_LK0_P_RX HS_LK0_N_RX LP_LK0_N_RX LP_LK_P_RX
Dev Board for CC IMX28. Mechanicals Board Size should be 7 X 8 inches Group similar connections together (ENET, USB, UART, etc) H5 ANT1
0 S oard Size should be X inches roup similar connections together (NT, US, URT, etc) S URT T OUT NT Power Supplies TM US0 (OT) umpers and switches need to be organized in functional groups and labeled
FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate
Revision History. EFM32PG12 Pearl Gecko STK. Description. Board Function Page. EFM32PG12 Pearl Gecko Starter Kit. Title Page 1.
EFMPG Pearl Gecko STK oard Function Page Title Page User Interface Rev. 00 History escription Initial release EFM Signal ssignments 0 hanged to rev of EFM EFM Power EFM I/O STK oard ontroller dvanced Energy
Power. I/O Extensions. CPU Extensions. JADE-D Subsystem
XXSvideo- Revision: P. Power WI V_ORE_PG WI V_ORE_PG Reference I: 00 # WI PU Extensions HOST_SPI[..0] SPI_0[..0] PU_[..] PU_[..0] MEM_TRL[..0] MEM_RY VIN0_[..0] HOST_SPI[..0] S PI_0[..0] PU_[..] PU_[..0]
2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM
Table of ontents Notes MS0LGLK Touch Sensors Touch Sensors Power OSM US OM L Revisions Rev escription X First raft X Replaced, M RN with sigle resistors Updated Power section Swapped LE_ER, with ER, to
Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode
Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:
+V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R0 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V 0.uF U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V
CS P/N A042C868 SS P/N A042F943 TB-6 TB-8 TB-11 TO PUMP CONTROLLER TB-311 TB-312 TB V +10V +10V +10V LED 59 K23 LED 60 LED 58 LED 47 K15
TO PUMP ONTROLLER S P/N 0 SS P/N 0F T- T- T- P/N 0H0 FPDP GEN II S P/N 0G SS P/N 0G P/N 0G ORD LED U(PIN) T- LED T- T- T- T- T- T-0 T-0 T-0 T-0 T-0 T-0 T- T- T-0 T-0 K U(P) T-0 LED K U(P0) LED K U(P) LED
AML7266-H. Feature table. Block Thursday, February 12, 2009 AMLOGIC AML7266-H. Main Chip: Internal: Video: Audio: Interfaces: UART USB HOST RJ45
ON Y Pb Pr is(smk,sk,slrk,s) MP U V V pin con to Mainboard IR MI MI U WM SMK,SK,SLRK MII_(ST) URT JTG con U ML-H SPI FLSH U MXL-G U NN FLSH KFGU Gb SL +.V/. POR LO U +.V RJ RMII Eth PHY U LN US HOST RMII
Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI
TO PUMP CONTROLLER TB-304 TB-311 TB-312 TB-302 TB V +10V LED 59 K23 +10V +10V LED 60 LED 58 LED 47 K15 U18(P2) U14(P1) U18(P0) U18(P1) +10V
TO PUMP ONTROLLER S P/N 0 SS P/N 0F T- T- T- P/N 0J FPDP GEN II S P/N 0G SS P/N 0G P/N 0G ORD LED U(PIN) T- LED T- T- T- T- T- T-0 T-0 T-0 T-0 T-0 T-0 T- T- T-0 T-0 K U(P) T-0 LED K U(P0) LED K U(P) LED
12V SMPS_1_2 SMPS_4/5 SMPS6 VDD_CORE VDD_MPU VDD_DSP 5V0 PS_3V3 VDD_3V3 5V0 .01, C2 5V0_SNS 10.2K,1% 100uF,10V 1.91K PS_3V3 .
V.7uF,0V.LESR.7uF,0V.LESR 0.uf,V,00 R 69K U- U- U- V TO V U OOT VIN EN SS TPS.nF,0V,00 9 P PH GN 7 OMP 6 VSNS U- U-6 R SKFL-TP V0_OMP L.7uH V0_SNS V0 R 0.K,% R + 00uF,0V V0_TP V0 R.0,06 V SMPS SMPS_/ SMPS6
PTN3356 Evaluation and Applicaiton Board Rev. 0.10
E PTN Evaluation and pplicaiton oard Rev. 0.0 REVISION STORY : ------------------------------------- 0. June 0, 0 - ase on PTN_ONLY_REV.SN 0. July, 0 - OM changes due to long lead time items, LEs 0. July,
Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09
Table of ontents Notes F & PL MRM, S & SFLSH OPTIONL PORT Rev X0 escription onvert into FSL template Revisions X ll parts FL //0 X Replaced U with the correct part //0 X X Replaced some components with
P/N A042C868 TO PUMP CONTROLLER TB-307 TB-311 TB V +10V +10V LED 59 K23 +10V LED 60 LED 47 LED 58 K15 U18(P2) U14(P1) U18(P1) U18(P0) +10V
P/N 0 P/N 0H0 TO PUMP ONTROLLER T- T- T- FPDP GEN II S P/N 0G SS P/N 0G P/N 0G ORD LED U(PIN) T- LED T- T- T- T- T- T-0 T-0 T-0 T-0 T-0 T-0 T- T- T-0 T-0 K U(P) T-0 LED K U(P0) LED K U(P) LED K U(P) LED
M13 M14 FQP FFP VC1 VC2 VC3 MIX ATNEXPOT ADSR1 BM-VCF FAH1 FAW1 H W ATNEXPOT LFO FAH2 FAW2 H W +10VR FFP BP FQP FAH1 FAW1 FAH2 FAW2 R2 100K M15
MP_ MP_ MIIV JP HEE JP V0 V V V S_0 S_ S_0 S_ MIILK STTSTOP ESET SMP_ SMP_ HEE JP 0V 0V 0V 0V 0V 0V 0V 0V HEE X 000 JP9 000 MII VP VP 9 0 POTSLE POTH POTL POTSLE POTSLE POTH POTL POTSLE 9 0 HEE X 000 HEE