Dev Board for CC IMX28. Mechanicals Board Size should be 7 X 8 inches Group similar connections together (ENET, USB, UART, etc) H5 ANT1

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Agatha Johns
6 years ago
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1 0 S oard Size should be X inches roup similar connections together (NT, US, URT, etc) S URT T OUT NT Power Supplies TM US0 (OT) umpers and switches need to be organized in functional groups and labeled with legible font. We will be adding tables to the silk screen to show positions. PO and -WIR SSP SSP I0 I eader IN PI onnector US Need Vias for mounting kit in upper right hand corner Please mark all pin locations for interfaces connectors. URT URT URT S IMX NT NT0 ine up ZI () connectors on the module with ZI () connector on the ev oard N URT SMT X X N0 S UIO NT S ard Power, Recover, and Reset uttons User uttons and s S NT S 00-0 eet should go on bottom of board in the center and corners STNI P 00-0 P O c igi International Inc. 0 ll rights reserved O NOT S RWIN RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N T: 0// Scott Mcall TIT PRT NO. Y PPR Mechanicals T ev oard for IMX 00-0 ST RV. of

2 0 URT 0. abgn luetooth URT(-) I (0,) (bpp) w/touch screen separate connector i.mx Module NT (0,) N (0,) Main features of each variant. See ardware Reference manual for more information on available interfaces in each variant. US0 (OT) US IS PWM (0,,-) SSP (0,,) (SSP0 is SIO) R (0-) SU i.mx S RM NTS 0. abgn T T -Wire _WMX_P_T_T M M Y Y Y Y Y _WMX_P_T_ M M Y Y Y Y N _WMX_P_T M M Y Y Y Y N _WMX_P_VM_ M M Y N Y Y N _WMX_P_VM M M Y N Y Y N _WMX_P_ZM_ M M N N Y Y N _WMX_P_ZM M M N N Y Y N _WMX_P_V_ 0 M M 0 Y N N N N _WMX_P_V 0 M M 0 Y N N N N _WMX_P_VM_T 0 M M Y N Y N N _WMX_P_VM 0 M M Y N Y N N _WMX_P_ZM_ 0 M M N N N N N _WMX_P_ZM 0 M M N N N N N One-Wire S and Trigger RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall PRT NO. ev oard for IMX lock iagram O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST RV. of

3 0 S0-S- ayout for PIe mini card IMX dge onnector NT0_TX 0u S0-SN- 0u NT0_RX NT0_RX- NT0_TX- 0 Ohm/ V_V_ URT_TS/SSP_SS0/SI0_M R R I_S URT_RTS/SSP_MOSI/SI0_R R 0 R I_S URT_RX/SSP_MISO/SI0_IT R R URT_RX/I0_S URT_TX/SSP_S/SI0_T0 R R URT_TX/I0_S PSWIT US0_M R R0 RST SSP0_M US0_P R 0 R SSP0_T0 US0_I/PWM R0 R SSP0_T VTT R SSP0_T S0 R R SSP0_T N0_RX/S_Trigger R R SSP0_S N0_TX R 0 R USR_utton SSP_SSN/R0 R R R/SI_T0 SSP_MOSI/R R IMX_V SSP_MISO/R R R -WIR SSP_S/R R R USR_utton URT_TS/R/NT0_SP_ R 0 R URT_RX URT_RTS/R/NT0_TIV_ R R0 URT_TX URT_TX/PWM/USR_ R0 R N_RX/URT_RX/NT_TIV_ URT_RX/PWM0/USR_ R 0 Ohm/ V_V_ R N_TX/URT_TX/NT_SP_ O connector Pins NT_TX NT_TX- 0 NT_RX/US_M NT_RX-/US_P ven onnector Pins 0u The zero ohm resistors are to allow disconnection of various portions of the V board from the module. This will allow developement to go forward while the V board is being updated (should updates be required). o not put traces into the board under the module connectors. We need to have copper fill with vias on each layer of the P for thermal management. O c igi International Inc. 0 ll rights reserved O NOT S RWIN RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N T: 0// Scott Mcall TIT PRT NO. Y PPR dge onnector T ev oard for IMX 00-0 ST RV. of

4 0 P M-R V_PO PO_N - R 0 - SW Switch/0--V R0 V0P R. Wall_V 00n S Yellow efault for switch SW PO abel: PO/V Input Power u/v 00n U SR VIN IS SN V OOST N VSW V V Power Supply 00n 0 MRS0T MMS u R0 R R R u 00u/V 0 0u efault for switch SW R abel: V R/xternal V xternal Supply M Switch/0--V SW % R V_V V umper to measure module currnet 0u/0V umper P TSW-0-0--S R. P Place these caps close to the IMX power input 0u S Yellow 00n p.p 0 Ohm/ 0 Ohm/ V_V_ V_V_ One errite for each V connection to the module VTT MR0VST U 0TR P TSW-0-0--S umper P.V Xee Power V Power MR0VST V0P VIN.u S SW VOUT u/v U0 T VIN N OUT.V Power Supply. O 0u 0 V_V_US.V oard Power P umper P TSW-0-0--S VR_V_always_ 0 Ohm/ Place these caps close to the SMT Xee power input 0u 00n 00n p p.p.p V_._X Xee Power Place these caps close to the through hole Xee power input V_._X 0u R 0 R SN PRO N TP R M R u/v 0u 00n RV O SRIPTI O N Y PPR T TIT PPROVS: T: VOUT =.Vx(M/k) =.V SIN:. supply for USs RWN: : NINR: Scott Mcall PRT NO. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 0// ev oard for IMX POWR 00-0 ST RV. of

5 0 TT (.V) M umper to measure attery current umper P VTT S R efault for switch SW R abel: TT R/xternal P TSW-0-0--S. Volt Power Supply for attery Simulation SW U SR MMS Switch/0--V Wall_V - V0P 00n u/v 00n VIN IS SN V OOST N VSW V 00n MRS0T u R 0 R R u 00u/V 0u 0 % R RN.V Power 0u/0V 0u Place these caps close to the TT input 00n p.p 0 Ohm/ VTT VR_V_always_ US ROVRY 0 R SW T00Q VR_V_always_ PSWIT SW T00Q R0 RST 0n 0 R MR0VST RST SW TSW-R O c igi International Inc. 0 ll rights reserved O NOT S RWIN R 0n POWR 00 Pull own on the Module RV O PPROVS: SIN: RWN: : NINR: 0 R SRIPTI O N T: 0// Scott Mcall TIT PRT NO. Y PPR T ev oard for IMX attery, Power and Reset utton 00-0 ST RV. of

6 0 VR_V_always_ This switch is included to remove all.v inputs to the IMX during reset should the need arise R IMX_V Q T R 00 R0 00 S SiS Q R0 V_V R0 S Yellow.V Power RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall PRT NO. ev oard for IMX.V O Switch O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST RV. of

7 0 URT VR_V_always_ U- SPU- u u V URT RS onnections URT_TX/I0_S URT_RX/I0_S SW T00SR u URT_TX 0 IN ROUT T T T V- V 0 u 00 Ohm/00m 00 Ohm/00m R.R p/-su Male RS connection efault switches closed URT_RX OUT R R R IN 0 R IMX_V VR_V_always_ R R 0 R 00 IN STTUS SUTOWN VR_V_always_ u V U- SPU- N RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: RWN: : NINR: Scott Mcall PRT NO. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 0// ev oard for IMX URT RS 00-0 ST RV. of

8 0 URT is only available in the following Variants: -WMX-P-T-T -WMX-P-T- -WMX-P-T -WMX-P-VM- -WMX-P-VM -WMX-P-ZM In ddition TS and RTS share with R and R (see jumper page) URT_TX/PWM/USR_ URT_RTS/R/NT0_TIV_ URT_RX/PWM0/USR_ URT_TS/R/NT0_SP_ SW S00S URT_TX URT_RTS u u IN URT U- SPU- T T T V V- V 0 0 u u VR_V_always_ 00 Ohm/00m 00 Ohm/00m 00 Ohm/00m URT RS onnections R.R p/-su Male RS connection efault switches open URT_RX URT_TS 0 ROUT OUT R R IN 00 Ohm/00m 0 R R IMX_V VR_V_always_ R VR_V_always_ R 0 IN STTUS SUTOWN R 00 u V U- SPU- N RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: RWN: : NINR: Scott Mcall PRT NO. URT_RS O c igi International Inc. 0 ll rights reserved O NOT S RWIN 0// ev oard for IMX 00-0 ST RV. of

9 0 URT shares with SSP (see jumper page) for the following variants: -WMX-P-T-T -WMX-P-T- -WMX-P-T -WMX-P-VM- -WMX-P-VM -WMX-P-ZM VR_V_always_ URT U- SPU- u 0 u V URT RS onnections URT_TX/SSP_S/SI0_T0 URT_RTS/SSP_MOSI/SI0_R URT_RX/SSP_MISO/SI0_IT URT_TS/SSP_SS0/SI0_M SW S00S efault switches open URT_TX URT_RTS URT_RX URT_TS u 0 T IN T T ROUT R OUT R V- V IN 0 u 0 00 Ohm/00m 00 Ohm/00m R.R 00 Ohm/00m 00 Ohm/00m p/-su 0 Male RS connection R R IMX_V VR_V_always_ R 0 R IN STTUS SUTOWN R 00 VR_V_always_ O c igi International Inc. 0 ll rights reserved O NOT S RWIN u V N U- SPU- RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N T: 0// Scott Mcall TIT PRT NO. Y PPR T ev oard for IMX URT_RS 00-0 ST RV. of

10 0 URT eaders URTS are TT level URT IMX_V U- NSZ0PX_N VR_V_always_ R 0 URT_RX URT_RX U- NSZMX O U- NSZMX O URT_TX URT_TX P TSW URT P TSW V N VR_V_always_ U- NSZMX 00n V N U- NSZMX 00n 00n V N U- NSZ0PX_N 0 URT is shared with N and NT s SW0 T00SR N_RX/URT_RX/NT_TIV_ N_TX/URT_TX/NT_SP_ URT_RX URT_TX efault switches open RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall ev oard for IMX URT eaders PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST 0of

11 0 V_V 0 R 0 R 0 R U- VTPW O T/R R S RN S RN S RN S RN S RN RN S RN S S RN 0 URT_TX URT_RX URT_RTS URT_TS URT_TX URT_RX URT_RTS URT_TS R R0 R R R R V N 0 U- VTPW 00n 00 0 R0 0 R0 0 R0 0 R 0 R R R S S0 R S R S R S R S R S0 R R S V_V U- VTPW O T/R 0 V N U- VTPW 00n 0 URT_TX URT_RX R R 0 R 0 R RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N Y PPR T TIT T: 0// PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN S R S R Scott Mcall ev oard for IMX URT s 00-0 ST of

12 0 NT0 NT0_TX 00n NT0_TX- XVOIP--Y-MS T T T- T Transmit TX TX- NT PYs are on the module NT0 ontrol: URT_TS: RN SP URT_RTS: Y TIV V_PO - P SW-0-0--S PO_N PO MOU P SW-0-0--S n R0 R n R0 R 0 n R0 R 0 n R0 R NT0_RX 00n NT0_RX- V_V R 0 NT0_SP_ 0 R NT0_TIV_ n/v 0 Ohm/ 0 Receive R T R- T PO - PO - Y - R - ousing RX RX- T RIT URT_TS/R/NT0_SP_ URT_RTS/R/NT0_TIV_ NT ontrol: URT_TX: RN SP URT_RX: Y TIV truth table ow = igh = O NT0_SP_ SW T00SR NT0_TIV_ efault switches open NT XVOIP--Y-MS NT_TX NT_TX- NT_RX NT_RX- 00n 00n T T T R T T Transmit Receive TX RX T- R- TX- RX- N_TX/URT_TX/NT_SP_ N_RX/URT_RX/NT_TIV_ NT_SP_ SW T00SR NT_TIV_ efault switches open 0 PO - PO - V_V n R00 R n R R n R R n R R NT_SP_ NT_TIV_ n/v R00 R0 0 0 Ohm/ - - Y R ousing T RIT RV O SRIPTI O N Y PPR T NT RX and RX- are shared with US (see NT_US_oot umpers page), and are only available when US is not. O c igi International Inc. 0 ll rights reserved O NOT S RWIN PPROVS: SIN: RWN: : NINR: T: 0// Scott Mcall TIT PRT NO. ev oard for IMX thernet 00-0 ST of RV.

13 0 US_M NT_RX/US_M NT_RX NT_RX- NT_RX-/US_P US_P R0 0u R0 NT/US TSW-0-0--S P umper P umper TSW-0-0--S Settings for US and NT Variant Setting -WMX-P-T-T NT -WMX-P-T- NT -WMX-P-T NT -WMX-P-VM- US -WMX-P-VM US -WMX-P-ZM US -WMX-P-V- US -WMX-P-V US -WMX-P-VM-T US -WMX-P-VM- US -WMX-P-VM US -WMX-P-ZM- US -WMX-P-ZM US IMX oot Mode onfig: uffer Mode nable NN S 0 0 T T T T T 0 US X S T Module efault is NN lash boot Setting 0, to 0, 0 boots from Module efaults by setting all buffers in tri-state. T= tri-state (high Z) Place ap by each chip (U, U, U0, U, U, and U) 00n U- V N Q 00n V N 00n U- Q V_V V N U0- Q R IMX_V R V_V SW T00SR efault switches as shown R 0 R0 0 U- SNVR U- SNVR U- MV0 U- MV00T 00n R O U- Q O O 00n _0/TM 0/TM 00/TM_0 _0/TM 0/TM_ O c igi International Inc. 0 ll rights reserved O NOT S RWIN U- Q O U- Q U- Q S 00n R R IRM R R R U- Q O _0 IMX_V _0 U0- Q 0 O O V N RV U0- Q U0- Q O U0- Q O O PPROVS: SIN: RWN: : NINR: U- MV00T U- MV0 _0 _0 _0 _0 _00 _00 _0 _0 SRIPTI O N T: 0// Scott Mcall TIT V N PRT NO. 0 O U- Q O O Y V N U- Q U- Q U- SNVR PPR T ev oard for IMX NT_US umpers_oot onfig 00-0 ST of RV.

14 0 V_V V_V_US R. R 00 MX0S u 0 R 0. R UT ST N U V_V R 00 MX0S V_V_US u 0 US0 (OT) Micro connector 0 Ohm/ 00n 0 The Module is not powered from the US because it can pull more than 00m US Micro R R. UT ST N U US0_I/PWM P umper US0_M US0_P P TSW-0-0--S umper P0 PWM_ is available on pin of P with the jumper open. P TSW-0-0--S 0n 0 Ohm/ 0 0 US_M US_P US Type connector 00u/0V 0 Ohm/ 0 Ohm/ n 0000 SSIS S0 S0 TSW-0-0--S US is shared with NT RX and RX- (see NT_US_oot umpers page), and is only available when NT is not. N0_RX/S_Trigger RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall ev oard for IMX US_S PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST of

15 0 efault switches open R/SI_T0 URT_TS/SSP_SS0/SI0_M URT_TX/SSP_S/SI0_T0 URT_RX/SSP_MISO/SI0_IT SW S00S R00 I_S I_S U- ST000XN/R TR_ TRO TR_T TR_0_S TR_MO p URT_RTS/SSP_MOSI/SI0_R IS INTR IS_IN IS_OUT IS_S IS_R ine In N Microphone N 0p N 0p N 0 0p 0p N N R.0 R.0 R.0 N R R.0 R N N.u N 00n 00n u u u 0 P/R PMP/V IT SYS_M PIT V ININ_R ININ_ MI MIIS 00n O c igi International Inc. 0 ll rights reserved O NOT S RWIN V_V 0 Ohm/ R INOUT_R INOUT_ 00n P_R P_VN P_ 0u N 0 0 u u 00u/0V 00u/0V R0 0 U- ST000XN/R V VIO N N P V N N N N N N N N POWR R 0 R 0 N R 0 RV 0 0p O PPROVS: SIN: RWN: : N NINR: 0p N R R0 R R SRIPTI O N T: 0// Scott Mcall N TIT PRT NO. ine Out/ead Phones Y PPR T ev oard for IMX UIO 00-0 ST of RV.

16 0 MIRO S ard Socket V_V 0 0u 0 R 0 R 0 R0 0 R0 R n P micros/00 SSP0_T SSP0_T SSP0_M SSP0_S SSP0_T0 SSP0_T R R0 T /T M V VSS T0 T 0 0p 0 0p 0p 0p 0p 0p R 0 R TT R TT SSIS SSIS RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall ev oard for IMX S-R PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST of

17 0 N0_RX/S_Trigger P umper N0_TX P TSW-0-0--S U- SNV R Rs N N R N0 P umper P TSW-0-0--S NUP0T p/-su 0 The N USS are only available with the following Variants: -WMX-P-T-T -WMX-P-T- -WMX-P-T -WMX-P-VM- -WMX-P-VM -WMX-P-ZM N_TX N_RX U- SNV R Rs N N N R P umper P TSW-0-0--S NUP0T 0 p/-su 0 N is shared with URT SW T00SR V_V N_RX/URT_RX/NT_TIV_ N_TX/URT_TX/NT_SP_ N_RX N_TX 00n V N U- SNV 00n V N U- SNV efault switches open O c igi International Inc. 0 ll rights reserved O NOT S RWIN RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N T: 0// Scott Mcall TIT PRT NO. Y N PPR T ev oard for IMX 00-0 ST of RV.

18 0 R. R. V_V I0 P0 ntenna N 0 Ohm Trace U. to RPSM Place with separate (isolated) Ns on opposite boad edges P -0T0 N N N N P ntenna N N 0 Ohm Trace P0-0T0 N N N N URT_TX/I0_S URT_RX/I0_S SW T00SR efault switches open P TSW-0-0--S URT and I0 are software selectable N X U. to RPSM Place with separate (isolated) N P ntenna N 0 Ohm Trace P -0T0 N N N N N I_S I_S V_V I P TSW-0-0--S -WIR -WIR P TSW-0-0--S SW T00SR efault switches open U S I/O N N N N N I can also be used as the URT (software selectable) Pull up resistors are on the module One-Wire charges to.v One-Wire PROM RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall ev oard for IMX I, -Wire, U. PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST of

19 0 SSP_MOSI/R SSP_MISO/R SSP_S/R SSP_SSN/R0 SW S00S SPI efault switches open SSP_MOSI SSP_MISO SSP_S SSP_SSN V_V P TSW-0-0--S SSP is shared with R0,,, and. R and are shared with URT TS and RTS on the following Variants: -WMX-P-T-T -WMX-P-T- -WMX-P-T -WMX-P-VM- -WMX-P-VM -WMX-P-ZM R is shared with URT TX SSP is shared with URT. SSP is only available on the following Variants: -WMX-P-T-T -WMX-P-T- -WMX-P-T URT_RTS/SSP_MOSI/SI0_R -WMX-P-VM- URT_RX/SSP_MISO/SI0_IT -WMX-P-VM URT_TX/SSP_S/SI0_T0 -WMX-P-ZM URT_TS/SSP_SS0/SI0_M SW S00S SPI V_V P TSW-0-0--S efault switches open RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall ev oard for IMX SPI eaders PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST of

20 0 V_V Potentiometers for testing R Vmax=.V with divide by on i.mx SW S00S W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R0 0 SSP_SSN/R0 SSP_MOSI/R SSP_MISO/R SSP_S/R SW S00S URT_TS/R/NT0_SP_ URT_RTS/R/NT0_TIV_ R/SI_T0 efault switches open R[0-] SSP_SSN/R0 SSP_MISO/R URT_TS/R/NT0_SP_ R/SI_T0 P TSW SSP_MOSI/R SSP_S/R URT_RTS/R/NT0_TIV_ V_V SSP is shared with R0,,, and. R and are shared with URT TS and RTS on the following Variants: -WMX-P-T-T -WMX-P-T- -WMX-P-T -WMX-P-VM- -WMX-P-VM -WMX-P-ZM R is shared with URT TX O c igi International Inc. 0 ll rights reserved O NOT S RWIN RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N T: 0// Scott Mcall TIT PRT NO. Y PPR T ev oard for IMX R eader and POTs 00-0 ST 0of RV.

21 0 User uttons SW0 T00SR These connections come through URT_RTS, and SSP0_R_TT URT_TX/PWM/USR_ URT_RX/PWM0/USR_ USR_ USR_ V_V V_V efault switches open 0 R SW T00Q 0 R SW T00Q USR_utton USR_utton R R User s onnected to URT_TS and URT_RTS (PWM and PWM respectively) V_V V_V USR_ R0 0 Q MMT0T USR_ R 0 Q MMT0T S RN S RN R R RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall ev oard for IMX User s and uttons PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST of

22 0 V_._X Xee_out Xee_in Xee_nRST Xee_TR 0 PIN TT SPRIN 0 Xee SMT Socket Need to include the hole to push the part out of the socket 0 P SPRIN TT PIN 0 The layout of the SMT socket needs to be done the same as it is on 00x (the SMT ev. oard). Xee_omm Xee_RTS X_SSoc URT_TS/SSP_SS0/SI0_M URT_RTS/SSP_MOSI/SI0_R URT_TX/SSP_S/SI0_T0 URT_RX/SSP_MISO/SI0_IT Xee onnections for URT URT_RTS is used for TR during firmware upgrades SW S00S efault switches open Xee_RTS Xee_TR Xee_in Xee_out P Xee_nRST V_._X 0 0n R SW T00Q X Reset V_._X 0 SPRIN TT PIN P V_._X 0p/ Xee_out Xee_in Xee_nRST Xee_TR 0 Xee Through ole Socket Xee R MOU V 0/IO0 0 OUT /IO IN/I /IO IO RST /IO RTS//IO PWM0/RSSI/IO0 SSO//IO PWM/IO VR RSRV /SP/IO TR/SP_RQ/IO TS/IO 0 N /IO Xee_omm Xee_RTS X_SSoc 0p/ X ssociate S Yellow R0 SW R Q X_SSoc MMT0T Xee_omm 0 T00Q X OMM RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N Y PPR T TIT T: 0// ev oard for IMX Xee PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN Scott Mcall 00-0 ST of

23 0 p_0 _ZI_ RT T TI TO TMS TRST T us _S/TOU_INTRUPT TM_TT R _00/TM_0 R _0/TM_ R 0 _0/TM 0/TM_ R R _0/TM_ R _0/TM_ R _0/TM_ R _0/TM 0/TM_ R R0 _0/TM_ R _0/TM_0 R _/TM_ R 0 _/TM /TM_ R R _/TM_ R _/TM_ R _ R _ R _WR_RWN/TM_T R0 _N R _SYN R _VSYN R 0 _OT R R TM US ines can be used as PIOs (software selectable) RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall ev oard for IMX, TM Input onnector PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST of

24 0 onnector /TM /TM _0/TM_0 _0/TM 0/TM 0/TM_0 _0 _00 _0 _0 P x0p/ /TM /TM _/TM 0/TM 0/TM /TM 0/TM 0 _0 _0/TM_ T us TRST TI TMS T RT TO RST R R 0 R 0 T onnector P x0p/ox 0 0 V_V _N URT_RX/PWM0/USR VSYN SSP_MISO/R URT_TS/R/NT0_SP_ I_S SSP_SSN/R0 SSP_MOSI/R R _OT R _SYN SSP_S/R URT_RTS/R/NT0_TIV_ I_S SSP_S/R SSP_MISO/R R0. VR_V_always_ SSP is used for Touch Screen and SPI functions Pin unction R R SSP_SSN SSP_S SSP_MOSI SSP_MISO _S/TOU_INTRUPT V_V Wall_V 0 V_V Wall_V P umper P TSW-0-0--S PU or SPI Touch Screen umper open PU Touch ontroller umper Shorted SPI Touch ontroller 0 RV O SRIPTI O N Y PPR T PPROVS: TM US SIN: RWN: : NINR: TIT T: 0// PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN Scott Mcall ev oard for IMX and T 00-0 ST of

25 0 x_mictor R 0 RQ 0 _WR_RWN/TM_T XTTRI VTR VSUPPY R 0 R R 0 R V_V _0/TM 0/TM_ 0 _0/TM /TM 0/TM 0/TM /TM 0/TM /TM 0/TM /TM_ 0 _/TM 0/TM_0 _0/TM_ TM_TT _0/TM 00/TM_0 0 TM US RV O SRIPTI O N Y PPR T TIT PPROVS: T: SIN: 0// RWN: : NINR: Scott Mcall ev oard for IMX TM onnector PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT S RWIN 00-0 ST of

26 0 SW S R R R P R0 P P P0 P R R R R U0 R S R0 S R S R0 R0 R0 R R R R 0 R 0 P P R R R R R R R 0 R0 R P Q R0 P P R R R R R R P R R R 0 R0 0 R Q R R0 U U R0 R R R P 0 R U 0 R R R0 R R0 R R R R R R 00 R00 0 U U S S R U S S R R R R R 0 S S U 0 S S0 S S0 R S S R0 U R0 R R R S R S R U S S SW SW Q S SW R0 R R0 R0 0 U SW SW P SW0 P SW SW P R R R R R U P Q S SW R R S R0 U S R R R P P SW SW SW SW P R R R R R SW0 SW SW R P P SW P R R R0 SW SW R U P P R R 0 U R R R R R R R0 R R R P R P SPRIN SI SPRIN SI U U U0 U SW P R R R R R R R0 R0 R R R R R R R R0 R R R R R R R R R U SPRIN SI R R P R R R R R R R0 R R R R R R R R R0 R R R R R R0 R R R R R R R R R R R R R 0 R R 0 SW R R U P R0 R0 R R P SW SW P P R R R0 0 P P P P0 R P P P Q 0 R R P U R P R R R00 SW R P SW P0 R R R 0 U SW R0 0 R0 R0 R0 0 R 0 0 R0 R0 R P U S 0 R P RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N Y PPR T 0 ll rights reserved O NOT S RWIN ST T: Oc igi International Inc. TIT ev oard for IMX TOP SSMY PRT NO RV. O

27 0 RV O PPROVS: SIN: RWN: : NINR: SRIPTI O N Y PPR T 0 ll rights reserved O NOT S RWIN ST T: Oc igi International Inc. TIT ev oard for IMX OTTOM SSMY PRT NO RV. O

SM XBEE MODULE XBEE SMT MODULE NC GND GND RF_SELECT VCC COMM/AD0/DIO0 AD1/DIO1 DOUT/DIO13 AD2/DIO2 DIN/CONFIG/DIO14 DIO12 AD3/DIO3 RESET RTS/DIO6

SM XBEE MODULE XBEE SMT MODULE NC GND GND RF_SELECT VCC COMM/AD0/DIO0 AD1/DIO1 DOUT/DIO13 AD2/DIO2 DIN/CONFIG/DIO14 DIO12 AD3/DIO3 RESET RTS/DIO6 0 ONI N RST SW T00Q R 0 X_V R0 TI TMS T TO R IN T R V P TSW0 0 urrent Testing TSW00S P R OUT IO RSSI_PWM PWM X_V 0 0u/0V R R R R R R TR/PIN_SP 0u 00n p.p X_OUT X_IN X_IO X_RST X_PWM X_/MS_X X_TR/PIN_SP