Power. I/O Extensions. CPU Extensions. JADE-D Subsystem

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1 XXSvideo- Revision: P. Power WI V_ORE_PG WI V_ORE_PG Reference I: 00 # WI PU Extensions HOST_SPI[..0] SPI_0[..0] PU_[..] PU_[..0] MEM_TRL[..0] MEM_RY VIN0_[..0] HOST_SPI[..0] S PI_0[..0] PU_[..] PU_[..0] MEM_TRL[..0] M EM_RY VIN0_[..0] HOST_SPI[..0] SPI_0[..0] PU_[..] PU_[..0] MEM_TRL[..0] MEM_RY VIN0_[..0] JE- Subsystem TESTMOE_ MPX_MOE [..0] JTGSEL JTG[..0] INT_[..0] SPI_[..0] TESTMOE_ MPX_MOE [..0] JTGSEL JTG[..0] INT_[..0] S PI_[..0] V_ORE_PG TESTMOE_ MPX_MOE [..0] JTGSEL JTG[..0] INT_[..0] SPI_[..0] I/O Extensions ISP_SYN_R_[..0] LKIN LKO_R SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] ISP_SYN_R_[..0] LKIN LKO_R SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] ISP_SYN_R_[..0] LKIN LKO_R SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] Reference I: 00 Hierarchy PIX_SOUT[..0] PIX_SIN[..0] XXSvideo- TSG_R_[..] TST_R PWMO # PIX_SOUT[..0] PIX_SIN[..0] TST_R PWMO TSG_R_[..] Part References PIX_SOUT[..0] PIX_SIN[..0] TST_R PWMO TSG_R_[..] PWMO[..0] N_RX[..0] N_TX[..0] IS_[..0] TRE[..0] VIN_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TSG_R_[..] ML[..0] PWMO[..0] N_RX[..0] N_TX[..0] IS_[..0] TRE[..0] VIN_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TSG_R_[..] ML[..0] PWMO[..0] N_RX[..0] N_TX[..0] IS_[..0] TRE[..0] VIN_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TSG_R_[..] ML[..0] +---# XXSvideo Top +---# PU us Extension xx +---# Power xx +---# JE Subsystem +---# JE +---# JE- Part xx +---# JE- Part xx +---# JE- Part xx +---#9 JE- Part xx +---#0 R SRM xx +---# Flash xx +--- I/O Extension xx Top # Reference I: xx Gartenstrasse 0 Neumünster XXSvideo-: Top # Size ocument Number R ev 00 P ate: Wednesday, ugust, 009 Sheet of

2 VIN0_[..0] VIN0_[..0] PU_[..] PU_[..] LKIN LKO_R SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] ISP_SYN_R_[..0] HOST_SPI[..0] S PI_0[..0] TSG_R_[..] LKIN LKO_R SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] ISP_SYN_R_[..0] HOST_SPI[..0] S PI_0[..0] TSG_R_[..] VIN0_0 VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_9 VIN0_0 VIN0_ SYN_R_ SYN_R_ SYN_R_ SYN_R_0 OUTR_R_ OUTR_R_ OUTR_R_ OUTR_R_ OUTR_R_ OUTR_R_ OUTG_R_ OUTG_R_ OUTG_R_ OUTG_R_ OUTG_R_ OUTG_R_ OUT_R_ OUT_R_ OUT_R_ OUT_R_ OUT_R_ OUT_R_ ISP_SYN_R_0 ISP_SYN_R_ ISP_SYN_R_ ISP_SYN_R_ ISP_SYN_R_ ISP_SYN_R_ HOST_SPI0 HOST_SPI HOST_SPI HOST_SPI SPI_00 SPI_0 SPI_0 SPI_0 TSG_R_ TSG_R_ TSG_R_ TSG_R_ LK0 VINHSYN0 VINVSYN VINFI0 E HSYN VSYN G V HSYN0 VSYN0 G VO0 LKP LKN E0 HOST_SPI_I HOST_SPI_O HOST_SPI_SS HOST_SPI_SK SPI_I0 S PI_O0 SPI_SS0 SPI_SK0 HOST_SPI0 HOST_SPI PU_0 PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_0 PU_9 PU_ PU_ PU_ PU_ HOST_SPI_I HOST_SPI_O V u PIX_SIN PIX_SIN MEM_XS PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ MEM_XWR MEM_XR MEM_XS MEM_XS0 PU_ PU_ PU_ M EM_RY PIX_SOUT PIX_SOUT HOST_SPI HOST_SPI_SS PIX_SIN HOST_SPI HOST_SPI_SK PIX_SIN0 LKIN SPI_00 SPI_I0 PIX_SOUT SPI_0 S PI_O0 0 9 PIX_SOUT0 SPI_0 SPI_SS0 SPI_0 SPI_SK0 VIN0_ TSG_R_ VIN0_ TSG_R_ VIN0_ TSG_R_ 0 9 VIN0_ ISP_SYN_R_ LKP VIN0_ ISP_SYN_R_ LKN VIN0_ ISP_SYN_R_ E0 VIN0_ ISP_SYN_R_0 HSYN0 VIN0_ LK0 ISP_SYN_R_ G VO VIN0_0 ISP_SYN_R_ VSYN0 9 9 TSG_R_ OUT_R_ 9 9 TST_R OUT_R_ 9 9 PWMO OUTG_R_ 9 9 OUT_R_ OUT_R_ OUT_R_ OUTG_R_ 0 0 OUT_R_ OUTG_R_ 0 0 OUTG_R_ OUTR_R_ OUTR_R_ OUTG_R_ OUTG_R_ LKO_R 0 09 OUTR_R_ SYN_R_0 G V OUTR_R_ VIN0_9 VINHSYN0 OUTR_R_ VIN0_0 VINVSYN OUTR_R_ VIN0_ VINFI0 SYN_R_ VSYN SYN_R_ E 0 9 SYN_R_ HSYN 0 00n X00 QSH-00-0-F---K PIXGN MEM_XS0 MEM_XS MEM_XR MEM_XWR MEM_XS M EM_RY PIX_SIN0 PIX_SIN PIX_SIN PIX_SIN PIX_SOUT0 PIX_SOUT PIX_SOUT PIX_SOUT TST_R PWMO PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_0 PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_ MEM_TRL0 MEM_TRL MEM_TRL MEM_TRL MEM_TRL MEM_TRL PU_[..0] MEM_TRL[..0] PIX_SIN[..0] PIX_SOUT[..0] PU_[..0] MEM_TRL[..0] M EM_RY PIX_SIN[..0] PIX_SOUT[..0] TST_R PWMO Gartenstrasse 0 - Neumünster XXSvideo-: PU Extension Size ocument Number R ev 00 P ate: Tuesday, ugust, 009 Sheet of

3 V 00 0u 0 00n 0 n V 0 p R00 R0 R0 R0 R0 k k k k k9 RUN VIN ITH VF VF ITH LT GN SW PHSE GN FREQ PGOO L R0 0 00u 0 00u 0 00n 0 00n V V V R0 k 00u 0 n R0 0k RUN SW 0 V 09 p 00n VIN U00 LTEH GN MOE/SYN 9 L0 000 R09 V R SRM supply V_ORE_PG V_ORE_PG V PU core supply V V R0 k RESET M0 GN MR V WI 0 00n WI WI U0 M0Y9RJZ-R H00 Hole.mm H0 Hole.mm H0 Hole.mm H0 Hole.mm Outer diameter??? L0 900 Inenn GN Gartenstrasse 0 - Neumünster XXSvideo-: Power Size ocument Number Rev 00 P ate: Tuesday, ugust, 009 Sheet of

4 TESTMOE_ JTGSEL JTG[..0] MEM_TRL[..0] M EM_RY INT_[..0] PU_[..] PU_[..0] MPX_MOE [..0] TESTMOE_ JTGSEL JTG[..0] MEM_TRL[..0] M EM_RY INT_[..0] PU_[..] PU_[..0] MPX_MOE [..0] TESTMOE_ JTGSEL JTG[..0] MEM_TRL[..0] MEM_RY INT_[..0] PU_[..] PU_[..0] MPX_MOE [..0] JE- MR0 URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] N_RX[..0] N_TX[..0] SPI_0[..0] SPI_[..0] HOST_SPI[..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] N_RX[..0] N_TX[..0] S PI_0[..0] S PI_[..0] HOST_SPI[..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] N_RX[..0] N_TX[..0] S PI_0[..0] S PI_[..0] HOST_SPI[..0] R SRM R_VREF[..0] R_TRL[9..0] M[..0] MQ[..0] Reference I: xx #0 MPX_MOE [..0] Flash URT_GPIO_[..0] PU_[..] PU_[..0] MEM_XS MEM_XR RSY# R_VREF[..0] R_TRL[9..0] M[..0] MQ[..0] URT_GPIO_[..0] PU_[..] PU_[..0] MEM_XS MEM_XR RSY# R_VREF[..0] R_TRL[9..0] M[..0] MQ[..0] RSY# Graphics ontroller IS_[..0] ML[..0] PIX_SIN[..0] PIX_SOUT[..0] TST_R VIN0_[..0] VIN_[..0] LKO_R LKIN SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] ISP_SYN_R_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TRE[..0] PWMO[..0] TSG_R_[..] IS_[..0] ML[..0] PIX_SIN[..0] PIX_SOUT[..0] TST_R VIN0_[..0] VIN_[..0] LKO_R LKIN SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] ISP_SYN_R_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TRE[..0] PWMO[..0] PWMO0 PWMO PWMO TSG_R_[..] TSG_R_ TSG_R_ TSG_R_ TSG_R_ IS_[..0] ML[..0] PIX_SIN[..0] PIX_SOUT[..0] TST_R VIN0_[..0] VIN_[..0] LKO_R LKIN SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] ISP_SYN_R_[..0] ISP_P_R_[..0] ISP_N_R_[..0] T RE[..0] PWMO[..0] PWMO[..0] PWMO TSG_R_[..] TSG_R_[..] Reference I: 0x # top # TSG_R_[..] TSG_R_[..] TSG_R_ TSG_R_9 TSG_R_0 TSG_R_ TSG_R_ MEM_TRL[..0] MEM_TRL MEM_TRL MEM_TRL0 MEM_TRL MEM_TRL MEM_TRL MEM_XS MEM_XS MEM_XS0 MEM_XR MEM_XWR Gartenstrasse 0 - Neumünster XXSvideo-: JE Subsystem Size ocument Number R ev 00 P ate: Tuesday, ugust, 009 Sheet of

5 TESTMOE_ MPX_MOE [..0] VIN0_[..0] VIN_[..0] OUT_R_[..] OUTG_R_[..] OUTR_R_[..] LKIN LKO_R SYN_R_[..0] N_RX[..0] N_TX[..0] ML[..0] S PI_0[..0] S PI_[..0] HOST_SPI[..0] P WMO[..0] IS_[..0] T RE[..0] TESTMOE_ MPX_MOE [..0] VIN0_[..0] VIN_[..0] OUT_R_[..] OUTG_R_[..] OUTR_R_[..] LKIN LKO_R SYN_R_[..0] N_RX[..0] N_TX[..0] ML[..0] S PI_0[..0] S PI_[..0] HOST_SPI[..0] PWMO[..0] IS_[..0] TRE[..0] TESTMOE_ MPX_MOE [..0] VIN0_[..0] VIN_[..0] OUT_R_[..] OUTG_R_[..] OUTR_R_[..] LKIN LKO_R SYN_R_[..0] N_RX[..0] N_TX[..0] ML[..0] SPI_0[..0] SPI_[..0] HOST_SPI[..0] PWMO[..0] IS_[..0] TRE[..0] JE- Part JE- Part R_VREF[..0] R_TRL[9..0] M[..0] MQ[..0] ISP_SYN_R_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TSG_R_[..] R_VREF[..0] R_TRL[9..0] M[..0] MQ[..0] ISP_SYN_R_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TSG_R_[..] R_VREF[..0] R_TRL[9..0] M[..0] MQ[..0] ISP_SYN_R_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TSG_R_[..] Reference I: 00 # Reference I: 00 # TST_R PIX_SIN[..0] PIX_SOUT[..0] JTGSEL JTG[..0] MEM_TRL[..0] M EM_RY RSY# PU_[..] PU_[..0] INT_[..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] TST_R PIX_SIN[..0] PIX_SOUT[..0] JTGSEL JTG[..0] MEM_TRL[..0] M EM_RY RSY# PU_[..] PU_[..0] INT_[..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] TST_R PIX_SIN[..0] PIX_SOUT[..0] JTGSEL JTG[..0] MEM_TRL[..0] MEM_RY RSY# PU_[..] PU_[..0] INT_[..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] JE- Part JE- Part- Power Reference I: 00 # Reference I: 00 #9 Gartenstrasse 0 - Neumünster XXSvideo-: JE Subsystem: JE Size ocument Number R ev 00 P ate: Tuesday, ugust, 009 Sheet of

6 TESTMOE_ MPX_MOE [..0] LKIN TESTMOE_ MPX_MOE [..0] LKIN MPX_MOE 0 MPX_MOE TESTMOE_0 TESTMOE_ TESTMOE_ TESTMOE_ TESTMOE_ E E TESTMOE_0 TESTMOE_ TESTMOE_ TESTMOE_ TESTMOE_ MR0 JE- Part of V V V V V LKO_R SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] VIN0_[..0] VIN_[..0] PWMO[..0] IS_[..0] LKO_R SYN_R_[..0] OUTR_R_[..] OUTG_R_[..] OUT_R_[..] VIN0_[..0] VIN_[..0] PWMO[..0] IS_[..0] SYN_R_ SYN_R_ SYN_R_ SYN_R_0 OUTR_R_ OUTR_R_ OUTR_R_ OUTR_R_ OUTR_R_ OUTR_R_ OUTG_R_ OUTG_R_ OUTG_R_ OUTG_R_ OUTG_R_ OUTG_R_ OUT_R_ OUT_R_ OUT_R_ OUT_R_ OUT_R_ OUT_R_ VIN0_0 VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_9 VIN0_0 VIN0_ VIN_0 VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_9 VIN_0 VIN_ PWMO0 PWMO PWMO IS_0 IS_ IS_ IS_ IS_ E HSYN VSYN GV LKO_R OUTR_R_ SYN_R_ SYN_R_ SYN_R_ OUTG_R_ OUTR_R_ OUTR_R_ OUTR_R_ OUT_R_ OUT_R_ OUTG_R_ OUTG_R_ SYN_R_0 OUTR_R_ OUTR_R_ OUTG_R_ OUTG_R_ OUT_R_ OUTG_R_ OUT_R_ OUT_R_ OUT_R_ LKO R0 R OUTR_ SYN_ SYN_ SYN_ RN0 Rx OUTG_ OUTR_ OUTR_ OUTR_ RN0 Rx OUT_ OUT_ OUTG_ OUTG_ RN0 Rx SYN_0 OUTR_ OUTR_ OUTG_ RN0 Rx OUTG_ OUT_ OUTG_ OUT_ RN0 Rx OUT_ R R OUT_ R R No pin for PWMO / URT_SOUT available at connector VP MPX_MOE 0 MPX_MOE MPX_MOE 0 MPX_MOE LKIN LKO SYN_ SYN_ SYN_ SYN_0 OUTR_ OUTR_ OUTR_ OUTR_ OUTR_ OUTR_ OUTG_ OUTG_ OUTG_ OUTG_ OUTG_ OUTG_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ VIN0_0 VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_ VIN0_9 VIN0_0 VIN0_ VIN_0 VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_9 VIN_0 VIN_ PWMO0 PWMO PWMO IS_0 IS_ IS_ IS_ IS_ LK0 VINHSYN0 VINVSYN0 VINFI0 LK VINHSYN VINVSYN VINFI TP00 IS_SO IS_ELK IS_SK IS_WS IS_SI F K K U U J J J J H H H H G G G G F F F F E E F E F E F E F 0 0 E0 F0 F Multiplex setting-related pins VP MPX_MOE 0 MPX_MOE MPX_MOE 0 MPX_MOE LKIN LKO MPX_MOE_[:0] "00" ISP / "0" MEM_bit Ext. / "0" ISP E / XK_ / E HSYN / REQ_ / HSYN VSYN / XK_ / VSYN GV / REQ_ / GV OUTR_ / MEM_E_ / OUTR_ dbg_mux0 OUTR_ / MEM_E_0 / OUTR_ dbg_select OUTR_ / MEM_E_9 / OUTR_ OUTR_ / MEM_E_ / OUTR_ OUTR_ / MEM_E_ / OUTR_ OUTR_ / MEM_E_ / OUTR_ OUTG_ / MEM_E_ / OUTG_ OUTG_ / MEM_E_ / OUTG_ dbg_mux OUTG_ / MEM_E_ / OUTG_ OUTG_ / MEM_E_ / OUTG_ OUTG_ / MEM_E_ / OUTG_ OUTG_ / MEM_E_0 / OUTG_ OUT_ / MEM_E_9 / OUT_ OUT_ / MEM_E_ / OUT_ OUT_ / MEM_E_ / OUT_ OUT_ / MEM_E_ / OUT_ OUT_ / MEM_XWR_ / OUT_ OUT_ / MEM_XWR_ / OUT_ MPX_MOE_[:0] MPX_MOE_[:0] "00" / "0" / "0" MPX_MOE_[0] "0" / "" VIN0_0 / VIN0_0 / MEM_E_ / VIN0_0 / GI_ VIN0_ / VIN0_ / MEM_E_ / VIN0_ / GI_ VIN0_ / VIN0_ / MEM_E_ / VIN0_ / RI_ VIN0_ / VIN0_ / MEM_E_ / VIN0_ / RI_ VIN0_ / VIN0_ / MEM_E_0 / VIN0_ / RI_ VIN0_ / VIN0_ / MEM_E_9 / VIN0_ / RI_ VIN0_ / VIN0_ / MEM_E_ / VIN0_ / RI_ VIN0_ / VIN0_ / MEM_E_ / VIN0_ / RI_ LK0 / LK0 / 0 / LK0 / 0 VINHSYN0 / VINHSYN0 /MEM_E_ /VINHSYN0 / GI_ VINVSYN0 / VINVSYN0 /MEM_E_ / VINVSYN0 / GI_ VINFI0 / VINFI0 / MEM_E_ / VINFI0 / GI_ VIN_0 / VIN_0 / MEM_XWR_ / VIN_0 / 0 VIN_ / VIN_ / MEM_XWR_ / VIN_ / I_ VIN_ / VIN_ / REQ_ / VIN_ / I_ VIN_ / VIN_ / XK_ / VIN_ / I_ VIN_ / VIN_ / MEM_E_ / VIN_ / I_ VIN_ / VIN_ / MEM_E_ / VIN_ / I_ VIN_ / VIN_ / MEM_E_0 / VIN_ / I_ VIN_ / VIN_ / MEM_E_9 / VIN_ / GI_ LK / LK / 0 / LK / LK VINHSYN / VINHSYN / REQ_ / VINHSYN / VINHSYN VINVSYN / VINVSYN / X_ / VINVSYN / VINVSYN VINFI / VINFI / MEM_E_ / VINFI / VINFI MPX_MOE_[0] "0" / "" PWMO0 / URT_SIN PWMO / URT_SOUT PWMO / URT_SIN PWMO / URT_SOUT MPX_MOE_[0] "0" "" IS_SO / PWM_0 IS_ELK / PWM_0 IS_SK / PWM_0 IS_WS / PWM_0 IS_SI / 0 R9 R0 R0 R0 k k k k TESTMOE_0 TESTMOE_ TESTMOE_ TESTMOE_ TESTMOE_ R R TESTMOE_ 0 => little endian, => bid endian RN00 0kx MPX_MOE 0 MPX_MOE MPX_MOE 0 VP MPX_MOE R R0 R0 V R09 NP R0 NP R0 R0 R k R SPI_0[..0] SPI_[..0] HOST_SPI[..0] ML[..0] SPI_0[..0] SPI_[..0] HOST_SPI[..0] ML[..0] SPI_00 SPI_0 SPI_0 SPI_0 SPI_0 SPI_ SPI_ SPI_ HOST_SPI0 HOST_SPI HOST_SPI HOST_SPI SPI_00 SPI_0 SPI_0 SPI_0 SPI_0 SPI_ SPI_ SPI_ HOST_SPI0 HOST_SPI HOST_SPI HOST_SPI SPI_I0 SPI_O0 SPI_SS0 SPI_SK0 SPI_I SPI_O SPI_SS SPI_SK HOST_SPI_I HOST_SPI_O HOST_SPI_SS HOST_SPI_SK F E F9 E9 9 9 E F MPX_MOE_[0] MPX_MOE_[:0] "0,XX" / ",0X" SPI_I0 / GPIO_P_0 SPI_O0 / GPIO_P_ SPI_SS0 / GPIO_P_ SPI_SK0 / GPIO_P_ MPX_MOE_0[:0] MPX_MOE_[:0] "00,XX" / "0,0X" / "0,XX" SPI_I / SPI_I / S_WP SPI_O / SPI_O / S_XM SPI_SS / SPI_SS / S_M SPI_SK / SPI_SK / S_LK MPX_MOE_[0] MPX_MOE_[:0] "0,XX" / ",0X" HOST_SPI_I / GPIO_P_9 HOST_SPI_O / GPIO_P_0 HOST_SPI_SS / GPIO_P_ HOST_SPI_SK / GPIO_P_ N_RX[..0] N_RX[..0] ML0 ML ML ML0 ML ML ML_T ML_SIG ML_LK F E E ML ML_T ML_SIG ML_LK N_TX[..0] N_TX[..0] N_RX0 N_RX N_TX0 N_TX N_RX0 N_TX0 N_RX N_TX 9 9 F9 E9 N N_RX0 N_TX0 N_RX N_TX TRE[..0] TRE[..0] TRE TRE TRE TRE TRE TRE0 TRE TRE TRE TRE TRE TRE0 TRELK TRETL TRET_ TRET_ TRET_ TRET_0 R0 R MPX_MOE_[0] "0" / "" TRELK TRETL TRET_ / PWM_0 TRET_ / PWM_0 TRET_ / PWM_0 TRET_0 / PWM_0 U00 Jade- Gartenstrasse 0 - Neumünster XXSvideo-: JE- Subsystem: JE-: JE- Part Size ocument Number Rev 00 P Tuesday, ugust, 009 ate: Sheet of

7 JTG[..0] JTGSEL MEM_TRL[..0] JTG[..0] JTGSEL MEM_TRL[..0] JTG0 JTG JTG JTG JTG JTG JTG MEM_TRL MEM_TRL MEM_TRL0 MEM_TRL MEM_TRL MEM_TRL R TK XSRST TK XTRST TMS TI T O MEM_XS MEM_XS MEM_XS0 MEM_XR MEM_XWR V R k NP R9 k NP PIXGN PIXGN XTL_LK M00 V R k PLLTTRST n JTG0 JTG 9 n JTG JTG JTG V JTG JTG RIPM0 RIPM RIPM RIPM LK_SEL ELK OS_FILTER OS_IS0 OS_IS OS_MOE0 OS_MOE R TK XSRST TK XTRST TMS TI T O JTGSEL E K E System-related pins RIPM_0 RIPM_ RIPM_ RIPM_ XRST PLLTTRST LK_SEL ELK OS_FILTER OS_IS0 OS_IS OS_MOE0 OS_MOE XTL0 XTL IE-related pins RTK XSRST JTG-related pins TK XTRST TMS TI TO JTGSEL MR0 JE- Part of V RIPM0 RIPM RIPM RIPM R R R R V RN 0kx JTGSEL XSRST XTRST R0 NP RN0 0kx INT_0 INT_ INT_ INT_ RN 0kx M00 OS_IS0 OS_IS OS_MOE0 OS_MOE R0 NP R NP R NP R RN 0kx R LK_SEL V R k OS_FILTER R k R9 NP RSY# MEM_RY PU_[..] PU_[..0] INT_[..0] RSY# MEM_RY PU_[..] PU_[..0] INT_[..0] R PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_0 PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_ INT_0 INT_ INT_ INT_ MEM_RY MEM_RY R k MEM_TRL MEM_TRL MEM_TRL0 MEM_TRL MEM_TRL MEM_TRL M0 MEM_XS MEM_XS MEM_XS0 MEM_XR MEM_XWR R R R R F F F E E E E F E External bus interface-related pins MEM_XS_ MEM_XS_ MEM_XS_0 MEM_XR MEM_XWR_ MEM_XWR_0 MEM_RY MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_9 MEM_E_0 MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_9 MEM_E_0 MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_0 MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_9 MEM_E_0 MEM_E_ MEM_E_ MEM_E_ MEM_E_ MEM_E_ ExIR-related pins INT 0 INT INT INT R k NP R9 V R k NP R 00n NP L0 LMPG00SN 0 GN V WP SL S U TS00-SU n 0 00n V 00n I_SL0 I_S0 0u GN _V0 I_SL0 R0 k I_S0 R k I_SL R k Place filter circuits directly to the corresponding U00 pins! I_S R9 k TST_R PIX_SIN[..0] PIX_SOUT[..0] TST_R PIX_SIN[..0] PIX_SOUT[..0] PIXGN PIX_SIN0 PIX_SIN PIX_SIN PIX_SIN VM0 00n SIN0P SIN0M SINP SINM PIXGN VM 00n PIXGN VM0 VM TST_R R k % R PIX VM0 VM RREF TST SIN0P SIN0M SINP SINM V URT_0[..0] URT_[..0] URT_GPIO_[..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] PIX_SOUT0 PIX_SOUT PIX_SOUT PIX_SOUT URT_00 URT_0 URT_0 URT_0 URT_0 URT_ SOUT0P SOUT0M SOUTP SOUTM URT_SIN0 URT_SOUT0 URT_TS0# URT_RTS0# URT_SIN URT_SOUT E9 9 E F E F E SOUT0P SOUT0M SOUTP SOUTM URT-related pins MPX_MOE_9[:0] MPX_MOE_[:0] "00,XX" / "0,0X" / "0,,XX" URT_SIN0 / GPIO_P_ / URT_SIN0 URT_SOUT0 / GPIO_P_ / URT_SOUT0 URT_XTS0 / GPIO_P_ / URT_SIN URT_XRTS0 / GPIO_P_ / URT_SOUT MPX_MOE_0[:0] MPX_MOE_[:0] "00,XX" / "0,0X" / "0,XX" URT_SIN / GPIO_P_ / S_T_0 URT_SOUT / GPIO_P_ / S_T_ V L LMPG00SN 0 00n OE GN OS V OUT Y0 SG-0 SF.00MHz R R ELK Place R directly to Y0 pin! I_0[..0] I_[..0] I_0[..0] I_[..0] URT_GPIO_0 URT_GPIO_ I_00 I_0 I_0 I_ URT_SIN URT_SOUT I_SL0 I_S0 I_SL I_S 0 0 F0 E0 URT_SIN / GPIO_P_ / S_T_ URT_SOUT / GPIO_P_9 / S_T_ I-related pins I_SL0 I_S0 I_SL I_S L LMPG00SN 00n OE GN OS V OUT Place R directly to Y pin! XTL_LK [9..0] L 900 Inenn [9..0] GN 0 _VRH0 _VRL0 _VIN0 _VR0 _VRH _VRL _VIN _VR _VIN 9 _VIN nalog signal to be shielded in P layout! GN _V0 / converter-related pins F V F VS E _VRH0 _VRL0 _VIN0 _VR0 E _VRH _VRL _VIN _VR _VIN _VIN U00 Jade- PIXGN Y SG-0 SF.000MHz Gartenstrasse 0 - Neumünster R R PIXGN 00n NP PIXGN XXSvideo-: JE- Subsystem: JE-: JE- Part M00 Size ocument Number Rev 00 P Tuesday, ugust, 009 ate: Sheet of

8 R_VREF[..0] R_TRL[9..0] R_VREF[..0] R_TRL[9..0] R_VREF0 R_VREF V R k NP O TONT R 0 R 0 V R0 k NP R NP R9 k R R k F P N E R-related pins RTYPE O OT OTONT ILLRST MKE_STRT MR0 JE- Part of V V V V R R k 0 k 00n 00n R_VREF0 R_VREF M[..0] MQ[..0] M[..0] MQ[..0] R_TRL0 MK R_TRL MK# R_TRL MKE R_TRL MS# R_TRL MWE# R_TRL MRS# R_TRL MS# R_TRL MM0 R_TRL MM R_TRL9 MM R_TRL0 MM R_TRL MQS0 R_TRL MQS#0 R_TRL MQS R_TRL MQS# R_TRL MQS R_TRL MQS# R_TRL MQS R_TRL MQS# R_TRL9 O TONT M0 M M M M M M M M M9 M0 M M M M M0 M M MK MK# R_VREF R_VREF0 R0 R MM0 MM MM MM MQS0 MQS MQS MQS MQS#0 MQS# MQS# MQS# MS# MKE MRS# MS# MWE# M0 M M0 M M M M M M M M M9 M0 M M M K V R N R P V R K G W T K G Y U L H E E F E F E VREF VREF0 MKP MKN MM_0 MM_ MM_ MM_ MQSP_0 MQSP_ MQSP_ MQSP_ MQSN_0 MQSN_ MQSN_ MQSN_ MS MKE MRS MS MWE M_0 M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_9 M_0 M_ M_ M_ R k 00n R k 00n ISP_SYN_R_[..0] ISP_P_R_[..0] ISP_N_R_[..0] ISP_SYN_R_[..0] ISP_P_R_[..0] ISP_N_R_[..0] MQ0 MQ MQ MQ MQ MQ MQ MQ MQ MQ9 MQ0 MQ MQ MQ MQ MQ MQ MQ MQ MQ9 MQ0 MQ MQ MQ MQ MQ MQ MQ MQ MQ9 MQ0 MQ ISP_SYN_R_0 ISP_SYN_R_ ISP_SYN_R_ ISP_SYN_R_ ISP_SYN_R_ ISP_SYN_R_ ISP_P_R_0 ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_9 ISP_P_R_0 ISP_P_R_ ISP_N_R_0 ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_9 ISP_N_R_0 ISP_N_R_ HSYN0 VSYN0 GVO0 LKP LKN E0 ISP_P_n and ISP_N_n has to routed parallel! ISP_P_R_ ISP_N_R_ ISP_P_R_0 ISP_N_R_0 ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ ISP_P_R_0 ISP_N_R_0 ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ ISP_P_R_9 ISP_N_R_9 ISP_P_R_ ISP_N_R_ TSG_R_ TSG_R_9 TSG_R_ ISP_SYN_R_ TSG_R_ ISP_SYN_R_ ISP_SYN_R_ RN0 RN RN RN RN RN RN x x x x x x x ISP_P_ ISP_N_ ISP_P_0 ISP_N_0 ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_0 ISP_N_0 ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_9 ISP_N_9 ISP_P_ ISP_N_ TSG_ TSG_9 TSG_ ISP_SYN_ TSG_ ISP_SYN_ ISP_SYN_ MQ0 MQ MQ MQ MQ MQ MQ MQ MQ MQ9 MQ0 MQ MQ MQ MQ MQ MQ MQ MQ MQ9 MQ0 MQ MQ MQ MQ MQ MQ MQ MQ MQ9 MQ0 MQ ISP_SYN_0 ISP_SYN_ ISP_SYN_ ISP_SYN_ ISP_SYN_ ISP_SYN_ ISP_P_0 ISP_N_0 ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_ ISP_N_ ISP_P_9 ISP_N_9 ISP_P_0 ISP_N_0 ISP_P_ ISP_N_ W W Y Y W Y V V T T U U T U R R L L M M L M L K H H J J H J G G W V W U U V L L L L M M M M N N N N P P P P R R R R T T T T MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_9 MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_9 MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_9 MQ_0 MQ_ isplay-related pins MPX_MOE_[:0] "00" / "0" / "0" / "" HSYN0 / 0 / 0 / 0 VSYN0 / 0 / 0 / 0 GV0 / 0 / 0 / 0 LKP / LKP / 0 / 0 LKOUT0 LKN / LKN / 0 / 0 LKOUT0 E0 / 0 / 0 / 0 ISP0P / PIX0_S_0 / PIX0_S_0 / GPIO_P_0 OUTR0_0 ISP0N / PIX0_S_ / PIX0_S_ / GPIO_P_ OUTR0_ ISPP / ISPP / GPIO_P_ / GPIO_P_ OUTR0_ ISPN / ISPN / GPIO_P_ / GPIO_P_ OUTR0_ ISPP / ISPP / GPIO_P_ / GPIO_P_ OUTR0_ ISPN / ISPN / GPIO_P_ / GPIO_P_ OUTR0_ ISPP / ISPP / GPIO_P_ / GPIO_P_ OUTR0_ ISPN / ISPN / GPIO_P_ / GPIO_P_ OUTR0_ ISPP / PIX0_S_ / PIX0_S_ / GPIO_P_ OUTG0_0 ISPN / PIX0_S_ / PIX0_S_ / GPIO_P_9 OUTG0_ ISPP / ISPP / GPIO_P_0 / GPIO_P_0 OUTG0_ ISPN / ISPN / GPIO_P_ / GPIO_P_ OUTG0_ ISPP / ISPP / GPIO_P_ / GPIO_P_ OUTG0_ ISPN / ISPN / GPIO_P_ / GPIO_P_ OUTG0_ ISPP / ISPP / GPIO_P_ / GPIO_P_ OUTG0_ ISPN / ISPN / GPIO_P_ / GPIO_P_ OUTG0_ ISPP / PIX0_S_ / PIX0_S_ / GPIO_P_ OUT0_0 ISPN / PIX0_S_ / PIX0_S_ / GPIO_P_ OUT0_ ISP9P / ISP9P / GPIO_P_ / GPIO_P_ OUT0_ ISP9N / ISP9N / GPIO_P_9 / GPIO_P_9 OUT0_ ISP0P / ISP0P / GPIO_P_0 / GPIO_P_0 OUT0_ ISP0N / ISP0N / GPIO_P_ / GPIO_P_ OUT0_ ISPP / ISPP / GPIO_P_ / GPIO_P_ OUT0_ ISPN / ISPN / GPIO_P_ / GPIO_P_ OUT0_ TSG_R_[..] TSG_R_[..] TSG_R_ TSG_R_ TSG_R_ TSG_R_ TSG_R_ TSG_R_9 TSG_R_0 TSG_R_ TSG_R_ RN x TSG_R_ TSG_R_0 TSG_R_ TSG_R_ RN x ISP_SYN_R_ ISP_SYN_R_ ISP_SYN_R_0 TSG_R_ RN9 x TSG_ TSG_0 TSG_ TSG_ ISP_SYN_ ISP_SYN_ ISP_SYN_0 TSG_ TSG_ TSG_ TSG_ TSG_ TSG_ TSG_9 TSG_0 TSG_ TSG_ W W Y Y Y Y MPX_MOE_[:0] MPX_MOE_[:0] "00,XX" / "0,0X" / "0,0X" TSG_ / LKIN0 / LKIN0 TSG_ / GPIO_P_0 / GPIO_P_0 TSG_ / GPIO_P_ / GPIO_P_ TSG_ / GPIO_P_ / PIX_S_0 TSG_ / GPIO_P_ / PIX_S_ TSG_9 / GPIO_P_ / PIX_S_ TSG_0 / GPIO_P_ / PIX_S_ TSG_ / GPIO_P_ / PIX_S_ TSG_ / GPIO_P_ / PIX_S_ Gartenstrasse 0 - Neumünster U00 Jade- XXSvideo-: JE Subsystem: JE: JE (R & Video) Size ocument Number Rev 00 P Tuesday, ugust, 009 ate: Sheet of

9 PV SV SV PV V V V VPIX VPIX GN GN V VPIX GN GN GN GN GN PIXGN PIXGN VPIX PIXGN PIXGN PIXGN PIXGN PIXGN V GN GN PIXGN Size ocument Number R ev ate: Sheet of 00 P XXSvideo-: JE Subsystem: JE: JE ( Power ) Gartenstrasse 0 - Neumünster 9 Tuesday, ugust, 009 Input voltage V 00 m Ouput voltage. V M0 M0 M0 0 00n L LMPG00SN 9 0u 00n 0u 0 n k NP R9 00n 9 00n 00 n n 00n n R9 0 0u 0 00n 09 n 00n 9 00n n 0u 0 00n 0 00n 00n 00n 90 00n 9 00n 00n L0 LMPG00SN 9 00n n 9 00n 00n 00n MR0 Part of JE- U 00 Jade- VE_0 F VE_ V VE_ E VE_ E VE_ VE_ E VE_ F VE_ L VE_ M VE_9 U VE_0 V VE_ VE_ VE_ 0 VE_ VE_ 9 VE_ E VE_ E0 VE_ E VE_9 M0 VE_0 N0 VE_ T0 VE_ U0 VE_ U VE_ U VE_ K VE_ K VE_ K VE_ K VE_9 K VSS_0 VSS_ VSS_ E VSS_ V VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_9 VSS_0 V VSS_ R VSS_ M VSS_ J VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_0 P VSS_ N VSS_ VSS_ VSS_ M VSS_ H VSS_ G VSS_ E9 VSS_ E VSS_9 E VSS_0 E VSS_ VSS_ J VSS_ K VSS_ R VSS_ T VSS_ VSS_ VSS_ VSS_9 VSS_0 VSS_ Y VSS_ W VSS_ R VSS_ L VSS_ M VSS_ N VSS_ P VSS_ R VSS_9 T VSS_0 T VSS_ T VSS_ T VSS_ T VSS_ T VSS_ R VSS_ P VSS_ N VSS_ M VSS_9 L VSS_0 L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ N VSS_ P VSS_ R VSS_ R VSS_9 R VSS_0 R VSS_ P VSS_ N VSS_ M VSS_ M VSS_ M VSS_ N VSS_ P VSS_ P VSS_9 N PIXV_0 VI_0 G VI_ H VI_ N VI_ P VI_ W VI_ Y VI_ VI_ 9 VI_ 0 VI_9 VI_0 P VI_ N VI_ F VI_ E VI_ E VI_ E VI_ K0 VI_ L0 VI_ P0 VI_9 R0 VI_0 U VI_ U VI_ U VI_ U VI_ R VI_ P VI_ L VI_ K VI_ K VI_9 K RVE P RVE N RVE K RVE J RVE U RVE T RVE N RVE M RVE RVE RVE U RVE T PIXV_0 PIXV_ 0 PIXV_ PIXV_ 0 PIXVSS_0 PIXVSS_ 0 PIXVSS_ PIXVSS_ 9 PIXVSS_ E PIXVSS_ E0 SV SVS PV E PVS E 9 n 00n 00n L LMPG00SN 0 n 00n L LMPG00SN 0 00n 0u 9 00n n L LMPG00SN n 99 0u 0 n 0u 9 n 0 0u LT U0 LTS Out SENSE/J GN YP SHN GN GN IN 9 00n 0 0u n 0 0u 9 00n 00n 0u

10 R_VREF[..0] R_TRL[9..0] O TONT R_VREF0 MQ[..0] M[..0] M MQ M M0 MQ0 MS#_T MQ M MQ M M_T MQ M0 MQ M M MQ MQS#_T MQ M M MWE#_T M_T M_T M M9 MQ M_T M_T9 M M MRS#_T MQ MQ MQ0 MQ MQ MQ MQS_T MS#_T M_T M_T MQ0 MQ M MQ MQ MQ9 M_T0 M_T0 MQ MQ9 MQ M_T0 M_T MQ M0 O TONT M MQ M_T MQ R_VREF0 MQ MQ9 MQ MQ M_T M_T M_T MQ0 R_VREF M_T MQ M R_VREF MM_T MKE_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T0 MQ_T9 MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T0 MQ_T0 MQ_T9 MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T0 MQ_T9 MQ_T MQ_T MQ_T MQ_T MM_T MQS_T MQS_T# M_T M_T M_T M0 M M M0 M M M M M M9 M M M M M0 M MKE MS# MWE# MRS# MS# MM0 MM MQS MQS# MQS0 MQS#0 M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T9 M_T0 M_T M_T M_T M_T M_T0 M_T M_T MQS_T MQS#_T MQS_T0 MQS_T#0 MKE_T MS#_T MWE#_T MRS#_T MS#_T MM_T0 MM_T MRS#_T MS#_T MM_T0 MM_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T9 M_T0 M_T M_T M_T M_T0 MQS_T MQS#_T MQS_T0 MQS_T#0 MKE_T MS#_T MWE#_T M_T MK R_TRL0 MQS# R_TRL MKE R_TRL MK# R_TRL MQS# R_TRL MM R_TRL0 MM0 R_TRL O TONT R_TRL9 MQS R_TRL MQS#0 R_TRL MM R_TRL MWE# R_TRL MQS# R_TRL MQS R_TRL MQS0 R_TRL MQS R_TRL MRS# R_TRL MM R_TRL9 MS# R_TRL MS# R_TRL MQS MQS MQS# MQS# MM MM MM_T MM_T MQS_T# MQS_T MQS#_T MQS_T MQ MQ MQ MQ MQ MQ0 MQ9 MQ MQ MQ MQ MQ MQ MQ MQ0 MQ MQ_T0 MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T MQ_T0 MQ_T MQ_T9 MQ_T MQ MQ9 MQ0 MQ MQ MQ MQ MQ MQ MQ MQ0 MQ MQ9 MQ MQ MQ MQ_T MQ_T MQ_T MQ_T MQ_T9 MQ_T MQ_T0 MQ_T MQ_T0 MQ_T MQ_T MQ_T9 MQ_T MQ_T MQ_T MQ_T MK MK MK# MK# M[..0] MQ[..0] R_VREF[..0] R_TRL[9..0] V V V V V Size ocument Number Rev ate: Sheet of 00 P XXSvideo: PU Subsystem-: R SRM Gartenstrasse 0 - Neumünster 0 Tuesday, ugust, 009 Place capacitors directly to R SRM power pins! R layout according to application note! low HW high HW XXSvideo: R0 + R = 0 NP MTHMN- MTHMN- 00n R0 k NP 0 n R SRM FG 0 x U00 R Mbit (x) P N N N N M M 0 M Q0 G Q F9 R R R R P 0 M 9 P P Q G Q H Q H Q H Q H9 Q F 0 L Q Q9 Q0 Q Q Q 9 Q Q 9 K J KE K S L S L L V J9 WE K LM F VSS VSS J VSS E V R RS K N N E L K K OT K9 UM UQS UQS LQS F LQS E V V E V M9 VL J VQ 9 VQ VQ VQ VQ 9 VQ E9 VQ G VQ G VQ9 G VQ0 G9 VREF J VSSL J VSS N VSS P9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E VSSQ F VSSQ F VSSQ9 H VSSQ0 H n R0 9R9 RN0 Rx 0u 00n L00 LMPG00SN RN0 Rx RN Rx 9 00n 0 00n R 9R9 RN0 Rx RN Rx RN Rx R0 k NP R0 0u RN0 Rx 0 00n RN09 Rx 09 00n 00n R0 9R9 0 0u n R0 k NP 0 n L0 LMPG00SN 0 00n n R0 R 9R9 0 0u RN00 Rx n RN0 Rx RN Rx 00 00n RN0 Rx RN Rx 0 00n R00 RN0 Rx RN Rx 00n RN0 Rx 0 n R0 k NP R SRM FG 0 x U0 R Mbit (x) P N N N N M M 0 M Q0 G Q F9 R R R R P 0 M 9 P P Q G Q H Q H Q H Q H9 Q F 0 L Q Q9 Q0 Q Q Q 9 Q Q 9 K J KE K S L S L L V J9 WE K LM F VSS VSS J VSS E V R RS K N N E L K K OT K9 UM UQS UQS LQS F LQS E V V E V M9 VL J VQ 9 VQ VQ VQ VQ 9 VQ E9 VQ G VQ G VQ9 G VQ0 G9 VREF J VSSL J VSS N VSS P9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E VSSQ F VSSQ F VSSQ9 H VSSQ0 H RN0 Rx 0 00n R09 n R0

11 PU_[..0] PU_[..0] PU_[..] PU_[..] URT_GPIO_[..0] URT_GPIO_[..0] URT_GPIO_0 URT_GPIO_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ E E F G : Mbit : Mbit : Gbit S L9GLxxxM FPG Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q E H E H H E H E F G F G F G F G PU_0 PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_ PU_9 PU_0 PU_ PU_ PU_ PU_ PU_ MEM_XR RSY# MEM_XR RSY# V R00 k R0 k S IT_FLSH_N MEM_XR RSY# F G F E OE WE WP/ RY/SY Reset YTE N N N N N N N N N9 H E H G MPX_MOE [..0] MPX_MOE [..0] U00 SL9GLxxxN V S S V S S V S S E H H G V V I O V I O F V MPX_MOE 0 MPX_MOE 00 00n V 0 0u 0 00n V -Input OR V G N MPX_MOE 0 MPX_MOE I0 I I Y 0 00n U0 NSZPX_NL -Input OR I0 I I V G N Y S IT_FLSH_N MEM_XS MEM_XS U0 NSZPX_NL oeker Stieg - ukrug XXSvideo-: JE Subsystem: Flash Size ocument Number R ev 00 P ate: Tuesday, ugust, 009 Sheet of

12 PWMO[..0] PWMO[..0] WI V_ORE_PG TESTMOE_ WI V_ORE_PG TESTMOE_ TESTMOE VIN _VIN 9 R00 R0 NP OPT_PIN_0 V R0 OPT_PIN_ 00 R0 NP 0u PWMO0 PWMO IS_0 IS_ IS_ IS_ IS_ IS_[..0] IS_[..0] JTGSEL JTGSEL N_RX[..0] N_RX[..0] MPX_MOE [..0] MPX_MOE [..0] 0 00n N_RX0 N_RX N_TX[..0] N_TX[..0] JTG[..0] INT_[..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] ML[..0] JTG[..0] INT_[..0] URT_0[..0] URT_[..0] URT_GPIO_[..0] I_0[..0] I_[..0] [9..0] ML[..0] JTG0 JTG JTG JTG JTG JTG JTG INT_0 INT_ INT_ INT_ URT_00 URT_0 URT_0 URT_0 URT_0 URT_ URT_GPIO_0 URT_GPIO_ I_00 I_0 I_0 I_ 0 9 ML0 ML ML MPX_MOE 0 MPX_MOE RTK XSRST TK XTRST TMS T I TO U RT_SIN0 URT_SOUT0 URT_TS0# URT_RTS0# U RT_SIN URT_SOUT U RT_SIN URT_SOUT I_SL0 I_S0 I_SL I_S _VRH0 _VRL0 _VIN0 _VR0 _VRH _VRL _VIN _VR _VIN _VIN ML_T ML_SIG ML_LK 0 00n GN V V 0 00n I_S0 I_SL0 I_SL S PI_O SPI_I TSG_R_ TSG_R_9 URT_SOUT U RT_SIN URT_TS0# U RT_SIN0 URT_RTS0# URT_SOUT0 _VRH _VIN _VRH0 OPT_PIN_0 OPT_PIN_ ISP_P_R_0 ISP_N_R_0 ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ SPI_ SPI_0 ISP_P_R_ ISP_N_R_ N_RX N_TX ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ PWMO0 IS_ELK IS_ PWMO IS_SK IS_ IS_SO IS_0 VIN_ LK VIN_ MPX_MOE 0 MPX_MOE VIN_ VINFI JTGSEL XSRST XTRST T I V_ORE_PG WI Signals from XXSvideo pins 0,,,, are changed to pins n+ for ISP pair! X QSH-00-0-F---K INT_0 INT_ I_S INT_ INT_ TSG_R_0 TSG_R_ SPI_SK SPI_SS U RT_SIN URT_SOUT _VRL _VR _VRL0 _VR0 _VIN0 ISP_P_R_0 ISP_N_R_0 ISP_P_R_ ISP_N_R_ ISP_P_R_ ISP_N_R_ ISP_P_R_9 ISP_N_R_9 N_TX0 N_RX0 ISP_P_R_ ISP_N_R_ TSG_R_ VIN_9 VINHSYN IS_WS IS_ VIN_ VIN_0 VIN_0 VINVSYN IS_SI IS_ VIN_ VIN_ VIN_ VIN_ VIN_ ML ML_SIG ML ML_LK ML0 ML_T RTK TK TMS TO TRE0 TRET_0 TRE TRET_ TRE TRETL TRE TRET_ TRE TRE SPI_ SPI_ TRET_ TRELK GN LKP and LKN parallel N_TX0 N_TX SPI_I S PI_O SPI_SS SPI_SK ISP_P_R_0 ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_ ISP_P_R_9 ISP_P_R_0 ISP_P_R_ ISP_N_R_0 ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_ ISP_N_R_9 ISP_N_R_0 ISP_N_R_ TSG_R_ TSG_R_9 TSG_R_0 TSG_R_ TSG_R_ TRE0 TRE TRE TRE TRE TRE VIN_0 VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_ VIN_9 VIN_0 VIN_ SPI_0 SPI_ SPI_ SPI_ ISP_P_R_[..0] ISP_N_R_[..0] TSG_R_[..] S PI_[..0] TRE[..0] VIN_[..0] S PI_[..0] ISP_P_R_[..0] ISP_N_R_[..0] TSG_R_[..] T RE[..0] VIN_[..0] Pins,, and not useable for P reasons on Interface oard On XXSvideo MPX_MOE_ was configurable from external. Now MPX_MOE_ and not MPX_MOE_ is configurable from external. Gartenstrasse 0 - Neumünster XXSvideo-: I/O: I/O Extension Size ocument Number R ev 00 P ate: Tuesday, ugust, 009 Sheet of

Power. Video out. LGDC Subsystem

Power. Video out. LGDC Subsystem Power LE_UX# LG Evaluation System: Mainboard Revision: P Reference I: 00 # Video out LG Subsystem _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I/O ISP_LK I[..0] ISP_[..0]