HF SuperPacker Pro 100W Amp Version 3

Transcription

1 HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project and is available to Radio mateurs that sign up for the project. I consider this to be a medium to high skill level project. passion for building a quality project is prerequisite. Specifications imensions (inch) Overall: T Weight (lbs): T Power:. V 0 max. Reverse Polarity Protection. Power Pole connectors Power Supply: Internal 0 V range o Insensitive to battery condition; full output until the battery depleted (0 V) o phase / onverter: V max (computer control. Off during receive) HF and overage: 0, 0, 0, 0, 0, 0,,,, 0 M (00W) Option and overage: M, M, 0MHz (0W each). Seamless selection o User dd In Modules (up to ) Low Pass Filter uto selection: 0 0 M; 00W omputer ontrol, US, SPI ports o US Remote ontrol hoices US: HF Projects P ashboard US: Kenwood T commands support US: SR Interface o US choice US: Local ontrol Panel Module. inch QVG (0x0 color w/ touch control) SR Interface (alternate) Input rive: 00mW to 0W. uto Input Range Select o 0 ohm inary Pi Network daptor. Range: 0 to d in d steps Monitoring: In power, Out power, SWR, Temperature, Voltage, Frequency, urrent uto djustment: ias User djustments: Hang Time, Modes Two Transceiver Input Select Two ntenna Select External Fan ontrol Firmware field upgrade via US Environmental: No internal fan or venting to eliminate environmental contamination onstruction: RF Modules attached to skin for heat transfer to external heat sinks Indicators: LE Power Switch

2 uty ycle: ontinuous Spurious Products: 0 d or 00 watts RF ontrol: RF Sensing or PTT Relay and Selection: RF Sensing, FT and ata Voltage Level interface, Kenwood T Modes: SS, W, PSK Power Transistors: MOSFET ircuitry: lass, Push Pull; Impedance: 0 ohms input and output. onstruction: aluminum enclosure, external heat sinks, painted panels, silkscreens, all circuit boards and parts o Home onstruction Project, onstruction Manual via , Surface Mount installation option. ESRIPTIONS OVERVIEW MOSFET MP MOULE 0 schematic Refer to the attached schematic to follow the descriptions. The amplifier is a lass Linear mplifier using two R00HHF MOSFET transistors mounted on a thermal transfer block and the circuit board. The thermal transfer block is attached to a passive heat sink mounted on the skin of the case rear panel. The current passing through the MOSFETs is monitored by the voltage drop across a 0.0ohm resistor. The voltage drop is monitored by a high resolution analog to digital converter. The bias is controlled by a dual channel high resolution / converters. The temperature of each MOSFET is monitored by sensors attached to each MOSFET. The module is mounted to the rear panel and communicates with the ontroller via a pin flat cable. SPI interface is used to control the mp Module devices. The RF Input passes through a 0 ohm binary tree PI Network that has a range from 0 to d. The network is used to set the maximum RF power Input to the amplifier. The network auto ranges to protect the amplifier while configuring for the maximum RF input. rain Power to the board is directly from the phase / onverter that delivers V and up to current as required. The circuit board is four layer with a continuous ground plane. The thermal transfer block is a small aluminum block that moves the heat from the MOSFETs to the heat sink. The surfaces are milled flat for maximum conductivity. The internal RF connections are fabricated SM style cables. RF PTH schematic RF Output: The RF PTH is portion of the main board that mounts flat in the center of the amplifier enclosure. Refer to the RF PTH schematic to follow the descriptions. The amplifier RF Input attaches to the RF PTH circuits at MP IN, J. The mplifier output is connected directly to the Low Pass Filter and the output of the Low Pass Filter connects to LPF OUT, J. The LPF Output flows through T (Power Output Measurement) to K and K to one of two RF Output connectors (J and J). RF Input: The RF Input enters through one of two rear panel N connectors, J and J0. K selects one of the two RF Inputs to flow through to the amplifier input. The RF Input signal first encounters T which is a RF Tap. T steps up the voltage so that it may be monitored and measured by the controller. The

3 signal passes through T where the input power is measured. Relay K is a T/R switch that routes the RF Power Input to the mplifier input. The signals, and are power measurements that are routed to the controller nalog to igital onverter. is FT and ata Voltage Input that is measured by the ontroller to determine the low pass filter to select if the FT ontrol Mode is selected. ONTROLLER schematic The ontroller is Microhip PIFK. This is a 0 pin socket part which has major functionality of MHz clock speed, K program memory, K RM, K EEPROM, two SPI channels, two serial ports, 0 bit / conversion ( used) high current digital outs (V) and a frequency measurement input. The serial channels are interfaced to US chips (ual US IO). The mplifier Module has a sixteen pin flat cable interface to the ontroller through which the mplifier SPI components are controlled. The HF Filter Module has an eight pin flat cable interface that select the chosen filter. User efined SPI Port is available for expansion through an eight pin flat cable. For local programmer debug, there is an in circuit debug connector for connection to a Microchip I box. Power input to the board is V which is locally regulated to V. EXT INTERFE schematic The External IO schematic contains the RF frequency measurement logic and the generation of the R (carrier signal) from either the RF Input or the PTT input. UL US IO schematic This schematic has two identical US channels for interface with a P or isplay Module. ctivity LEs provided.

4 +V R& Prototype V V.0 VIN VOUT U L0 +V.0 SHN SHN +V V VREF VREF 0.uF VOUT E E R 00 Q.u.u - + U LM JP SK SO S SK SI VOUT 0 N0 +V 0.uF SI SO SHN G0 G 0 0 SK L G G L L VSS U MP.u.u.u R R.K U LT V VREF ONV IN+ SK IN- SO VSS SK SI G0 G G G V R K R K.u R 0 R0 0 Q R00HHF 0 000P 000P 000P MP IN SM N00 K N00 K N00 K N00 K T T R 00K 0.T J MP PWR R 0.0 MH MH MH Thermal Transfer lock 0P u 000P n 000P V_SW 000u 000P u 0.T 0.T T T. T SM MP OUT T. 0.T E R 00K E MH MH MH 0 u R R R d R R R 0 0 d R R R 0 0 d R R R R0 R R d.u R K R 0 000P 000P 000P R K R 0 Q R00HHF.u.u.u R to thermistors for Q Q H H +V +V 0.u +V.u R.K R.K - + U LM - + +V U LM H0 H V VSS SK IN OUT S/SHN U MP0 SK SO SI HF PROJETS - KOOR MOSFET MP MOULE 0 Size ocument Number Rev PGE 0 Friday, September 0, 0 ate: Sheet of

5 RF IN RF IN J N J0 N K inch #0 RE T T J SM +V T RF TP XVR F- R uh x 0T 0T # GRN T T # WHT T N-0 R TX +V J SM K T/R SWITH J SM K +V NT K J NT J NT V R K R0 0 N N R K R.K R K - + +V R K U LM MP IN 0. +V LPF OUT R K R 0 R.00 0 N.00 N R K R K R.K R.K T N-0 R R 0.K R0 0.K uh x 0T 0T # GRN T T # WHT V +V U LM. U LM +V FT N T INPUT J R JK R 0K - + U LM FT N T VOLTGE LEVELS 0M=0.V; 0M=0.V; 0M=.0V 0M=.V; 0M=.V; M=.0V M=.V; M=.V; 0M=.0V M=.V; M=.V; 0MHz=V last revised: 0// KOOR - HF PROJETS RF PTH Size ocument Number Rev <oc> 0 ate: Tuesday, October, 0 Sheet of

6 KOOR - HF PROJETS MPLIFIER MOULE FN last revised: 0// USER EFINE SPI PORT <oc> 0 ONTROLLER Tuesday, October, 0 Size ocument Number Rev ate: Sheet of MLR PG PG MLR PG PG L SK SO SHN G0 G SI SO SK SHN L SO SK SI F F F0 F F F F F F F F F0 G0 G G G G G SERIN SERLR SRK RK RK SRK SERLR SERIN SI FN SO SI SK SPIS0 SPIS SPIS SPIS0 SPIS SPIS RX TX TX RX NT XVR M M UHF TX PS R FREQ +V +V +V +V +V +V +V +V +V +V +V +V R.K J 0.uF 0.uF Q N0 Q N0 R 0K JP 0 0 R 0K H JF FILTER U 0 0 SER OUT RIN0 RIN RIN RIN RIN RIN RIN RIN RK SRK SERLR SERIN V N N G U LM0 IN OUT N00 H ISP.. 0.uF 0.uF U 0 0 SER OUT RIN0 RIN RIN RIN RIN RIN RIN RIN RK SRK SERLR SERIN V N N G U PIFK R/RX/T R/SO R R/TX R/RX V R0/INT0 R/INT R/INT R R R R/PG R/PG R0/N0 R/N R/N/VREF- R/N/VREF+ R/N/TOK R/N/LVIN RE0/N RE/N RE/N MLR/VPP/RE R0 V R R R/SK/SL R0/SK/SL R/SI/S R R R/SI/S R/SO R/TX/K R R R 0K R 0 R 0K

7 +V J SM RF TP R.0K V IN OUT IN OUT IN OUT LK V PR L U Q Q F LK V PR L U Q Q F IN IN IN U F OUT OUT OUT 0 FREQ R0 PTT JK Rear Panel J R JK H J +V PTT OPTIONS K.0 R 0 N Q N0 U0 N R M R last revised: 0// KOOR - HF PROJETS EXT INTERFE Size ocument Number Rev <oc> <Revode> ate: Tuesday, October, 0 Sheet of

8 US J R.K R 0K pf 0.0uF pf +V 0 V_IO V USM USP N RESET* OS OS0 VOUT TX RX RTS# TS# TR# SR# # R# US0 US US US US 0 R 00 R 00 R0 0 R 0 LE LE RX TX +V TX RX 0 0.uF U FTRL TEST US J R.K R 0K pf 0.0uF pf +V 0 V_IO V USM USP N RESET* OS OS0 VOUT TX RX RTS# TS# TR# SR# # R# US0 US US US US 0 R 00 R 00 R 0 R 0 RX TX +V LE LE TX RX 0.uF TEST U FTRL KOOR - HF PROJETS UL US IO Size ocument Number Rev USIO 0 ate: Tuesday, October, 0 Sheet of