P300. Technical Manual I/Os, 240 solenoid drivers th Street, Davis, CA 95616, USA Tel: Fax:

Transcription

1 00+ I/Os, 0 solenoid drivers Technical Manual 0 th Street, Davis, CA, USA Tel: Fax: sales@tern.com

2 COPYRIHT, i-engine, A-Engine, R-Engine and ACTF are trademarks of TERN, Inc. AmES and AmES are trademarks of Advanced Micro Devices, Inc. IntelEX and IntelSX are trademarks of Intel Corporation. Paradigm C/C++ is a trademark of Paradigm Systems. Microsoft, MS-DOS, Windows/000/NT/ME/XP are trademarks of Microsoft Corporation. Version.00 November, 00 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of TERN, Inc th Street, Davis, CA, USA Tel: Fax: sales@tern.com Important Notice TERN is developing complex, high technology integration systems. These systems are integrated with software and hardware that are not 00% defect free. TERN products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices, or systems, or in other critical applications. TERN and the Buyer agree that TERN will not be liable for incidental or consequential damages arising from the use of TERN products. It is the Buyer's responsibility to protect life and property against incidental failure. TERN reserves the right to make changes and improvements to its products without providing notice. Temperature readings for controllers are based on the results of limited sample tests; they are provided for design reference use only.

3 Chapter : Introduction Chapter : Introduction. Functional Description Measuring. x.0 x 0. inches, the offers a large I/O expansion to any TERN Engine board (A-Engine, A-Engine, i-engine and R-Engine). The versatility of the allows the use of 0 TTL-level I/O, high voltage input and solenoid driving output plus LCD and keypad support. The is the perfect expansion board for applications where high speed and low cost are a concern. The is designed for industrial control applications which require solenoid drivers and protected highvoltage inputs. There are 0 high-voltage I/O lines on the that can be configured as high voltage inputs or solenoid driving outputs. The inputs handle up to V DC. The outputs are capable of sinking 0 ma at 0V per line, and they can directly drive solenoids, relays, or lights. The high voltage chips may also be replaced with resistor pack ICs to provide digital TTL I/O to the user. A/D Bus TTL I/O (CA) TERN Host Microcontroller (AE, AE, ie, RE) A/D Bus chip select U Decoder (HC) S0-S U,U,U,U, U,U,U0 0 High Voltage I/O Expansion Controller S A/D Bus U Decoder (HC) A/D Bus S0-S S A/D Bus TTL I/O (CA) U, U, U TTL I/O (CA) U LCD and eypad Interface Figure. Functional block diagram of the -

4 Chapter : Introduction. Features Standard Features Dimensions:. x.0 x 0. inches Power input: +V to + V unregulated DC (up to +V with optional switching regulator ) On-board +V switching power supply On-board RS/ serial drivers I/O pins supporting digital, high voltage, LCD/keypad interfacing. Physical Description The physical layout of the is shown in Figure.. T T T SER0 SER J Power Jack U U U U U U U U0 U U U J T T T Figure. Physical layout of the The physical layout/description of the is shown above. Labels for pin headers are located nearest pin of the respective header (also applies to the J and J expansion sockets). T -

5 Chapter : Introduction Each CA PPI chip is label by location and a letter which corresponds to a specific I/O address found in the p00.h header file (of the TERN host controller directory). For example, if the A-Engine is being used as the host controller, see tern\\include\p00.h, and if using the i-engine, see tern\\include\p00.h. The table below will summarize the name of each CA PPI chip. Location U U U U U U U0 U U U U Name B E F H I L M N R To find the I/O address for the U PPI chip, for example, open the appropriate header based on the host controller. If using the A-Engine, open tern\\include\p00.h. Each PPI chip will have its own define statement based on its letter name. For U, look for the #define PPI 0xb0 statement.. Minimum Requirements for System Development.. Minimum Hardware Requirements PC or PC-compatible computer with serial COMx port that supports,00 baud TERN Engine controller (AE/AE/iE/RE). See appropriate technical manual. Debug serial cable (RS; DB connector for PC COM port and IDE x connector for controller) Center negative wall transformer (+V 00 ma).. Minimum Software Requirements TERN EV-P/DV-P it CD-ROM PC software environment: Windows//000/ME/NT/XP The C/C++ Evaluation it (EV-P) and C/C++ Development it (DV-P) are available from TERN. The EV-P it is a limited-functionality version of the DV-P it. With the EV-P it, the user can download and remote debug an application (STEP ), as well as perform standalone field tests with the application residing in the battery-backed SRAM of the host controller (STEP ). However, the DV-P it is required to generate application binary and HEX files for a final production version (STEP ). -

6 Chapter : Installation Chapter : Installation. Software Installation The technical manual for the host controller will provide details about the software installation for evaluation of TERN controllers.. Hardware Installation Hardware installation for the consists of installing the host controller onto the and connecting the to power and the PC for remote debugging. Overview Install the host controller onto the. Connect debug serial cable: For debugging (STEP ), place IDE connector on SER0 (J pin header on the ) with red edge of cable at pin. Connect wall transformer: Connect V wall transformer to power and plug into power jack.. Installing the host controller onto the Each host controller will install onto the in the same manner. All that is necessary is to align the J and J pin headers on the host controller with the J and J expansion sockets on the. See the diagram below for illustrated details... Connecting the to the PC The diagram below shows the link between the PC and the. It consists of connecting the debug serial cable to the PC and the SER0 pin header of the. It is important to note the red edge of the x IDE connector must align with PIN of the SER0 pin header. SER0 is located at J on the... Powering-on the & host controller The TERN EV-P and DV-P its include a +V DC power transformer. Plug the output of the transformer into the DC power jack on the. Refer to the following diagram. Upon power-up, the on-board LED of the host controller should blink twice and remain on to indicate ready for remote debugging. -

7 Chapter : Installation J (SER0) Red edge of cable aligns with pin. J. of A-Engine aligns with J. of Output of transformer plugs into DC power jack. J. of A-Engine aligns with J. of A-Engine installed onto the ; connected to PC via serial debug cable and output of transformer. -

8 Chapter : Hardware Chapter : Hardware. Engine controllers The must be driven by an Engine controller, such as the A-Engine, A-Engine, i-engine, or R-Engine. The Engine installs on top of the via the 0x pin headers J and J, and can be secured by two #-0 mounting screws. See Chapter for full installation details.. Serial Ports Drivers The can provide up to channels RS-/ drivers. Two RS- drivers are installed to interface the two asynchronous serial channels from the installed Engine controller via 0x pin header J and J. In addition, the Engine controller can support an additional UART. The can be configured to interface the additional UART with an RS- or RS- driver. The default debug serial port, SER0, is routed to J, SER is at J, and the SCC port is at J0. Part specifications for the serial port drivers can be found in the tern_docs\parts directory of the TERN installation CD (max.pdf and snlbc.pdf).. I/O Mapped Devices.. I/O Space External I/O devices use I/O mapping for access. You can access such I/O devices with inportb(port) or outportb(port,dat). These functions will transfer one byte of data to/from the specified I/O address. Each PPI (ca) device is identified by a letter. Each letter then corresponds to its matching I/O address, which can be found in p00.h of the host controller s directory. Chapter of this manual gives a table and diagram for identifying each PP... Programmable Peripheral Interface (CA) The PPI (C, or upd0l) is a low-power CMOS programmable parallel interface unit for use in microcomputer systems. They each provide TTL level I/O pins that may be individually programmed in two groups of and used in three major modes of operation. Eleven are installed on the for a total of I/Os. They are found in locations U, U, U, U, U, U, U0, U, U, U, and U. In MODE 0, two groups of pins can be programmed in sets of and pins to be inputs or outputs. In MODE, each of the two groups of pins can be programmed to have lines of input or output. Of the remaining pins, are used for handshaking and interrupt control signals. MODE is a strobed bi-directional bus configuration. -

9 Chapter : Hardware 0 R O U P P o r t ( L o w e r ) 0 O u t p u t I n p u t P o r t M o d e 0 0 O u t p u t I n p u t M o d e 0 M o d e R O U P P o r t ( U p p e r ) 0 O u t p u t I n p u t P o r t 0 M o d e X O u t p u t I n p u t M o d e 0 M o d e M o d e Figure. Mode Select Command Word C o m m a n d S e l e c t 0 B it m a n i p u la ti o n M o d e S e l e c t To program the PPI, determine the necessary command word based on chart above. This value must be written to the PPI s command register. For an example, consider the PPI at location U. The maps U, the PPIUB C/uP0, at base I/O address PPIUB = 0x??0. The?? address will vary based on host controller. Here, the registers will map as follows: Command Register = PPIUB+ Port 0 = PPIUB Port = PPIUB+ Port = PPIUB+ Two possible configurations will be shown. () Set all ports to output mode (Mode 0) outportb(ppiub+,0x0); The output pins can then be driven by writing to each port: outportb(ppiub+0,0x); outportb(ppiub+,0x); outportb(ppiub+,0x); () Set all ports to input mode: outportb(ppiub+,0xf); -

10 Chapter : Hardware The input ports can be read using one inport statement per port: inportb(ppiub+0); /* Port 0 */ inportb(ppiub+); /* Port */ inportb(ppiub+); /* Port */ This returns an -bit value for each port, with each bit corresponding to the appropriate line on the port. There are a total of x TTL level I/O pins, all free for applications use. These I/O lines are specified as ma driving current capability. The PPI at location U is located near the center of the. Its I/Os are routed directly to headers T and T. Each port is pulled-up via 0 resistor for easy implementation of an LCD/keypad interface. (Refer to sample code p00_kp.c) Refer to the schematics at the end of this manual (or tern_docs\schs) for additional pin location details. The data sheet for the CA can be found in the tern_docs\parts directory under ca.pdf.. High-Voltage, High-Current Drivers The has high voltage, high current Darlington transistor arrays, consisting of silicon NPN Darlington pairs on a common monolithic substrate. All channels feature open-collector outputs for sinking 0 ma at 0V, and integral protection diodes for driving inductive loads. Peak inrush currents of up to 00 ma sinking are allowed. These outputs may be paralleled to achieve high-load capability, although each driver has a maximum continuous collector current rating of 0 ma at 0V. The maximum power dissipation allowed is.0 W per chip at degree C. The common substrate,, is routed to. All currents sinking in must return to. A heavy gage (0) wire must be used to connect to an external common ground return. connects to the protection diodes in the chips and should be tied to highest voltage in the external load system. can be connected to an unregulated on board +V. is a sinking driver not sourcing driver. Typical application wiring is shown below. O Solenoid +V Power Supply /SUB +V /SUB Figure. Drive inductive load with high voltage/current drives. The uses devices, providing one high voltage channel per 0 TTL level I/O. By default all channels are high voltage output. Other possible configurations include replacing the s with IC resistor packs for TTL level I/O. See the data sheet, uln00a.pdf, found in the tern_docs\parts directory on the TERN installation CD for additional details. -

11 Error! Reference source not found.board Modification Appendix A: Board Modification modifications to support VE, AE, AE, RE, E, E was designed for V-Engine in. J header signals NOT compatible to all Engines are J.=, J.=/WR, J.=/CTS. H provides selection for I/O select line /SIO: H.=J., H.=/SIO, H.=J. Modification needs to cut pins on J., J., no connection between and Engine controller. For RE: ) Add wire connect J.=J. to use P=/PCS ) Jumper on H.=H.=J.=J. to use P=/PCS ) Cut pins on J., J., no connection between and RE J pin = /WR must be cut off the pin on Engine or cut off the trace on PCB.

12 D 0 U C D 0 U C D 0 U C D 0 U D 0 U /WR 0 B0 B0 B0 B0 B0 B0 B0 B00 R D D D D N D D D D V /WR S 0 C P B D P P B P0 P B PPI P0 P B PPIS B P P B P0 P0 0 B P B0 / P P P P P C N A A N P B P B S D 0 C 0 /WR 0 E0 E0 E0 E0 E0 E0 E0 E00 R D D D D N D D D D V /WR S 0 C P E D P P E P0 P E PPI P0 P E PPIS E P P E P0 P0 0 E P E0 / P P P P P C N A A N P E P E S D 0 C 0 /WR 0 F0 F0 F0 F0 F0 F0 F0 F00 R D D D D N D D D D V /WR S 0 C P F /WR 0 D P P F 0 P0 P F 0 PPI P0 P F 0 PPIS F 0 P P F 0 P0 P0 0 F 0 P F0 0 / P P P P F 00 P P P F C N A A N S D 0 C 0 R D D D D N D D D D V /WR S 0 C P D P P P0 PPI P P0 PPIS P P P P0 P0 0 P / P P P P P P C N A A N P S D 0 C 0 0 /WR 0 H0 H0 H0 H0 H0 H0 H0 H00 R D D D D N D D D D V /WR S 0 C P D P P P0 PPI P P0 PPIS P P P P0 P0 0 P / P P P P P P C N A A N P S D 0 C 0 H H H H H H H H0 H H 0 S0 B B0 A B A0 B B B 0 S E E0 A E A0 E E E 0 S F F0 A F A0 F F F 0 S 0 A A0 0 S H H0 A H A0 H H H U B B B B B B B B B B B B0 C C C C C C C 0 U F B F B F B F B F B F F0 C C C C C C C 0 V V V V V V V AE /PCS /CTS /SIO IE /CS P U RXD RO MPO /RE DE TXD DI VLC / C U B B B B B B B B B B B B0 C C C C C C C 0 U V0 F B V F B V F B V F B V F B V F V F0 B A C C C C C C C 0 H A A A B A C /TXD /RXD A /SIO A B LTC U R A A /RXD A B P 0 /RXD R C /TXD /TXD R 0 0 S A HDRS B LM O U V F V O / I U N F O N T D B N D I N RCH0 / +V R M J +V VOFF LX HDR C /TX 0 uh /RX V V V0 V V V V B0 B0 B0 B0 B0 B0 B00 U0 U V V E V B0 B C U B V E B B C B B C B C B B C B C V B B C B B C B C B C V E V E0 V E V E B C 0 C V E V0 E C V E V H0 C 0 V E0 C C C C C C C 0 U V F0 B C U V V F0 V F0 F B C B C U B C B C B C V B V B B C C B V F0 V F B C V B V0 F0 V 0 C B C V B V F0 V C 0 C V B V F0 V C 0 V V F00 V0 H V 0 U HC Y0 Y Y Y Y Y 0 Y Y Y0 Y Y Y Y Y 0 Y Y HC PB PB00 J 0 J S0 S S S S S S S S0 S S S C C BP C C C C C C C 0 V E V0 E V E V E V E V E V E0 U B B B B B C C C C C C C 0 U V B V V0 B V B V B B V V 0 C C C C C C C 0 V T V V T V V T V V V V V V V V V V V V V V V V V V V V 0 V0 V 0 V0 V 0 V0 V V V V V V V V V V V V V V V V V V V V V V V V V 0 V0 V 0 V0 V 0 V00 V V V V V0 V0 V V V V V0 V0 V V V V V0 V0 V V V V V0 V0 V 0 V0 V 0 V0 V0 0 V0 V V V V V V V V V V V V V V V V V V V V V V V V V 0 V0 V 0 V0 V 0 V0 HDR0 P BEEP BT +VI +V C DJ-00 N J /TXD /RXD 0 /TXD /RXD J0 0 HDR0 HDR0. D D /TXD V0 V0 /RXD H S H S /RT S S S0 S0 S S +VI S S A0 S S A0 A A / / /SIO /WR /SIO /WR H T T V V V V V0 V V V V V V V V0 V E0 E0 E0 E0 E0 E0 E C+ V+ C- C+ C- V- /TX /RX C+ C U 0 J C+ P V+ P /CTS0 P C- TO RXD /TXD C+ RI TX /INT TXD /RXD C- RO RX /RTS VOFF 0 D RXD P P V- TI 0 TXD TXD /RTS0 TO TI 0 TX RXD / RI RO RX P P /CTS /INT P 0 MPO MAXA P0 0 /INT MPI P P V+ /WR P A C C P P A P0 P /WR 0 A V- 0 A /INT0 /NMI A /INT P A C P P DCD 0 A A0 HDR0 J HDR0 C- C+ C0 C- /RT U B V C B V C B C B C V B C V C V C 0 V V U0 B C V V B C B C V B C V B C V C C 0 V V U H H B B H B H H B H B H0 Title C C C C C C C 0 U H0 B H0 H0 B H0 B H0 B B H0 H00 C C C C C C C 0 V V00 H H V0 H V0 H V0 H V0 H V0 H0 V V V V V V V MASS I/O EXPANSION Size Document Number B.SCH U B C V0 B C V0 B C B C V0 V0 B C V0 C V C 0 V J HDR / REV Date: November, Sheet of

13 D 0 U D 0 U0 D 0 U D 0 U D 0 U /WR 0 R D D D D N D D D D V I /WR 0 R D D D D N D D D D V /WR 0 R D D D D N D D D D V 0 R D D D D N D D D D V M /WR 0 R D D D D N D D D D V /WR S 0 C /WR S 0 C /WR S 0 C L /WR /WR S 0 C /WR S 0 C N P P P P P I0 D P D P D P D P D P P I 0 P L0 P L M0 P M N0 P N I0 P0 PPI P0 PPI P0 PPI P0 PPI P0 P I 0 P L0 P L M0 P M N0 P N I0 PPI P0 PPIS P0 PPIS P0 PPIS P0 PPIS P0 P I 0 P L0 P L M0 P M N0 P N I0 PPIS I 0 L0 L M0 M N0 N I0 P P P P P P I 0 P L0 P L M0 P M N0 P N I0 P0 P0 0 I 0 P0 P0 0 L0 P0 P0 0 L M0 P0 P0 0 M N0 P0 P0 0 N I0 I0 0 0 L0 L0 M0 M0 N0 N0 I00 P P P / P P P P P P / P P P P P P / P P P P P P / P P P P P P P / P I 00 L00 L M00 M N00 N P P P P P P P I C N A A N P C N A A N P L C N A A N P M C N A A N P N C N A A N C S D 0 C 0 S D 0 C 0 S D 0 C 0 S D 0 C 0 S D 0 C 0 C S I S S0 L S M S N C I0 0 L0 M0 N0 A I A A L A M U A N A0 I A0 A0 L A0 M V A0 N I I L L M M B C V N N B C V U U U U U U B C B C V U I0 V I V I V I0 V 0 V V V N0 V I0 B C V I B C V I B C V0 I B C V 0 B C V B C V B C V N0 B C V I0 B C V I B C V I B C V I B C V 0 B C V B C V0 0 C V N0 B C V B C B C B C B C B C B C C 0 B C I0 B B B B C B C B C C C C B C B B B B B C C C C C B C B C V I V I V 0 V 0 V V N0 V I0 C V I C V0 I C V C V 0 C V C V N0 C V I0 C 0 V I C 0 V I C 0 V C 0 V 0 C 0 V0 C 0 V N0 C 0 V0 I00 V I0 V I0 V N0 V 00 V 0 V N00 V U M V M B C B C V M V U0 L0 B V L L0 C U B C B V L V L C U L0 V L B C B C V0 L0 V L B C U L B C B V B C C B C V M0 V L B C U L B C C B V B C C B C V0 M V M0 B C U M B C 0 C C B V M0 B C C B C V M V0 M B C B C V M B C 0 C C B V0 B C C B C B C V V0 M B C U M0 B C 0 C C V0 B C B C C N V V V B C 0 C C B C C 0 N B C B C V N V0 B C L0 V L V0 L V M0 V M0 V0 M V0 N C 0 C B C V L0 V L V L V M V M0 V00 M V0 N B C V L0 V L V L V M V M0 V M V0 N C 0 C V L00 V0 L0 V L0 V N V M00 V M0 V0 N0 C 0 V U0 N V T N B C B V C R0 R0 T T T N B V C R0 R0 V V V V V0 V0 N B V U C V0 N V H V0 B N B C C V0 D R0 V V V V V0 / / R0 R0 V V V V V0 N V V0 R00 C B C R 0 R V V V V V0 V0 N0 0 0 C 0 V B C A0 A0 R R V 0 V0 V V0 V0 V0 B C A A V V V V V V 0 U B C R R V V V V V V C HDR V V V V V V /WR C 0 /WR V V V V V V /WR S S R T 0 R D D D D N D D D D V V 0 V0 V 0 V0 V 0 V0 R0 /WR S 0 C D P R RN 0 S S R V D V V V V V R0 P RN 0 R P R0 R R S0 S0 R V V V V V V R0 S S R V V V V V V R0 S S S S R P0 P R0 R PPI R V V V V V V P0 P R0 R PPIS R R0 V 0 V0 V 0 V0 V 0 V0 R0 R0 R RN 0 P R0 R N R P R0 R N H H R V V V V V V R0 P0 P0 0 R 0 P HDRS / P P P P P P C N A A N P 0 R0 0 R N V V V V V V R0 N V0 V0 R R0 R00 R0 V V V V V V R00 N0 /SIO /SIO R R R V V V V V V N R0 R V V0 V V00 V V0 N D D S D 0 C 0 RN0 0 HDR0 HDR0 HDR0 RN 0 RN 0 RN 0 M0 M 0 M0 M RN 0 R S R R M0 M M R0 R M0 M M A R R M0 M M 0 A0 R R0 M0 M M R RN RN 0 RN 0 RN 0 RN 0 RN 0 R R M0 M M0 R M00 M0 M RN 0 RN 0 / M M /SIO I 0 L0 L N0 N I0 RN 0 I 0 L0 L N0 N RN 0 STE/TERN I0 I I 0 L0 L N0 N L I0 I I 0 L0 L N0 N L Title I0 I I 0 L0 L N0 N L. PPIs I0 I I 0 L0 L N0 N L Size Document Number REV 0 I0 I0 I I0 I I0 I00 I 0 I 0 0 L L00 0 L N0 L0 L 0 N00 0 N L0 N0 L N L B. Date: November, Sheet of

14 VB0 V V V V V T 0 V V V V V0 VA V V V V VB V V V V V 0 V0 V V V V VA V V V V VB V 0 V0 V V V V V V V V VA V 0 V0 HDR0 VA0 VB VA VB VA VB V T V VB V V V V V V V 0 V0 V V VA V V V V VB V V V 0 V0 V V V V V V VA V V V 0 V0 VB0 V V V V V V V V V 0 V0 HDR0 VA VB VA VB VA0 VB VA V T V V V VB V V V V V 0 V0 V V V V VA V V V V VB V 0 V00 V0 V0 V0 V0 V0 V0 VA V0 V0 V0 0 V0 V V VB V V V V V V V 0 V0 HDR0 VA VB VA VB VA VB V0 V0 V0 V0 V0 V V V V V V V V V V V V V V V T HDR0 V0 V0 V0 V0 V0 V V V V V0 V V V V V0 V V V V V0 VA B B B U B C B C B C B C B C C C 0 V V V V VB0 VA0 B B B U B C B C B C B C B C C C 0 V VB V V0 V VA B0 B0 B0 U0 B B B B B C C C C C C C 0 V V V V VB VA B0 B B U B B B B B C C C C C C C 0 V V V V VB VA E E E U B C B C B C B C B C C C 0 V VB V0 V V VA E E E U B C B C B C B C B C C C 0 V VB V V V VA E0 E0 E0 U B C B C V VB B C V B C V V B C VA C C 0 F F F U B C B C B C B C B C C C 0 V0 V V V VB VA F F F F F F F0 U B B B B B C C C C C C C 0 V V V V0 V V V VB VA F0 F0 F0 U B B B B B C C C C C C C 0 V V V V V V V0 VB VA F0 F F U B C B C B C B C B C C C 0 V V V V VB0 VA0 U B C B C B C B C B C C C 0 V V V0 V VB VA U B C V VB B C V B C V B C V VA B C C C U0 B C B C B C B C B C C C 0 V VB V V V VA H H H U B B B B B C C C C C C C 0 V V00 V0 V0 VB VA H H H U B B B B B C C C C C C C 0 V0 V0 V0 V0 VB VA H0 H0 H0 U B C B C B C B C B C C C 0 V V V V VB VA N N N U0 B C B C B C B C B C C C 0 V V V V VB VA /CTS /SIO P H.=H. H MODIFY E J.=J. 0 P /CTS0 TX RX P 0 TXD RXD P /CTS P0 0 P /WR P P0 0 /INT0 /INT P HDR0 P P /INT /RTS P /RTS0 CUT J. P /INT /INT P P P P /NMI P P DCD J MODIFICATION ON TO SUPPORT DACs (LTC): INSTALL LTC IN SOCETS REPLACIN A CUT LTC PIN ADD TO DAC PIN ADD TO DAC PIN FOR -ENINE, CUT J.. Title MODIFICATION FOR MASS ANALO OUTPUTS Size Document Number B _DA.SCH REV Date: September, 00 Sheet of