MM54C14 MM74C14 Hex Schmitt Trigger
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1 MM54C14 MM74C14 Hex Schmitt Trigger General Description The MM54C14 MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors The positive and negative going threshold voltages V Ta and V Tb show low variation with respect to temperature (typ V C at V CC e 10V) and hysteresis V Ta b V Tb t 0 2 V CC is guaranteed All inputs are protected from damage due to static discharge by diode clamps to V CC and GND Connection Diagram Features Dual-In-Line Package February 1988 Y Wide supply voltage range 3 0V to 15V Y High noise immunity 0 70 VCC (typ ) Y Low power 0 4 VCC (typ ) TTL compatibility 0 2 V CC guaranteed Y Hysteresis 0 4 VCC (typ ) 0 2 V CC guaranteed MM54C14 MM74C14 Hex Schmitt Trigger Top View Order Number MM54C14 or MM74C14 TL F C1995 National Semiconductor Corporation TL F 5879 RRD-B30M105 Printed in U S A
2 Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin b0 3V to V CC a 0 3V Operating Temperature Range MM54C14 b55 Ctoa125 C MM74C14 b40 Ctoa85 C Storage Temperature Range Power Dissipation Dual-In-Line Small Outline Operating V CC Range Absolute Maximum V CC Lead Temperature (Soldering 10 seconds) DC Electrical Characteristics Min Max limits apply across the guaranteed temperature range unless otherwise noted b65 Ctoa150 C 700 mw 500 mw 3 0V to 15V 18V Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS V Ta Positive Going Threshold Voltage V CC e 5V V V CC e 10V V V CC e 15V V V Tb Negative Going Threshold Voltage V CC e 5V V V CC e 10V V V CC e 15V V V Ta V Tb Hysteresis V CC e 5V V V CC e 10V V V CC e 15V V V OUT(1) Logical 1 Output Voltage V CC e 5V I O eb10 ma 4 5 V 260 C V CC e 10V I O eb10 ma 9 0 V V OUT(0) Logical 0 Output Voltage V CC e 5V I O e 10 ma 0 5 V V CC e 10V I O e 10 ma 1 0 V I IN(1) Logical 1 Input Current V CC e 15V V IN e 15V ma I IN(0) Logical 0 Input Current V CC e 15V V IN e 0V b1 0 b0 005 ma I CC Supply Current V CC e 15V V IN e 0V 15V ma CMOS LPTTL INTERFACE V CC e 5V V IN e 2 5V (Note 4) 20 ma V CC e 10V V IN e 5V (Note 4) 200 ma V CC e 15V V IN e 7 5V (Note 4) 600 ma V IN(1) Logical 1 Input Voltage V CC e 5V 4 3 V V IN(0) Logical 0 Input Voltage V CC e 5V 0 7 V V OUT(1) Logical 1 Output Voltage 54C V CC e 4 5V I O eb360 ma 2 4 V 74C V CC e 4 75V I O eb360 ma 2 4 V V OUT(0) Logical 0 Output Voltage 54C V CC e 4 5V I O e 360 ma 0 4 V 74C V CC e 4 75V I O e 360 ma 0 4 V OUTPUT DRIVE (see 54C 74C Family Characteristics Data Sheet) T A e 25 C (Short Circuit Current) I SOURCE Output Source Current V CC e 5V V OUT e 0V (P-Channel) I SOURCE Output Source Current V CC e 10V V OUT e 0V (P-Channel) b1 75 b3 3 ma b8 0 b15 ma I SINK Output Sink Current V CC e 5V V OUT e V CC ma (N-Channel) I SINK Output Sink Current V CC e 10V V OUT e V CC ma (N-Channel) 2
3 AC Electrical Characteristics T A e 25 C C L e 50 pf unless otherwise specified Symbol Parameter Conditions Min Typ Max Units t PD0 t PD1 Propagation Delay from Input V CC e 5V ns to Output V CC e 10V ns C IN Input Capacitance Any Input (Note 2) 5 0 pf C PD Power Dissipation Capacitance (Note 3) Per Gate 20 pf AC Parameters are guaranteed by DC correlated testing Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits The table of Electrical Characteristics provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 C PD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90 Note 4 Only one of the six inputs is at V CC the others are either at V CC or GND Typical Applications Low Power Oscillator t 1 RC fin V Ta V Tb t 1 RC fin V CC b V Tb V CC b V Ta 1 f RC fin V 1 Ta (V CC b V Tb) 1 7 RC V Tb (V CC b V Ta) Note The equations assume t 1 a t 2 n t pd0 a t pd1 TL F TL F
4 Typical Performance Characteristics Typical Transfer Characteristics Guaranteed Trip Point Range TL F TL F Note For more information on output drive characteristics power dissipation and propagation delays see AN-90 TL F
5 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C14J or MM74C14J NS Package Number J14A 5
6 MM54C14 MM74C14 Hex Schmitt Trigger Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C14N or MM74C14N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 nsc com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
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CD4025 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
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