Features MIC4468 V S GND. Micrel, Inc Fortune Drive San Jose, CA USA tel + 1 (408) fax + 1 (408)
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1 MIC// Quad.-Peak Low-Side MOSFET Driver Bipolar/CMOS/DMOS General Description The MIC// family of -output CMOS buffer/drivers is an expansion from the earlier single- and dual-output drivers, to which they are functionally closely related. Because package pin count permitted it, each driver has been equipped with a -input logic gate for added flexibility. Placing four high-power drivers in a single package also improves system reliability and reduces total system cost. In some applications, one of these drivers can replace not only two packages of singleinput drivers, but some of the associated logic as well. Although primarily intended for driving power MOSFETs, and similar highly capacitive loads, these drivers are equally well suited to driving any other load (capacitive, resistive, or inductive), which requires a high-efficiency, low-impedance driver capable of high peak currents, rail-to-rail voltage swings, and fast switching times. For example, heavily loaded clock lines, coaxial cables, and piezoelectric transducers can all be driven easily with MICX series drivers. The only limitation Features Built using reliable, low power CMOS processes Latchproof. Withstands ma Inductive Kickback Input Logic Choices Symmetrical Rise and Fall Times...ns Short, Equal Delay Times...ns High Peak Output Current.... Wide Operating Range.... to V Low Equivalent Input Capacitance (typ)... pf Inputs = Logic for Any Input From.V to ESD Protected Applications General-Purpose CMOS Logic Buffer Driving All MOSFETs in an H-Bridge Direct Small-Motor Driver Relay or Peripheral Drivers Dual Differential Output Power Drivers CCD Driver Pin-Switching Network Driver Logic Diagrams MIC MIC MIC A B Y A B Y A B Y Y Y Y Fortune Drive San Jose, CA USA tel + () - fax + () - July MIC//
2 on loading is that total power dissipation in the IC must be kept within the power dissipation limits of the package. The MICX series drivers are built using a BCD process. They will not latch under any conditions within their power and voltage ratings. They are not subject to damage when up to V of noise spiking (either polarity) occurs on the ground line. They can accept up to half an amp of inductive kickback current (either polarity) into their outputs without damage or logic upset. Ordering Information Part Number Temperature Standard Pb-Free Range Package MICxxCN* MICxxZN* C to + C -pin Plastic DIP MICxxCWM* MICxxZWM* C to + C -pin Wide SOIC MICxxBN* MICxxYN* C to + C -pin Plastic DIP MICxxBWM* MICxxYWM* C to + C -pin Wide SOIC * xx identifies input logic: NAND AND AND with inverting input **Pb-Free industrial grade PDIP available in MIC & MIC only. Truth Table Inputs Output Part No. A B Y MIC L X H (Each Driver) X L H H H L MIC H H H (Each Driver) L X L X L L MIC L X L (Each Driver) X H L H L H Pin Configurations -Pin DIP (N) -Pin Wide SOIC (WM) A B V S Y Y A B V S Y Y TOP VIEW TOP VIEW MIC// July
3 Block Diagrams MIC IN A IN B V Regulator Level Shifter Y OUT Functional Diagram for One Driver (Four Drivers per Package Ground Unused Inputs) MIC IN A IN B V Regulator Level Shifter Y OUT Functional Diagram for One Driver (Four Drivers per Package Ground Unused Inputs) MIC IN A IN B V Regulator Level Shifter Y OUT Functional Diagram for One Driver (Four Drivers per Package Ground Unused Inputs) July MIC//
4 Absolute Maximum Ratings (Notes and ) Supply Voltage V Input Voltage ( V) to ( +.V) Maximum Chip Temperature Operating C Storage to + C Maximum Load Temperature ( sec, for soldering) C Operating Ambient Temperature C Version to + C B Version to + C Power Dissipation N Package (-Pin Plastic DIP).W WM Package (-Pin Wide SOIC) W Package Thermal Resistance N Package (-Pin Plastic DIP) θ JA WM Package (-Pin Wide SOIC) θ JA C/W C/W Electrical Characteristics: Measured at T A = C with.v V unless otherwise specified. (Note ) Symbol Parameter Conditions Min Typ Max Units INPUT V IH Logic Input Voltage.. V V IL Logic Input Voltage.. V I IN Input Current V IN µa OUTPUT V OH High Output Voltage I LOAD = ma -. V V OL Low Output Voltage I LOAD = ma. V R O Output Resistance I OUT = ma, = V Ω I PK Peak Output Current. A I Latch-Up Protection > ma Withstand Reverse Current SWITCHING TIME t R Rise Time Test Figure ns t F Fall Time Test Figure ns t D Delay Time Test Figure ns t D Delay Time Test Figure ns POWER SUPPLY I S Power Supply Current. ma Supply Note. Specification for packaged product only. MIC// July
5 Electrical Characteristics: Measured over operating temperature range with.v V unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units INPUT V IH Logic Input Voltage.. V V IL Logic Input Voltage.. V I IN Input Current V IN µa OUTPUT V OH High Output Voltage I LOAD = ma -. V V OL Low Output Voltage I LOAD = ma. V R O Output Resistance I OUT = ma, = V Ω I PK Peak Output Current. A I Latch-Up Protection ma Withstand Reverse Current SWITCHING TIME t R Rise Time Test Figure ns t F Fall Time Test Figure ns t D Delay Time Test Figure ns t D Delay Time Test Figure ns POWER SUPPLY I S Power Supply Current. ma Supply NOTE : Functional operation above the absolute maximum stress ratings is not implied. NOTE : Static sensitive device. Store only in conductive containers. Handling personnel and equipment should be grounded to prevent static damage. July MIC//
6 Typical Characteristics Rise and Fall Time vs. Supply Voltage C L = pf T A = C Delay Time vs. Supply Voltage C L = pf T A = C Rise and Fall Time vs. Temperature C = pf L = V T R T D T D T R T F T F SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE ( C) Delay Time vs. Temperature C L = pf = V T D T D TEMPERATURE ( C) SUPPLY CURRENT (ma) Supply Current vs. Capacitive Load T A = C = V khz khz khz CAPACITIVE LOAD (pf) k Rise and Fall Time vs. Capacitive Load T A = C = V T R T F CAPACITIVE LOAD (pf) SUPPLY CURRENT (ma) Supply Current vs. Frequency High Output vs. Current Low Output vs. Current.. T A = C = V T = C V A C = V T A = C = V C L = pf.. V V V V (V) S OUT... V V OUTPUT VOL AGE (V)... V V FREQUENCY (khz). CURRENT SOURCED (ma). CURRENT SUNK (ma) MIC// July
7 . Quiescent Power Supply Current vs. Supply Voltage Quiescent Power Supply Current vs. Supply Voltage SUPPLY CURRENT (ma).... NO LOAD BOTH INPUTS LOGIC "" T = C A SUPPLY CURRENT (µa) NO LOAD BOTH INPUTS LOGIC "" T = C A SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Test Figure VS INVERTING INPU T +V % µf FILM. µf CERAMIC IN V OUT IN pf IN IN IN IN IN IN V INPUT % t D t D V OUTPUT t F t R V V % NON-INVE RTING INPU T +V VINPUT % V V OUTPUT V % % % % % t D td t R % % % t F Package Power Dissipation -PIN PDIP SLOPE = mw/ C Quad Driver Drives H Bridge to Control Motor Speed and Direction +V TO +V MIC P D (mw) CW CCW DC BRUSH MOTOR -PIN WIDE SOIC SLOPE = mw/ C PWM SPEED AMBIENT TEMPERATURE ( C) July MIC//
8 Package Information. (.) MAX PIN. (.). (.) (.). (.). (.). (.). (.). (.). (.). (.). (.). (.) -Pin Plastic DIP (N) PIN. (.) INCHES (MM). (.). (.) TYP. (.) TYP. (.) TYP (.) R PLANE MIN. (.). (.). (.) TYP. (.). (.) TYP TYP. (.) -Pin Wide SOP (WM) MICREL INC. FORTUNE DRIVE SAN JOSE, CA USA TEL + () - FAX + () - WEB This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. MIC// July
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Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. CD4020BC CD4040BC CD4060BC 14-Stage Ripple Carry Binary Counters 12-Stage
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TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates,
MM74HC161 MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear
September 1983 Revised February 1999 MM74HC161 MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear General Description The MM74HC161 and MM74HC163
54AC32 Quad 2-Input OR Gate
54AC32 Quad 2-Input OR Gate General Description The AC/ ACT32 contains four, 2-input OR gates. Features n I CC reduced by 50% on 54AC/74AC only Logic Symbol IEEE/IEC n Outputs source/sink 24 ma n ACT32
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 2005 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
TC74LCX08F,TC74LCX08FN,TC74LCX08FT,TC74LCX08FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LCX08F/FN/FT/FK TC74LCX08F,TC74LCX08FN,TC74LCX08FT,TC74LCX08FK Low-Voltage Quad 2-Input AND Gate with 5-V Tolerant Inputs and Outputs The
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
Features. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics
CD4001BM CD4001BC Quad 2-Input NOR Buffered B Series Gate CD4011BM CD4011BC Quad 2-Input NAND Buffered B Series Gate General Description These quad gates are monolithic complementary MOS (CMOS) integrated
MM54HC154 MM74HC154 4-to-16 Line Decoder
MM54HC154 MM74HC154 4-to-16 Line Decoder General Description This decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications It possesses
Features. Y Wide supply voltage range 3 0V to 15V. Y Guaranteed noise margin 1 0V. Y High noise immunity 0 45 VCC (typ )
MM70C95 MM80C95 MM70C97 MM80C97 TRI-STATE Hex Buffers MM70C96 MM80C96 MM70C98 MM80C98 TRI-STATE Hex Inverters General Description These gates are monolithic complementary MOS (CMOS) integrated circuits
Low Power Quint Exclusive OR/NOR Gate
100307 Low Power Quint Exclusive OR/NOR Gate General Description The 100307 is monolithic quint exclusive-or/nor gate. The Function output is the wire-or of all five exclusive-or outputs. All inputs have
MM54HC244 MM74HC244 Octal TRI-STATE Buffer
MM54HC244 MM74HC244 Octal TRI-STATE Buffer General Description These TRI-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed noninverting buffers They possess
Excellent Integrated System Limited
Excellent Integrated System Limited Stocking Distributor Click to view price, real time Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor CD4050BCN For any questio, you can email us
MM54HC373 MM74HC373 TRI-STATE Octal D-Type Latch
MM54HC373 MM74HC373 TRI-STATE Octal D-Type Latch General Description These high speed octal D-type latches utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power
CD4093BC Quad 2-Input NAND Schmitt Trigger
CD4093BC Quad 2-Input NAND Schmitt Trigger General Description The CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a 2-input NAND gate with Schmitttrigger action on both inputs.
MM54HC173 MM74HC173 TRI-STATE Quad D Flip-Flop
MM54HC173 MM74HC173 TRI-STATE Quad D Flip-Flop General Description The MM54HC173 MM74HC173 is a high speed TRI-STATE QUAD D TYPE FLIP-FLOP that utilizes advanced silicongate CMOS technology It possesses
74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance