Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz
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- Ambrose Gordon Lynch
- 5 years ago
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1 V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion onnector x LEs x Pushbuttons GPIO URT TSX00 ortexm0 //Opamps Input Jack Potentiometer udio mp 0Way oresight SW onnector SW SPI SYSLK XTL Reset Output Jack S ard Slot Touch Screen QVG isplay (MQVGTSisplay) Oscillator MHz rystal.mhz Reset utton MTSX00 lock iagram ate: Number: HI0 Revision: 0 0/0/0 Time: :: Sheet of lock_iagram.schoc
2 OS_EN JP V R K U EN GN MHz OS EN HEER X V OUT R 00n V R 00K 0p R K X.MHz R M 0p V_ 00n V V V V J HEER X Prototyping power headers J HEER X J HEER X V_ PIN_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ SWLK PIN_ OS_EN INT PIN_ PIN_ SLK SS SS PIN_ PIN_ J0 0 0 HEER X J 0 0 PIN_ PIN_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ SWIO PIN_ TEST PIN_0 PIN_ PIN_ SS TS PIN_ PIN_ V_ 00n V_ PIN_ PIN_ PIN_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ SWLK SWIO PIN_ PIN_ 0 0 V GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ SWLK SWIO VSS PIN_ LK_IN SYSLK INT XOUT XIN OUT IN IN IN IN OUT VREF IN0 IN0 IN IN IN IN IN IN V OUT OUT OUT OUT OUT OUT OUT0 OUT0 VSS VSS TOUT THLT TLK PEN POUT V VSS LK_IN SYSLK INT XOUT XIN V OUT IN IN IN IN OUT VREF IN0 IN0 IN IN IN IN IN IN VSS V TEST0 TEST INT SLK SS SS SS TS VSS 0 0 U TSX00 OUT OUT OUT OUT OUT OUT OUT0 OUT0 PIN_ PIN_ PIN_ PIN_ PIN_0 PIN_ PIN_ TOUT THLT TLK PEN POUT V_ V_ 00n 00n IN IN OUT IN0 IN IN IN LK_IN INT XIN OUT IN IN VREF IN0 IN IN IN PIN_0 PIN_ TOUT TLK POUT J 0 0 J 0 0 HEER X PIN_ SYSLK XOUT OUT OUT OUT OUT0 PIN_ PIN_ OUT OUT OUT OUT0 PIN_ PIN_ PIN_ THLT PEN V_ V_ V_ HEER X V_ HEER X V 00n J 0 MIPI 0 ortex debug connector (oresight interface) 0K R 0K R 0K R V 0K R R SWIO SWLK TP TP 00n V V R R0 OS_EN TEST INT PIN_0 PIN_ PIN_ PIN_ PIN_ SLK SS SS SS TS PIN_ PIN_ PIN_ PIN_ V_ V_ These links can be replaced with low value resistors for current measurement puposes. TP TP SS SS SS SLK R R R R R R R V 0K 0K 0K 0K 0K 0K 0K V GPIO_ GPIO_ SLK 0 0 J HEER X EXP TS GPIO_0 INT MU ate: 0/0/0 MU.Schoc Number: HI0 Revision: 0 Time: :: Sheet of
3 US, Power & Serial HI0 0 0/0/0 US_Power_Serial.Schoc Number: ate: Revision: Sheet of Time: :: STE V V TOUT RIN ROUT TIN 0 TIN ROUT RIN TOUT GN V U LS J VOUT U LS J VOUT U US VUS GN SHIEL SHIEL J V E SOKET 0 J OM T0 T0 00n 00n 00n 00n V TS WY J V V 0u 0u 0u 0u 0 u L R V 00n 0 0n 0 M R FTRQ 0 TR VIO RI GN N SR TS US US 0 US USP USM VOUT GN V GN 0 US US0 N GN TEST OSI OSO N N N N GN P U US_N US_P V 00n 00n 00n TS _US _US TS_US _US _US _US TS_US _US TS USLS IO GN IO IO VUS IO U US_N US_P V V VUS 00n HEER X JP HEER X JP HEER X JP HEER X JP Serial port selection jumpers. RS interface US interface Expansion interface VUS 0K R 0K R 0K R0 0K R V US US USSHL V R R R V_REG V_REG V K R K R 0 R K R K R K R 0 R K R
4 JP,,, placed together to allow loopback connections from OUT/ to IN0/ JP JP JP JP TP JP0 HEER X 00n R 0K R0 K VOLUME Fully clockwise = MX Fully anticlockwise = MIN U GIN IN IN GN LM GIN YP VS VOUT 00n V 00n R n 00u JP HEER X J JK SOKET SP N N Speaker JP To select MI jack V JP JP JP JP JP JP JP JP JP To select POT NOTE: For IFF input, remove shunts and attach cable to: JP. (IFF) JP. (IFF) JP. (GN) To select LN IFF JP To select JK input OUT R NOTE: For IFF input, remove JP/ shunts and attach cable to: JP. (IFF) JP. (IFF) JP. (GN) JP n 0K V IN IN 00n R 0K 00n R R0 n Fully clockwise =.V Fully anticlockwise = 0V R K/0K 0K 0K JP HEER X JP HEER X JP HEER X 00n R0 n n R OUT OUT R MI_VREF MI_VREF IN R R R IN R R R JP HEER X JP HEER X OUT0 OUT0 VREF REF J JK SOKET 00n JP R K HEER X 00n JP HEER L JK_YPSS 0 00n 00n R 00K R 00K 00n IN IN IN MI_VREF IN OUT OUT R 00K R K R 00K R0 00K MI_VREF JK_YPSS JP HEER T R K R K JP HEER T IN IN R R n K OUT OUT K n JP IN0 HEER X JP IN0 HEER X nalog ate: Number: HI0 Revision: 0 0/0/0 Time: :: nalog.schoc Sheet of
5 Misc HI0 0 0/0/0 Misc.Schoc Number: ate: Revision: Sheet of Time: :: MQVGTSISPLY N T_INT S RS SK R P P P 0 P P P P P P0 P P P P 0 P P P L_GN L_ENLE V V GN GN L_V 0 SO SI T_S SK J S P S P S P S P P 0 P P P MIRO S S V SLK GN SW 0 J R 00n V R 00n R 00n R 00n GPIO_ GPIO_ GPIO_ GPIO_ 00K R 00K R 00K R 00K R V SS SLK SLK SS V 00n R R R R GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ P P0 P P R R R0 R 0K R V V 00n STM00 VSS RST V U S 0K R 0n 0 0 R0 V GPIO_ GPIO_ 0K R 00n V 00K R 00K R 00K R 00K R 00K R 00K R 00K R0 00K R V SLK SS INT 0K R V SPI isplay, SPI Touchscreen
6 lock iagram lock_iagram.schoc US, Power & Serial US_Power_Serial.Schoc MU MU.Schoc nalog nalog.schoc Misc Misc.Schoc P text MTSX00 HPI0 KEIL Tools by RM (logo) escriptions on all jumper links escriptions on prototyping power pads escriptions on power LEs Polarity markings on pads micros next to card connector OM next to way connector ortex debug next to debug connector M Prototyping areas M FOOT LUE M FOOT LUE M FOOT LUE M FOOT LUE GN GN Fiducial pads FI FI FI FI PROTOXX00TH M M M M M M M0 M M M M M PROTO0XX0SM M M M M M M0 M M M M See efault_jumper_settings.pdf for jumper link placement. THUMWHEEL LUE FIT TO R PROTOXX0SM SYM SYM P Pb PbFREE WEEE SYM MO MOIENT NOTE This sheet may be omitted from customer schematics HPI0 MTSX00 Evaluation oard ate: Number: HI0 Revision: 0 0/0/0 Time: :: MTSX00.Schoc Sheet of
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PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]
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VCC 21 VCC 52 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD
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AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%
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0603/15p/10v L R/100MHz. 100nF/50V. 100nF/16V. 100nF/50V C105 C106 C108 C107 GND GND GND GND
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Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0
Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP
ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B
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NOTE: please place R8 close to J1
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ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board
ZRMZN0000KITG rimzon evelopment oard Kit PUG000-0 Product User Guide Introduction Zilog s ZRMZN0000KITG rimzon evelopment oard Kit is designed for use as a target with the rimzon In-ircuit Emulator (ZRMZNIE0ZEMG).
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MUSIC. California Institute of Technology. HEMT Power Supply Precision Voltage Source. D. Miller 8/17/2011 REVISION RECORD LTR DATED: C31 5V_ID 10K
REVISION REOR EO NO: PPROVE: TE: V_I R 0K.V_REF V 0.uF _SHN V_IN GN GN U GN V_OUT_F V_OUT_S GN LT 0uF R 0k 0uF IN IN VOS_TRIM VOS_TRIM U N OPE OUT.V_REF R 0k 0uF IN IN VOS_TRIM VOS_TRIM U N OPE OUT 9 00pF
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FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate
FUNCTION. Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers Digital Audio Interface - Test pin header. Regulator 1.2V.
[K-] K- K Evaluation oard Rev.0 GENERL ESRIPTION The K- is an evaluation kit for the K; a digital signal processor (SP) with channels digital data interface. It realizes an easy evaluation of the audio
3JTech PP TTL/RS232. User s Manual & Programming Guide
JTech PP-00 TTL/RS User s Manual & Programming Guide Revision. J Tech o., Ltd. Fu-Hsing N. Rd., F Taipei, Taiwan Tel: +--00 9 info@jtech.com.tw JTech (J Eng.), Inc. E. Valley lvd., Suite ity of Industry,
PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.
R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument
AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115
PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.
DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.
R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H
Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.
PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional)
Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header
esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use
256-Position SPI Compatible Dual Digital Potentiometer AD5162
Evaluation oard User Manual -Position SPI Compatible D Steps To Setup The Evaluation oard. Install D Software. Open D Rev.exe. Provide Power SupplyOr Use Power from Parallel Port +V. Configure oard and
REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK
REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown
All use SMD component if possible
R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off
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COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT
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For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used!
JP RS_SELET V For max ROUT is low when RIN is disconnected enabling the MX (RS-) This will not work if MX is used! V On Front Panel -F (To Pg.) RS- RE_ RE_ RV_Y RV_Z 0.uF V U MXUK STR U- H G U MX 0 Y Z
LED POWER STAGE1 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE2 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE3 NOT_EN LED+ PWM
MU LE POWER STGE MU MX LI LI_TX LI_RX THERMISTOR- MX_RX MX_TX MX_E MX_/RE EN_ EN_ EN_ EN _ V LE Power Stage LE POWER STGE LE+ LE- LE+ LE- R R 0 J 0 Way 0 LI_TX LI_RX MX_RX MX_TX MX_E MX_/RE V LE Power
Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA
Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive
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9-; Rev ; / MAXQ0 Evaluation Kit General Description The MAXQ0 evaluation kit (EV kit) provides a proven platform for conveniently evaluating the capabilities of the MAXQ0 low-power, -bit, RISC microcontroller
Channel V/F Converter
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Table of ontents Notes lock iagram isplay and Tower onnectors MU & apacitive Touch kt Rev X X escription Revisions Initial Release ate -JUL- pproved hanged Power L colours-jul- Removed J and J dded J &
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ADSP-CM419F EZ-KIT SCHEMATIC
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CONTENTS: REVISION HISTORY: NOTES:
ONTENTS: PGE - ONTENTS PGE - POWER, XOS PGE - SI, SI, JTG PGE - S/eMM, US, HMI, GPIO, OMPOSITE PGE - SOIMM REVISION HISTORY: V.0 - /0/0 NOTES: These reduced schematics omit core SMPS and LPR circuitry
PCAN-MicroMod Evaluation Kit. Test and Development Environment for the PCAN-MicroMod. User Manual
Test and Development Environment for the PCAN-MicroMod Products taken into account Product Name Item Number Model PCAN-MicroMod Evaluation Kit (incl. PCAN-Dongle) PCAN-MicroMod Evaluation Kit (incl. PCAN-USB)
JS3 VDDA PTA7/KBD7. Jmp VSSA PTA6/KBD6 PTA5/KBD5 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 33 FP-1 PTA0/KBD0 VSSAD PTC3 VDDAD
fb_inj fb_inj JS0 JS JS U JS Vsyn JS V PT/K 0 VSS PT/K GMXF- GMXF PT/K OS- JS OS PT/K OS- OS PT/K Squirt- RST PT/K ccel- PT0 PT/K Idle- JS Warmup- PT PT0/K0 FP- PT VSS 0 PT V TX- PT PT/ 0 JS JS0 RX- PT0/Tx
LED_POWER_STAGE1 PWM GND ADJ LED- -12V R2 RA. LED Power Stage LED_POWER_STAGE2 PWM GND ADJ LED- -12V R4 RB. LED Power Stage LED_POWER_STAGE3
MU THERMISTOR- MU LI_RX LI_TX LI_RX LI_TX MX_TX MX_RX MX_/RE MX_E MX_TX MX_RX MX_/RE MX_E MX_LI +.V_MU R 0K R 0K R R R R LE_POWER_STGE - Out GN J LE- -V LE Power Stage LE_POWER_STGE - Out GN J LE- -V LE
Revision History. EFM32 Wonder Gecko MCU Plugin. Rev. Description. Board Function. Page. EFM32 Wonder Gecko MCU Plugin Board
EFM Wonder Gecko MU Plugin oard Function Page History Rev. escription Front Page EFM Microcontroller Initial Version. Imported from GG MU Plugin oard. EFM Power EFM onnectors Signal ssignments # Signal
PCIextend 174 User s Manual
PIextend 7 User s Manual Preliminary M6- February Sycard Technology 8-F Miraloma Way Sunnyvale, 98 (8) 79- (8) 79- FX PIextend 7 User s Manual Page. Introduction Sycard Technology's PIextend 7 PI extender
Audio Mod RF-04-N-10 PC13 BAS85 56 PG1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PG0 57 PG2 87 PG3 88 PG4 89 PG5 90 PG6 91 PG7 92 PG8
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FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M.
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HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0.
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THAT Corporation. QSC Digital Cinema Monitor DCM-2/DCM-3 Monitor Board
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PCB NO. DM205A SOM-128-EX VER:0.6
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Xilinx Virtex -E Evaluation Kit
Xilinx Virtex -E Evaluation Kit November, 000 (Version.) RFT Features FPG Xilinx Virtex-E XV00E-PQ0 SPROM Xilinx XV0SO0 oard I/O onnectors Two 0-pin, 0. Header connector Pads for three MITOR connectors
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AKD4554-E Evaluation board Rev.0 for AK4554
SHI KSI [K4554] K4554- valuation boar Rev.0 for K4554 GNRL SRIPTION K4554- is an evaluation boar for the portable igital auio 6bit / an / converter, K4554. The K4554- can evaluate / converter an / converter
USBF USBF.prj. Title: Section: USBF-01. B Designer: Brian Ashelin Date: COMMUNICATIONS COMMUNICATIONS ADC ADC INPUT VCA 4 PAGE 7 PAGE 1 PAGE 5 PAGE 2
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0 [] [] [] [] [] [] [] [] [] [] [] [] MOSI MISO SK 0 H H N_MS TMS RX TX SL J P_MOSI P_MISO P_SK P_ P_IO0 P_IO P_IO P_ P_ 0 P0_GN P_NT P_GN/NT P_RXL/SS P_TXL P_IO P_(SL) P_(S) P_ P_0 0 P0_ P_ P_IO P_R+
XR21B1422/1424 POWER & USB 1.0 Date: Thursday, February 13, 2014
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DESIGNATION QTY DESCRIPTION SUPPLIER
Rev 0; /0 DS00 EMV Evaluation Kit General Description The DS00 evaluation kit (EV kit) is a proven platform to conveniently evaluate the capabilities of the DS00 smart card interface chip. It includes
01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES
Table of ontents 0 TITLE PGE 0 MU 0 EUG INTERFE 0 SUPPLY 0 POWER RIGE 0 MOSFET RIVERS / VI SENSING utomotive Product Group 0 William annon rive West ustin, T 9 esigner:. ZUZEK rawn by:. ZUZEK pproved:
X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies
Table of ontents lock iagram Type- onnector US/US PTN0 P TP Shield Headers P Source and Sink LS V, V0, V Supplies Rev escription ate pproved Prototype Release -Mar- K ring up to NL and make updates requested
RX-62N Multi-Breakout Board Options
RX-N Multi-Breakout Board Options The RX-N Multi-Breakout Board is designed to be a low-cost prototyping tool designed for hand-assembly. Using this document and the related drawings, the board can be