Xilinx Virtex -E Evaluation Kit

Transcription

1 Xilinx Virtex -E Evaluation Kit November, 000 (Version.) RFT Features FPG Xilinx Virtex-E XV00E-PQ0 SPROM Xilinx XV0SO0 oard I/O onnectors Two 0-pin, 0. Header connector Pads for three MITOR connectors Pads for one 0 pin General Purpose I/O interface Power.0 Power onnector. V Regulated Supply. V Regulated Supply Full ypass apacitance ommunication RS Serial Port onfiguration JTG Header onnector In-System Programmable PROM JTG ownload able Miscellaneous IP switches Push-buttons, ual igit Segment LE, right hand decimal Infrared Transceiver LEs 0 MHz Oscillator igital Thermometer emonstration application (Source VHL) Simple RS igital Thermometer LE Patterns escription The Evaluation Virtex-E Kit is used by engineers as a platform to test FPG designs that are targeted to the Xilinx Virtex-E device. It is also a great tool for beginners to get aquatinted with FPGs and VHL. dvance Product Specification The Virtex-E device is located in the center of the board. It can be configured via a JTG download or from the on board configuration PROM. The configuration PROM is also programmable through the JTG cable. Over signals are connected from the FPG to 0. header connectors for user connections. Other are connected to LE, dip switches, Two push buttons, RS- line driver/receiver, and a digital thermometer. emo pplication. The board is supplied with complete VHL source code that: ) Sequences LEs ) Reads ip Switches/push buttons ) Senses Temperature and displays value on dual segment LE ) Transmits startup message through RS- connector. ) Echoes RS- commands. (Serial cable not included) Ordering Information The following table lists the development system part numbers and available software options. Internet Link at Table Evaluation Virtex-E oard Part Number S-XLX-VE-EVL Hardware Xilinx Virtex-E Evaluation Kit November, 000 (Version.) Literature # S-000 Page - 000, vnet, Inc. ll rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc. ll other trademarks and registered trademarks are the property of their respective owners.

2 Xilinx Virtex-E Evaluation Kit S Evaluation Virtex-E oard This section provides information basic to the design of Evaluation Virtex-E oard board. Virtex-E FPG The Virtex-E Field-Programmable Gate rray device (U) utilized in this design is the 00K-system gate device (XV00E) in a PQ0 package. FPG onfiguration onfiguration information is provided from two sources; the JTG onnector (JTG0), and configuration PROM. Table JTG onnector Power The majority of the design is powered at.v with the Virtex-E FPG core powered at.v. The board should be powered by a -volt bench supply. The.V is derived via a linear regulator. linear regulator from the.v provides the.v Xilinx core voltage. barrel connector J (RP) is provided on the board for lab supply connections. The center tap is.0 volts and the outer is. Note: The lab supply should be regulated at.0 volts. While current requirements are dependent on the user application, it is suggested to limit your supply to. amps on initial power up. φ 0.0 in pin diameter φ 0. in housing diameter Signal Name JTG onnector Pin # TI TMS TK TO Jumpers JP, JP and JP select the configuration mode of the Virtex. The following table shows the jumper setting needed for each mode. Table Mode Select onfiguration Pullups JP/M JP/M JP/M0 Mode Master-serial No OFF /LOW OFF /LOW OFF /LOW oundary-scan No ON /HIGH OFF /LOW ON /HIGH SelectMP No ON /HIGH ON /HIGH OFF /LOW Slave-serial No ON /HIGH ON /HIGH ON /HIGH Master-serial Yes ON /HIGH OFF /LOW OFF /LOW oundary-scan Yes OFF /LOW OFF /LOW ON /HIGH SelectMP Yes OFF /LOW ON /HIGH OFF /LOW Slave-serial Yes OFF /LOW ON /HIGH ON /HIGH.0 Volts Printed ircuit oard The Evaluation Virtex-E oard printed circuit board is an -layer board with four signal layers, a full.v power plane incorporating an isolated.v mini-plane, and full ground plane. The board stack-up layers through is: ) omponent side /signal ) Ground Plane ) Signal ) Signal ) Power:.V and.v ) Solder side /signal The LE indicates the output level of the ONE pin of the Virtex-E device. It will illuminate when the Virtex-E configuration is complete. System lock n oscillator socket clock output is connected to the Virtex-E device. U is connected to Global lock Input #0 (PQ0 pin #P), The U socket is populated with a 0 MHz oscillator. synchronous (RS) ommunication Interface The M device provides level translation for a single RS interface ( connector). The second translation port on the device is terminated and unused. Page - Literature # S-000 November, 000 (Version.) 000, vnet, Inc. ll rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc. ll other trademarks and registered trademarks are the property of their respective owners.

3 Xilinx Virtex-E Evaluation Kit Miscellaneous Table RS Interface Signals RS SIGNL Virtex-E PIN # ROUT P TIN P EN_N P S_N P Table RS onnector Pinout Signal Name P () connector Pin # TX out RX in The Miscellaneous interfaces on the Virtex-E board consist of a single -position IP switch (-individual SPST switches), LEs, and two push-button switches. Table ip Switch Signals IP SW Virtex-E PIN # # P # P # P # P00 # P0 # P0 # P0 # P0 Table Push utton Switch Signals UTTON Virtex-E PIN # SW P0 SW P0 Table ual Segmented LE Signals LE Virtex-E PIN # E F G p E F G p P P P P P P P0 P P P P P P P P P Table 0 Infrared Signals LE Virtex-E PIN # TX RX SHN P0 P0 P00 Table igital Themometer LE Virtex-E PIN # E SLK SI SO P0 P P P Table LE ontrol Signals LE Virtex-E PIN # P P P P P P P P November, 000 (Version.) Literature # S-000 Page - 000, vnet, Inc. ll rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc. ll other trademarks and registered trademarks are the property of their respective owners.

4 Xilinx Virtex-E Evaluation Kit I/O Signal Headers Two 0-pin connectors provides Virtex-E I/O lines and ground pins. Table GP Signals JP GP ONNETOR PIN Virtex-E PIN # # P P P P P0 P P P P 0 P P P0 P P P P P P P 0 P P P P P P P P P P 0 P0 P0 P0 P P P P P P0 P 0 P P P P0 Reserved Reserved Reserved Reserved 0 Table GP Signals JP GP ONNETOR PIN Virtex-E PIN # # P P P P P P P P0 P 0 P P P P P P0 P P P P 0 P P0 P P P P P P P0 P 0 P P P P P P P P P P 0 P P0 P Reserved Reserved Reserved Reserved Reserved 0 Page - Literature # S-000 November, 000 (Version.) 000, vnet, Inc. ll rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc. ll other trademarks and registered trademarks are the property of their respective owners.

5 Xilinx Virtex-E Evaluation Kit Logic nalyzer onnector Three MP MITOR connector pads are provided to connect to a logic analyzer s mass termination cable. Table MITOR J onnector PIN # Virtex-E Name PIN # N/ N/ N/ N/ N/ N/ N/ N/ P0* LK_OUT P OS P0 RESS P RESS P0 RESS0 0 P RESS P0 RESS P RESS P RESS P RESS P RESS P0 RESS P RESS P RESS0 P RESS 0 P RESS P RESS P RESS P RESS P RESS P RESS P RESS P RESS P RESS P RESS0 0 P0 RESS P RESS P RESS P RESS P RESS P RESS P RESS P RESS P RESS0 0 Table MITOR J onnector PIN # Virtex-E Name PIN # N/ N/ N/ N/ N/ N/ N/ N/ P* GK P* GLK P T P T P T0 0 P0 T P T P T P T P T P0 T P T P T P T0 P T 0 P T P T P T P T P0 T P T P T P T P T P0 T0 0 P T P T P T P T P T P T P T P T P T0 0 November, 000 (Version.) Literature # S-000 Page - 000, vnet, Inc. ll rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc. ll other trademarks and registered trademarks are the property of their respective owners.

6 Xilinx Virtex-E Evaluation Kit onnector PIN # Table MITOR J Virtex-E PIN # Name N/ N/ N/ N/ N/ N/ N/ N/ P0* LK_OUT P* LK_IN P OUT P NTL P0 SWITH 0 P NTL P0 SWITH P NTL P TEMP_SO P NTL P TEMP_SI P NTL P0 TEMP_E P0 NTL0 P TEMP_SLK 0 P NTL P0 RSS_N P NTL P RSEN_N P NTL P RSTX P NTL P RSRX P0 NTL P NTL0 0 P NTL P0 NTL P NTL P NTL P NTL P NTL P NTL P NTL P NTL0 0 *Note: zero ohm resistor may be required to access the noted signals. vus onnector High-density connector pads are located on bottom of the board. The signals are listed in the following table. Table vus onnector P Name FPG PIN # onnector PIN # FPG PIN # Name RESS0 P N/ N/ P RESS RESS P P RESS RESS P0 P RESS RESS P P RESS RESS P UX_.V.V P RESS RESS P0 P RESS0 RESS P 0 0 P RESS RESS P P RESS RESS P N/ N/ P RESS RESS P P RESS RESS0 P P RESS RESS P P RESS RESS P UX_.V.V 0 0 P RESS RESS P P RESS RESS P P0 RESS RESS P0 P0 RESS0 T0 P N/ N/ P T T P P T T P P T T P P T T P 0 UX_.V.V 0 P T T P 0 P T0 T P 0 0 P T T P 0 P0 T T P 0 N/ N/ 0 P T T P 0 P T T0 P0 0 0 P T T P P T T P UX_.V.V P T T P0 P T T P P T T P P T0 NTL0 P N/ N/ 0 0 P NTL NTL P P NTL NTL P P0 NTL NTL P P NTL NTL P UX_.V.V P NTL NTL P P0 NTL0 Page - Literature # S-000 November, 000 (Version.) 000, vnet, Inc. ll rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc. ll other trademarks and registered trademarks are the property of their respective owners.

7 Xilinx Virtex-E Evaluation Kit Name FPG PIN # onnector PIN # FPG PIN # Name NTL P P NTL NTL P 0 0 P NTL NTL P N/ N/ P NTL NTL P0 P NTL NTL0 P P* LK_IN LK_OUT P0* P0* LK_OUT_F TMS UX_.V.V TO TI TK TRS 0 0 *Note: zero ohm resistor may be required to access the noted signals. Note: Reference Schematic for current JTG signal paths. emonstration Program Supplied with the development system is a demonstration program file that utilizes several devices on the evaluation board. The demonstration program uses the evaluation development board as a standalone platform that is connected to a lab supply and a terminal emulation program. On power up the onboard PROM will configure the FPG. Upon completion of the configuration the FPG functionality and input/output signal will activate. start up serial message will be sent to the terminal port via the RS- connection. The LEs will display a back and forth scanning pattern or -bit value corresponding to the current temperature. The ual segmented display will count up or display the current temperature. dditional Items Needed: Lab power supply,.0 volts at. amps. Serial Terminal or Terminal Emulator. RS- cable Setup: ) ttach the lab supply to the power connector on the Evaluation oard. ) ttach the serial terminal to the P connector of the Evaluation oard. ) Set the Serial Terminal to: data bits, stop, No parity, 00 baud. ) Verify jumper are NOT installed on JP,JP,and JP. ) Verify JP is installed across pins and. Power UP: ) pply power to the Evaluation oard. ) The ONE LE will light on the completion of the download. Reset: ) Press the Soft Reset button SW to reset the board. Serial emo ) Press the button SW to send the startup message. 0) The Power up message is displayed on the serial terminal. ) ll characters typed should be echoed to the terminal. ) Press the Reset button again to reset startup message. LE SN ) Set the dipswitch S dip to ON (rocker up). ) The LEs should be blinking such that the illuminated led should be scanning back and forth through the LE array. UP OUNTER ) Set the dipswitch S dip to ON (rocker down). ) The ual segmented LEs should be counting up. TEMPERTURE ) Set the dipswitch S dip to OFF (rocker down). ) The LE should now display the temperature in in two s complement binary. See the following table. ) Set the dipswitch S dip to OFF (rocker down). 0) The ual segmented LEs should now display the temperature in. ) Hold your finger on U to change the temperature. LE Pattern ecimal Value ( ) (..) November, 000 (Version.) Literature # S-000 Page - 000, vnet, Inc. ll rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc. ll other trademarks and registered trademarks are the property of their respective owners.

8 Xilinx Virtex-E Evaluation Kit Relevant ocuments ocuments relevant to this application are listed in the following table. Table. Relevant ocuments and Links ocument XILINX VIRTEX-E FPG ata Sheet lock iagram Source nfo/ds0.pdf ocument XILINX XV0 onfiguration PROM ata Sheet nalog evices M V RS Line river/receiver ata Sheet Source nfo/ds0.pdf M0_0.pdf RS- ual -Segment LE JTG Header LES ip Switches 0MHz OS igital Thermometer XILINX VIRTEX-E XV00E-PQ0 Push uttons FPG XILINX XV0SO0 0 Pin Header Infrared Transceiver 0 Pin Header MITORs vus oard to oard 0 Pin onnector onfiguration PROM Revisions Version.0 Version. Initial Release. Fixed typographical errors. Page - Literature # S-000 November, 000 (Version.) 000, vnet, Inc. ll rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc. ll other trademarks and registered trademarks are the property of their respective owners.

9 Mini-Virtex-E Evauation oard vnet esign Service s REV SHEET ESRIPTN TE LL Initial Release -OT m Function Sheet Number Lead Sheet FPG, SPROM Power Mictor and Header onnectors Switch, LE, OS aughter oard onnector opyright 000, vnet, Inc. ll Rights Reserved. This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in any form or by any means without the prior written permission of vnet, Inc. VNET and the V logo are registered trademarks of vnet, Inc. ll trademarks and trade names are the properties of their respective owners and vnet, Inc. disclaims any proprietary interest or right in trademarks, service marks and trade names other than its own. vnet is not responsiblefor typographical or other errors or omissions or for direct, indirect, incidental or consequential damages related to this material or resulting from its use. vnet makes no warranty or representation respecting this material, which is provided on an "S IS" basis. VNET HEREY ISLIMS LL WRRNTIES OR LIILITY OF NY KIN WITH RESPET THERETO, INLUING, WITHOUT LIMITTN, REPRESENTTNS REGRING URY N OMPLETENESS, LL IMPLIE WRRNTIES N ONITNS OF MERHNTILITY,SUITILITY OR FITNESS FOR PRTIULR PURPOSE, TITLE N/OR NON-INFRINGEMENT. This material is not designed, intended or authorized for use inmedical, life support, life sustaining or nuclear applications or applications in which the failure of the product could result in personal injury, death or property damage. ny party using or selling products for use in any such applications do so at their sole risk and agree that vnet is not liable, in whole or in part, for any claim or damage arising from such use, and agree to fully indemnify, defend and hold harmless vnet from and against any and all claims, damages, loss, cost, expense or liability arising out of or in connection with the use or performance of products in such applications. Title LIT# S-000 vnet, Inc. esign Services opyright 000 Mini-Virtex-E oard - Lead Sheet Size ocument Number Rev H-XLX-MVE-00 ate: Tuesday, October, 000 Sheet of

10 NOT POPULTE NOT POPULTE NOT POPULTE H-XLX-MVE-00 Mini-Virtex-E oard - Lead Sheet Tuesday, October, 000 Title Size ocument Number Rev ate: Sheet of vnet, I nc. esign Services opyright 000 MOE0 TMS FPG_TO TK LK INIT_N TMS TK 0 ONE SP_TI ONN_TO ONN_TI TMS TK FPG_TO SP_TI ONN_TO FPG_TO ONN_TI SP_TI MOE SP_TO S_N ONN_TK ONN_TK ONN_TMS ONN_TMS T0 T TK FPG_TO T0 T ONE T T T WRITE_N S_N MOE INIT_N 0 SP_TO MOE0 T T T T T T MOE T RESS LK F_N T T T0 T0 TMS T T T T T T T T T T MOE T T WRITE_N T T RESS RESS RESS RESS RESS RESS RESS0 RESS RESS RESS0 RESS RESS RESS RESS0 RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS0 NTL0 NTL NTL NTL NTL NTL NTL NTL NTL NTL NTL0 NTL NTL NTL NTL NTL NTL NTL NTL NTL NTL0 SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH0 LE0 LE LE LE LE LE LE LE F_N SWITH[0:] JTG_TMS JTG_TI JTG_TO JTG_TK JTG_TRS OS RESS[0:] NTL[0:0] GK LK_OUT_F T[0:] RSRX RSTX RSEN_N RSS_N SEG_ SEG_G SEG_G SEG_ SEG_E SEG_p SEG_ SEG_ SEG_p SEG_ SEG_ SEG_E SEG_ SEG_ SEG_F SEG_F TEMP_E TEMP_SO TEMP_SI TEMP_SLK GK_F GK OS_F OUT LK_OUT IR_SHN IR_RX IR_TX LE[0:] LK_IN.V.V R o Not Populate U X0SO0 0 0 LK RST/OE E 0/T /F EO TMS TK TI TO J o Not Populate om U VIRTEX E - PQ GK _LVS_LL_LN _VREF _LP_Y _VREF_LN_Y _LP_Y _LN_Y _LP_YY _LN_YY _LP_YY _VREF_LN_YY _VREF _LP_YY _LN_YY _VREF_L0P_Y _L0N_Y _S_LP_YY _WRITE_LN_YY _LP _VREF_LN _LP_YY _LN_YY _VREF_LP_YY _LN_YY _VREF_L0P_YY _L0N_YY _LP_YY _LN_YY _LP_Y _LN_Y _VREF_LP_Y _LN_Y _VREF _LVS_LL_LP GK _LN_YY _LP_YY _VREF_LN _LP LN_Y _VREF_LP_Y _L0N_Y _L0P_Y _LN_YY LP_YY LN_Y _VREF_LP_Y _LN_Y _VREF_LP_Y _LN_Y _LP_Y _VREF _IN_0_LN_YY _OUT_USY_LP_YY LK TO ONE _INIT_LN_YY LP_YY _L0N _VREF_L0P _LN_Y _LP_Y _VREF_LN_Y _LP_Y _VREF_LN_Y LP_Y LN_YY _LP_YY _LN_Y _LP_Y _VREF_LN_Y LP_Y _VREF _LP_Y _LN_YY _LP_YY _LN_YY _VREF_LP_YY _LN_YY _VREF_LP_YY _LN_YY _LP_YY _VREF _LN_YY _LP_YY GK0 _LVS_LL_L0P _VREF_LN _LP _LN_Y _VREF_LP_Y _LN_Y _LN_YY _LP_YY _LN_Y _VREF_LP_Y _LN_YY _LP_YY _VREF_LN_YY _LP_YY _VREF_LN_YY _LP_YY _LN_YY _LP_YY _LN _VREF_LP _VREF _LVS_LL_L0N GK _VREF_LP _LN _LP_Y _VREF_LN_Y _LP_Y _LN_Y _LP_YY _LN_YY _LP_Y _VREF_LN_Y _L0P_Y _VREF_L0N_Y _LP_Y _LN_Y _VREF _LP_YY _LN_YY _LN_Y _VREF_L0P_Y _L0N_Y _LP_YY _LN_YY _LP_Y _LN_Y _VREF_LP_Y _LN_Y _VREF _LP_YY _LN_YY _LP _VREF_LN _LP_Y _LN_Y _VREF_LP_Y INT INT INT INT INT INT INT INT INT INT INT INT M0 M M PROGRM TK TI TMS QTLP0- R 0R0/00 R K R 0R0/00 JTG JTG Header J o Not Populate om R o Not Populate R 0R0/00 JP HEER x R0 o Not Install R o Not Install R o Not Populate R o Not Install R 0K JP HEER x R 0K R 0K 0.uF R o Not Install JP HEER x R.K

11 JP HEER UX.V.V J RP V TN_uF IN U LV. OUT T.V TN_uF.V 0.uF U IN OUT IN OUT EN F RST N N N N TPSQPWP 0 /HS /HS /HS /HS /HS /HS 0 /HS /HS R o Not Populate R o Not Populate R.V 0K 0% TN_0uF.V Virtex-E ecoupling ap s 0. uf per Vccco uf per ank 0.uF 0.uF 0 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF TN_uF.V Virtex-E ecoupling a ps 0.uf per Vccin t four uf per devi ce one 0uF per devi ce 0.uF 0.uF 0 0.uF 0.uF TN_uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF TN_uF 0.uF TN_uF 0.uF TN_uF 0.uF 0.uF 0 TN_uF TN_uF 0 TN_0uF 0 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF TN_uF TN_uF TN_uF TN_uF TN_uF VNET, IN. ONFIENTIL Title vnet, Inc. esign Services opyright 000 Mini-Virtex-E oard - Power Size ocument Number Rev H-XLX-MVE-00 ate: Tuesday, October, 000 Sheet of

12 RESS[0:] RESS0 RESS RESS RESS RESS RESS0 RESS RESS RESS RESS RESS0 RESS RESS RESS RESS RESS0 NTL[0:0] NTL0 NTL NTL NTL NTL NTL0 OS R0 OUT 0R0/00 NOT POPULTE T[0:] NTL[0:0] NOT POPULTE R 0R0/00 GK GK NOT POPULTE R NOT POPULTE T0 T T T T T0 T T T T T0 T T T T T0 NTL NTL NTL NTL NTL R 0R0/00 0R0/00 LK_OUT_F JP JP RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS NTL NTL[0:0] NTL NTL NTL NOT POPULTE NTL 0R0/00 R T T T T T T T T T T T T T T T T NTL NTL NTL NTL NTL0 R 0R0/00 NOT POPULTE NOT POPULTE 0R0/00 R R 0R0/00 NOT POPULTE NTL[0:0] GK_F OS_F LK_IN LK_OUT RESS[0:] T[0:] NTL[0:0] LK_IN OS GK MITOR(MP -00-) J RESS0 RESS RESS /0:0 /:0 RESS RESS /0: /: RESS RESS /0: /: RESS RESS /0: /: 0 RESS0 RESS /0: /: RESS RESS /0: /: RESS RESS /0: /: RESS RESS /0: /: RESS RESS /:0 /:0 0 RESS RESS0 /: /: RESS RESS /: /: RESS RESS /: /: RESS RESS /: /: RESS RESS /: /: 0 RESS0 RESS /: /: RESS /: /: LK:/Q LK:0/Q0 LK_OUT n/c n/c n/c T0 T T T T T T T T T T0 T T T T T NTL0 NTL NTL NTL NTL NTL NTL NTL NTL NTL NTL0 NTL NTL NTL NTL NTL 0 MITOR(MP -00-) J /0:0 /:0 /0: /: /0: /: /0: /: 0 /0: /: /0: /: /0: /: /0: /: /:0 /:0 0 /: /: /: /: /: /: /: /: /: /: 0 /: /: /: /: LK:/Q LK:0/Q0 n/c n/c n/c 0 MITOR(MP -00-) J /0:0 /:0 /0: /: /0: /: /0: /: 0 /0: /: /0: /: /0: /: /0: /: /:0 /:0 0 /: /: /: /: /: /: /: /: /: /: 0 /: /: /: /: LK:/Q LK:0/Q0 n/c n/c n/c 0 T T T T T0 T T T T T T T T T T0 T GK NTL NTL NTL NTL NTL0 SWITH SWITH LK_OUT RSRX RSTX RSEN_N RSS_N TEMP_SLK TEMP_E TEMP_SI TEMP_SO OUT SWITH[0:] Title vnet, Inc. esign Services opyright 000 Mini-Virtex-E oard - onnectors Size ocument Number Rev H-XLX-MVE-00 ate: Tuesday, October, 000 Sheet of

13 LE0 LE LE LE LE LE LE LE LE[0:] 0K R 0K R 0K R SWITH[0:] QTLP0- R K QTLP0- R K QTLP0- R K QTLP0- R K QTLP0- R K QTLP0- R K QTLP0- R K QTLP0- R K 0K R0 S -0-0 SWITH0 SWITH SWITH SWITH SWITH SWITH SWITH SWITH OS U OUT OS OS/SOKET ENLE 0R0/00 R R0 o Not Populate 0.uF IR_TX IR_RX U TX RX LE LE R 0,.R R 0,.R SW J--000E SW J--000E 0K R 0K R 0K R 0K R 0K R 0K R SWITH SWITH IR_SHN SHN 0.uF 0.uF RSS_N RSEN_N 0.uF 0.uF 0.uF 0 U 0.uF EN V - - V- TOUT RIN ROUT S TOUT RIN ROUT n/c TIN TIN n/c MRS RSTX RSRX uF P R - TEMP_E TEMP_SLK 0R0/00 Mode TFU0E U V V E SERMOE SLK SI SO SU.uF, TN R 0R0/00 TEMP_SI TEMP_SO R O NOT POPULTE SEG_E R0 0 SEG_ R 0 SEG_ R 0 SEG_p R 0 SEG_E R 0 SEG_ R 0 SEG_G R 0 SEG_ R 0 SEG_p R 0 SEG_ R 0 U 0 E N/ N/ F p G E G S S p F 0 MN Title R 0 R 0 R 0 R 0 R0 0 R 0 vnet, Inc. esign Services opyright 000 Mini-Virtex-E oard - Switch, LE, OS Size ocument Number Rev H-XLX-MVE-00 SEG_F SEG_G SEG_ SEG_ SEG_F SEG_ ate: Tuesday, October, 000 Sheet of

14 NOT POPULTE NOT POPULTE NOT POPULTE H-XLX-MVE-00 Mini-Virtex-E oard - aughter oard onnector Tuesday, October, 000 Title Size ocument Number Rev ate: Sheet of vnet, Inc. esign Services opyright 000 RESS RESS RESS RESS RESS RESS RESS RESS RESS0 RESS RESS RESS RESS0 RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS RESS0 RESS RESS RESS RESS RESS0 T T T T T T0 T T T T T0 NTL0 NTL NTL NTL NTL NTL NTL NTL NTL NTL NTL0 NTL NTL NTL NTL NTL NTL0 NTL NTL NTL NTL T T T T T T T T T T T T0 T T T T0 T T T T T RESS[0:] T[0:] NTL[0:0] NTL[0:0] LK_OUT LK_IN LK_OUT_F JTG_TMS JTG_TI JTG_TRS JTG_TO JTG_TK T[0:] UX.V R 0R0/00 R0 0R0/00 P V V V V.V.V.V.V.V TMS.V TI TRST TO TK V V R 0R0/00