3JTech PP TTL/RS232. User s Manual & Programming Guide
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1 JTech PP-00 TTL/RS User s Manual & Programming Guide Revision. J Tech o., Ltd. Fu-Hsing N. Rd., F Taipei, Taiwan Tel: info@jtech.com.tw JTech (J Eng.), Inc. E. Valley lvd., Suite ity of Industry, 9 US Tel: info@jtech.com
2 Revision History Revision ate hanges.0 Oct,00 First Release / Kiwi Huang. Oct 9,00 onnector definition. Related ocuments or Files ) SI0 silicon data sheet ) IPx S-P0-00 modem chip set data sheet ) PP-00 T command sets.. Table of ontents General escription pplication Specification onnector definition Mechanical rawing Schematic.. JTech o., Ltd. onfidential
3 General escription The PP-00TTL is a highly integrated, low-cost, high performance, and low-power dissipation modem module. This module implements V.90 to achieve Internet connection rates up to Kbps, supporting existing V. data mode, lass FX mode. provide a TTL level serial interface for connecting to TE terminal and provide reliable connection with connection rate ranging from 00bps up to 00bps pplication Stand-alone modem Set-top box. Internet ccess. Remote ccess and control. Fax server. JTech o., Ltd. onfidential
4 Specification. ata mode capabilities:. ITU-T V.90. ITU-T V.. ITU-T V.bis, V.. ITU-T V.bis,V.. ITU-T V., V.. ell. ell 0. FX mode capabilities:. ITU-T V., V.9, V.ter, and V. h. TI/EI class FX. V. error correction (LPM and MNP). V.bis and MNP class data compression. World wide call progress tone detection. Operating system support: OS, Windows 9, Windows 9, Windows NT, Windows ME and Windows 000. TI/EI 0 standard for T command set. TE speed up to 00 JTech o., Ltd. onfidential
5 onnector efinition Honda pin RS- interface. Pin# Signal irection Function/omments RTS# Input Request To Send. (RS- Level) TS# Output lear To Send. (RS- Level). SR# Output ata Set Ready. (RS- Level) RX# Output Receive ata (RS- Level) TX# Input Transmit ata (RS- Level) RI# Output Ring Indicator (RS- Level) # Output ata arrier etect. (RS- Level) TR# Input ata Terminal Ready. (RS- Level) 9 ommon Signal Ground 0 ommon Signal Ground. ommon Signal Ground 9.V Input Power Source input 9.V /00m. JTech o., Ltd. onfidential
6 onnector efinition J RS- TTL interface Pin# Signal irection Funvtion/omment Input Power source V /00m Input Input ommon Signal Ground ommon Signal Ground ommon Signal Ground 9 ommon Signal Ground 0 MRLE# Output Modem ready LE output. SR Output ata Set Ready. (RS- TTL Level) TR_N Input ata Terminal Ready. (RS- TTL Level) TS_N Output lear To Send. (RS- TTL Level) RTS_N Input Request To send. (RS- TTL Level). _N Output ata arrier etect. (RS- TTL Level) RI_N Output Ring Indictor. (RS- TTL Level). RX Output Receive ata. (RS- TTL Level) TX Input Transmit ata. (RS- TTL Level) 9 ommon Signal Ground. 0 ommon Signal Ground. RST# Input Reset Low active. TIP i-irec. Phone Line RING i-irec. Phone Line. JTech o., Ltd. onfidential
7 JTech o., Ltd. onfidential
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9 From atery V S G PP-00.SN. PP(T)-00/ (0.ZIP) Thursday, March, 00 Title Size ocument Number Rev ate: Sheet of 9.V RST# H_LE H_LE RI# # TX# RX# TS# SR# RTS# TR# SR TR_N 9.V Vbat Vbat V9 V9 R 0 SR0S/ O- Q MMT90/ SOT- SR0S O- U HIN0 SOP/SSOP TIN TIN TIN TIN TIN ROUT ROUT ROUT V+ V- TOUT TOUT TOUT TOUT TOUT RIN RIN RIN 0.u 00 R 0 SR0S O- R NI 0 N LL- R K R 0 SW SK0 0 S S S S S' S' S' S' 0.u J Female Header IP/.mm u 0.u 0.u Q MMT90/ SOT- 0.u R NI R K U IRF0TR SO- JP Honda pin 9 0 R9.K R0 0/ R K/ R.K R.K/ R K 0.u R K/ 00uF/0V x IP Q MPT90 SOT- R 0 Q MPT90 SOT- SR0S O- R.K U IS SOP VIN UTY /SHN F S+ S- RI R 0K L uh SM 9 00uF/0V x IP LE LE/EL09EGW/R IP T Molex P/M able/wg TX TS_N RI_N TR_N TR_N RTS_N _N RX TIP RTS_N TX TR_N _N TS_N RING RI_N RX RST# MRLE# MRLE#
10 + 0 pf 00 pf 00 Y +.V.9MHz T/9US U _R ISO 0 0. uf 00 RTS_N RX TX TS_N RESET_N 0. uf LKIN/XTLI SO/ XTLO / LKOUT/0 ES/ FSY/ 0 V. ISO 9 V. V RTS/ V 9 RX/R SI/ 0 TX/WR RI/ TS/S INT/0 RESET OUT/INT Sixx pin TSSOP _N TR_N RI_N OUT +.V 0. uf 0. uf 00 R 0 00 Z ZMM. V 0. uf LL- V99 SOT pf uf/v U I-X IN OUT SOT-9 0.u +.V +.uf/v 0 +.uf/v 0 9 may be used for reducing emissions. +.V R9 0K SPK KSF9P IP Pitch:.mm 0u/V x IP LM 0.u R 0 U + - uf/v R 0K R0.K 000p 0.u OUT OUT RST# 0.u U V OUT RNV0 SOT-- RESET_N Title Sixx, onnector Size ocument Number Rev PP-00.SN. Thursday, March, 00 ate: Sheet of
11 PP-00.SN. IPx/I Plus orp. Thursday, March, 00 Title Size ocument Number Rev ate: Sheet of FLHWR FLHWR PSEN PSEN SPO_T SPO_R SPO_FR F_LK RI_N POR\ OH\ RESET_N SP_SLK SPO_R OH\ POR\ F_LK SP_SLK SPO_T RI_N SPO_FR OUT +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V R9 0 R0 0 R 0 0.u Y.MHz 9/US 0.u p p L E p Q MPT90 SOT- 0.u R NI 0.u L.uH 0 R 0.u 9.u/V uF/V x IP U0 IPx TR# V.V RX#.V.V TX# ORST T.V RTS# SR# TS# MRLE# TRLE# # LE# HSLE# RI# OH# V.V.V FLHWR# PSEN# EXT/INT_ROM H0 H H H H H H H H H9 V.V H0 H H H H H H H V.V T0 R0 SLK FS0 OELK.V H0 H H H H H H H V.V OUT0 OUT OSI OSO.V.V OUT OUT OUT OUT OUT OUT LS# EET EESK EES V.V RESET#.V.V.V VOUTR 0.u 0 0.u L ead 00 U MX9F00(Kx) PL ~WE ~E ~OE 0 VPP 0.u R 0K 0.u R.K R NI U 9-. S SK I O ORG + 0.uF/V 0 R K 9 0.u R R R M R 0 U9 SI0 SOI pin 9 0 MLK FSY SLK V SO SI F RESET OUT M V M0 RGT OFHK TR_N RTS_N TS_N _N TX RX ISO _R OUT MRLE# RI_N
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Title Number Revision Size A Date: 0..00 Sheet of File: C:\Altium00\..\Board.sch Drawn By: SW SW-D-B-0 RESET + C 00UF/V C 00NF/0V C 00NF/0V VIN VOUT IC LMM0 + C 0UF/V X NG-DC0A D N00 D N00 D N00 D N00
Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI
All use SMD component if possible
R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off
SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:
R 0K0 RST U S_ PF/0V PF/0V 0FS FS T T 0SLK N SOT N SOT Y mhz U LS0 debug port 0 do not stuff R WR S PS X/Y IN/IN IR 0IR MO J R M R 0K0 R0 K00 R 0K0 dsck dr dsi dso / G 0 U LS0 R 0K0 SI_RX SI_TX SI_LK TFS
AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:
+V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V SHN 0
JS3 VDDA PTA7/KBD7. Jmp VSSA PTA6/KBD6 PTA5/KBD5 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 33 FP-1 PTA0/KBD0 VSSAD PTC3 VDDAD
fb_inj fb_inj JS0 JS JS U JS Vsyn JS V PT/K 0 VSS PT/K GMXF- GMXF PT/K OS- JS OS PT/K OS- OS PT/K Squirt- RST PT/K ccel- PT0 PT/K Idle- JS Warmup- PT PT0/K0 FP- PT VSS 0 PT V TX- PT PT/ 0 JS JS0 RX- PT0/Tx
Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.
PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional)
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[K-] K- K Evaluation oard Rev.0 GENERL ESRIPTION The K- is an evaluation kit for the K; a digital signal processor (SP) with channels digital data interface. It realizes an easy evaluation of the audio
Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.
lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January,
74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance
74HC164; 74HCT bit serial-in, parallel-out shift register
Rev. 03 4 pril 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They
CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H
V N N V N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H N_L N_L J ON N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H
DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.
R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H
NHT Pro. A20 Digital Meter. From Low. Voltage 3 R814. Power 3. Supply. From Left Power Amp. From. Rigjht 2. Amp R810 4.
igital Meter R0.K V 0 0.UF U0 R 0 V R0 K 0 0.uF 0.V R9 R K K V V V 0 09 0 N0 0UF/V Low 0UF/V 00UF/V R R 00K 00K 0 pf Left N0 0 N N 0 VR0 0K 0 0.uF R 0M 0 0.uF k U0 9 0 V0 0.uF N0 V PI 0 09 R R 0 SPL GREEN
74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state
Rev. 03 20 January 2006 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with
Stand by & Multi Block
_NEUTRL LX0S _LIVE 0.,.0mH + 0%, - 0% HOT Stand by & Multi lock TM0S MULTI TRNS(EER) M /KV RM0 M0 K/W(R) /00V M SFF00G(00V/0) 0 M0 M0 UF00 UF00 M UF00 OL M.uF/0V(L0W) QM OL S-GN ZM MMZVTG RM RM 00K(0)F
MUSIC. California Institute of Technology. HEMT Power Supply Precision Voltage Source. D. Miller 8/17/2011 REVISION RECORD LTR DATED: C31 5V_ID 10K
REVISION REOR EO NO: PPROVE: TE: V_I R 0K.V_REF V 0.uF _SHN V_IN GN GN U GN V_OUT_F V_OUT_S GN LT 0uF R 0k 0uF IN IN VOS_TRIM VOS_TRIM U N OPE OUT.V_REF R 0k 0uF IN IN VOS_TRIM VOS_TRIM U N OPE OUT 9 00pF
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EFM US Type- 0 W harger History oard Function Title Page EFM & User Interface oard Power Page Rev. escription 00 Prototype version. 0 Initial release version. VUS Voltage Regulator ebug MU ebug Misc. P
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DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2
SEGMENT LE ISPLY R MUX MUX MUX MUX R nf SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ U R xt P P P P P P P P MX MX ss SL S P P P P P P P P nf S SEG_SL SEG_S SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_I_SL_
AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
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PRIMRE Power mplifier Service Manual . Technical Description.. Error codes.. Bias djustment.. Schematics.. Technical Specifications. onfidential! This document is not allowed to show for third part without
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PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.
R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument
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3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)
NXP VKIT-SZV Table of ontents 0 LOK IGRM N NOTS 0 I/O Headers 0 Power/MU 0 Peripherals 0 US/OSM Revisions Rev escription esigner ate X Initial raft 00 Release 0/0/ X hanged MU to SZV 0// U T I O N : This
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ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B
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3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
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