Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.

Transcription

1 lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January, 0 Sheet of

2 Wi-Fi & U U HORNET_GP HORNET_GP GPIO GPIO HORNET_GP HORNET_GP HORNET_GP HORNET_GP HORNET_GP HORNET_GP GPIO GPIO HORNET_GP HORNET_GP HORNET_GP HORNET_GP R 0K R 0K U OE NT00 U OE NT00 0 SS SK TP SK TP TP R R R R R R TP GP HNSHKE 0K VV U 0 (SS/PINT0)P0 (P//PINT)P (P0//PINT)P (SLK/PINT)P (INT/IN0)PE VUS - + (XK/#TS)P REF (#HW)PE U_- U_+ R0 0K R R 00nF R R REF - + V_US TP U YSSR0 K USM TP TP USP V_US R 0uF 00nF J MIRO US TP USGN V - + I G URT_TX URT_RX HORNET_GP R R TP URT_TX URT_RX URT_TX TP URT_RX TP U I VL O V O VL I V THREE-STTE MXE URT_TX URT_RX R R RX TX TP URT_TX TP URT_RX 0 (RX/INT)P (TX/INT)P XTL XTL OS_IN OS_OUT R M 0pF YZ MHz 0pF WIFI_MOULE Wi-Fi Module HORNET_GP HORNET_GP HORNET_GP0 LE0 LE LE P_TX+ P_TX- P_RX+ P_RX- US+ US- HORNET_GP HORNET_GP0 LE0 LE LE R0 R0 R R P_TX+ P_TX- P_RX+ P_RX- US+ US- K S R FSMJH NP R K LE LUE LE WHITE USER UTTON LE YELLOW Q R 0K S0 V Wireless LE US LE IO LE ontrol V R0 K WN LE Q P0GN R K VV R K G LE RE VV S R0 K S TSSK-PL TP0 U_nRESET U 00nF U LVG0 (/PINT)P (PINT/O#O/)P 0 (PINT/O/O/)P (PINT/O0/O/#RTS)P (T/#O/)P (IP/LK0/O)P #RESET (IP/)P (O/#O)P (T0/O/0)P TmegaU-MU TmegaU Part of (S/INT)P (O0/SL/INT0)P0 (/TI)PF (/TO)PF (/TMS)PF (/TK)PF 0 ()PF (0)PF0 R00 R0 R NP NP IO IO IO0 IO IO IO VV S SL U_0 U_ U_ U_ U_ U_ SK HNSHKE RX TX U_nRESET These files are licensed under a reative ommons ttribution Share-like license, which allows for both personal and commercial derivative works, as long as they credit dog hunter LL and release their designs under the same license. The Linino software is also open-source. The source code is released under the GPL and the /++ microcontroller libraries are under the LGPL. IO R K R K Q S0 S0/S0 SS U LVG0 LE YELLOW LERX R K V Wi-Fi & U Size ocument Number Rev Yun ate: Thursday, January, 0 Sheet of

3 , micros & US Host pf V. V. uf.v V Y MHz R R R0 R K R0 R 0K 0K XSO XSI pf US_PWRE hipn U XSO XSI MSINS US_PWREN UP_RREF hipn SN RT RT RT0 S_V ontrolout0 RT RT RT RT 0 RT RT RT RT0 RT ontrolout P_OVRUR P_PWRUP 0 SN RT RT RT0 RT RT P_OVRUR P_PWRUP R R TP RT TP RT TP RT TP RT TP RT0 TP RT TP0 RT V R K R V. PWR_V R ONTROLOUT0 R R 0K R0 K R 0K S GQ P0GN + 0uF 0V V R NP P_PWR R R 0pF urrent Limiter MI00- J 0 00nF V U FULT EN VOUT GN TP P_PWR US uf.v JP T T M V LK VSS 0 T0 T x V.ML00NR micros TFN-X0-0X0-H GN GN US+ US- R K R K US_M US_P U0-MGL Part of US_M US_P P_M P_P P_M P_P P_M P_P R R TP P_M TP P_P U YSSR0 K V - + G TP US GN US signal line trace:.keep traces of US bus + and - the same length..chieve 0 ohm differential characteristic impedance..chieve ohm common characteristic impedance..maintain parallelism between + and -..o not route US.0 + and - over the power plane split..o not route US.0 + and - over the other high frequency signals..it is preferred to route US.0 + and - over ground layer..it is preferred to route US.0 + and - using single layer., micros & US Host Size ocument Number Rev Yun ate: Thursday, January, 0 Sheet of

4 Power Supply & Pin Headers P_RX+ P_RX- P_TX+ P_TX- R0 R R0 R R0 R R0 R 0 00nF 0 00nF.0V T R R T+ R T- R R+ R- R 00nF T L L K L L K RJ Ethernet RXT TXT N SH SH R R R R0 R SMJ SMJ U +V V GN V V J I P V P g00 PoE 0 POE_V TP + 0 0uF V TP TP POE_V V VV U_nRESET 0 MRM0 MRM0 MRM0 U_0 U_ U_ U_ U_ U_ NP N IOREF RESET V V GN@ GN@ 0 J N IOREF RESET V V GN GN J0 0 SK J J SL S REF GN 0 J (TX0) 0(RX0) SL S REF GN@ 0 0 REF IO IO IO IO0 IO IO HNSHKE SL S TX RX 0000 VV ISP V_US POE_V MRM0 0 MRM0 GN TP 0.uF.V 0 0uF.V V.uF.V VV TP.uF.V R 00K 00nF 0V EN TP R EN TP U0 EN I RT00 LX F/OUT GN TP L.uH. pf R0 K % R K % 0uF.V uf.v 0 uf.v V TP0 00nF.V V R0 LE GREEN Power LE Power Supply & Pin Headers Size ocument Number Rev Yun ate: Thursday, January, 0 Sheet of

5 I Power VV VV 00nF uf 00nF U UV UGN TmegaU-MU TmegaU Part of V GN UP V V V P EXP GN GN GN 00nF R VV VV 00nF 0 00nF V VV U V V V VV U V V GN NT00 GN NT00 00nF 00nF 00nF V U VL GN MXE U V V GN LVG0 V 00nF 00nF VV uf VV N V R.uF.V V. U uf V.uF V V 00nF V PV.uF VH VH R 00 R 0 <-- V_OUT --> VV U0-MGL.uF.V Part of V V PLL_V V_OUT --> PLL_VSS VSSH 0 PVSS V. 0.uF 00nF.uF H H H H HS HS HS HS HS HS Reference esigns RE PROVIE "S IS" N "WITH LL FULTS". rduino ISLIMS LL OTHER WRRNTIES, EXPRESS OR IMPLIE, REGRING PROUTS, INLUING UT NOT LIMITE TO, NY IMPLIE WRRNTIES OF MERHNTILITY OR FITNESS FOR PRTIULR PURPOSE. rduino may make changes to specifications and product descriptions at any time, without notice. The ustomer must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." rduino reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The product information on the Web Site or Materials is subject to change without notice. o not finalize a design with this information. "rduino" name and logo are trademarks registered by rduino S.r.l. in Italy, in the European Union and in other countries of the world. I Power Size ocument Number Rev ustom Yun ate: Thursday, January, 0 Sheet of