Reference Schematic for LAN9252-HBI-Multiplexed Mode

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1 Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM opper Mode Interface hennai LN-HI Multiplexed Mode TITLE oard LN ate: Friday, May, 0 Sheet of

2 POWER SUPPLY J PJ-00H ui Stack V_EXT SW 0MSQE &K /0.0R LMEGSN V_SW F V R 0uF V TP RE EN_ 0.uF V REGULTOR, ( V fixed when Rb=) U VIN VOUT ENLE TRIM _mp OKR-T/-W- GN R.0K % (Ra) R % (Rb) R E % 0uF 0.uF TP ORNGE V NP.uF V R K "V Present" hennai LN-HI Multiplexed Mode Power Supply oard LN ate: Friday, May, 0 Sheet of

3 V F /0.0R LMEGSN VTXRX VTX VTX Power Supply Filtering V VR F /0.0R LMEGSN Note:Place close to the I 0.uF VTXRX 0 0.uF V F /0.0R LMEGSN 0.uF Note:Place close to the I Low ESR VTX VTX VTXRX VTXRX V V VR F /0.0R LMEGSN 0.uF 0.uF 0.uF 0.uF 0 0.uF 0.uF 0.uF 0.uF uf 0pF 0.uF 0.uF Note: PIN _OSVSS need to connect hip Gnd. U 0 V R 0.0K /0W % 0.uF pf Y itizen merica HM-.000MJT pf.000mhz ppm V R.K % OSI OSO REG_EN RIS TEST/FXLOSEN I_SL I_S GPIO GPIO POWER RIS VTXRX VTXRX OSV OSI OSO OSVSS REG_EN TEST/FXLOSEN TESTMOE VIS V OS ISL/EESL/TK IS/EES/TMS OTHER SIGNLS VIO VIO VIO VIO VIO I FXSEN/FXS/FXLOS INT PORT0 INT PORT (Only for Lan) LINKTLE0/TO/LEPOL0/HIP_MOE0 LINKTLE/TI/LEPOL/HIP_MOE RUNLE/LEPOL/EPSIZE VR VR VR VTX VTX TXN TXP RXN RXP TXN TXP RXN RXP FXSEN/FXS/FXLOS GPIO 0 0 FXS/FXLOS TXN TXP RXN RXP TXN TXP RXN RXP FXS/FXLOS Reset KT LN GN hennai LN-HI Multiplexed Mode LN(Part) oard LN ate: Friday, May, 0 Sheet of

4 R/R_WR WR_EN S SYN/LTH SYN0/LTH0 U 0 SYN/LTH SYN/LTH0 /IGIO/GPI/GPO/MII_RX0 /IGIO/GPI/GPO/MII_RXV /LEHI/IGIO0/GPI0/GPO0/LINKTLE/MII_LINKPOL/LEPOL /LELO/OE_EXT/MII_LK R/R_WR/IGIO/GPI/GPO/MII_RX WR/EN/IGIO/GPI/GPO/MII_RX S/IGIO/GPI/GPO/MII_RX 0///IGIO/GPI/GPO/MII_RXER //IGIO/GPI/GPO/MII_TX/TX_SHIFT //IGIO/GPI/GPO/MII_TX/TX_SHIFT0 //IGIO/GPI/GPO/MII_TX //IGIO/GPI/GPO/MII_TX0 0/0/IGIO/GPI/GPO/MII_TXEN //LTH_IN/SK //IGIO/GPI/GPO/MII_MIO 0 //IGIO/GPI/GPO/MII_M //IGIO0/GPI0/GPO0/MII_RXLK 0 //OUTVLI/SS# //IGIO/GPI/GPO/MII_LINK //W_TRIG/SIO //SOF/SIO //EOF/SO/SIO 0/0/W_STTE/SI/SIO0 LEHI LELO R/R_WR WR_EN SYN/LTH SYN0/LTH0 J 0 0 So Interface Header TSW--0-G- Samtec LELO LEHI S LN HI Multiplexed Mode Note: In So, If R & WR is different pins then R need to connect with pin & WR need to connect with pin 0 If R & WR are same pin, then R_WR need to onnect with pin, and the EN need to connect with pin0 V Signals Functions = LINKTLE0/TO/LEPOL0/HIP_MOE0 GPIO =LINKTLE/TI/LEPOL/HIP_MOE GPIO = RUNLE/LEPOL/EPSIZE GPIO [0:] & LE_POL_Strap GPIO RUNLE Strap etails GPIO R 0.0K R 0.0K R K R 0.0K EPSIZE (GPIO) (RUNLE) 00[efault] 0 HIP_MOE[:0] GPIO[:0] 0 0 The LE is set as active high. Low EEPROM Size P/N = 0 K bits ( x ) through K bits (K x ); The LE is set as active low, EEPROM Size P/N = F K bits (K x ) through K bits (K x ) or Mbits (K x ) (LN only) [efault] HIP_MOE[:0] Strap etails Port escription Port 0 = PHY, Port = PHY RESERVE Port 0 = PHY, Port = PHY, Port = MII Port 0 = MII, Port = PHY, Port = PHY MOE PORT MOE RESERVE PORT OWNSTREM MOE (Port = ownstream) PORT UPSTREM MOE (Port0 = Upstream) FX_Mode_Strap_ & FXS/FXLOS FXS/FXLOS TEST/FXLOSEN FX_Los_Strap_ & Signal Ref.Voltage Function TEST/ FXLOSEN 0 R PORT0 = opper R PORT = opper R 0K 0K 0K Level of 0V Selects FX-S / copper twisted pair for ports 0 and further determined by FXS and FXS. R.K U 0 WP V V GN F I EEPROM S SL 0.uF V R K R0 I_S I_SL Higher size EEPROM - F used as efault Strap-EPSIZE(GPIO) is HIGH To use Lower size EEPROM - 0, Strap-EPSIZE(GPIO) to be changed to LOW K GPIO hennai LN-HI Multiplexed Mode LN(Part), Strap & EEPROM oard LN ate: Friday, May, 0 Sheet of

5 TXP TXN Port 0 R. /0W % R. /0W % R0. /0W % R. /0W % VTXRX R T Pulse J000NL T+ TXT T- XMIT 0 RJ & R Green = Link/T RXP RXN NP 0pF 0V % NP 0pF 0V % NP 0pF 0V % NP 0pF 0V % 0.0uF 0V 0% R+ RXT R- N HS GN GN GN RV MTG 000 pf kv YEL MTG & Note: apacitors through are optional for EMI purposes and are not populated on the LN evaluation board. These capacitors are required for operation in an EMI constrained environment. R RES0 Yellow = Speed N for EtherT TXP TXN Port R. /0W % R. /0W % R. /0W % R. /0W % VTXRX R T Pulse J000NL T+ TXT T- XMIT 0 RJ & R GPIO Green = Link/T RXP RXN NP 0 0pF 0V % NP 0pF 0V % NP 0pF 0V % NP 0pF 0V % 0.0uF 0V 0% R+ RXT R- N HS GN GN GN RV MTG 000 pf kv YEL MTG & Note: apacitors 0 through are optional for EMI purposes and are not populated on the LN evaluation board. These capacitors are required for operation in an EMI constrained environment. R0 RES0 Yellow = Speed N for EtherT hennai LN-HI Multiplexed Mode opper Mode Interface oard LN ate: Friday, May, 0 Sheet of

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