8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

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1 isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty of any kind. XTL Interface Power Supply.MHz TXO/OXO LE Status IN Recovery lock Sources IN IN_PLL,... V OUT... OUT Jtag US- I module uontroller SHEMTI, VEV REV Size ocument Number R e v lock iagram. ate: Friday, June, Sheet of

2 V J TI TK TO T ON V Place close to the UT pins P~ u u Place close to the UT pins P~ U E P P P J P P P F V F V G V K V F V G V G V H V H V F L L L P P P L L OSI OSI E OSI OUT F OUT OUT VO VV_ R SW RP.K* SW_IP_ XTL_OUT XTL_IN XTL_OUT XTL_IN XTL_OUT XTL_IN XTL_OUT XTL_IN I_ I_ TP TP TP u nf V V IN IN IN IN_PLL_POS IN_PLL_NEG IN_PLL_POS IN_PLL_NEG IN IN IN IN_PLL_POS IN_PLL_NEG IN_PLL_POS N IN_PLL_NEG P XTL_IN XTL_OUT XTL_IN XTL_OUT H H J J M N P E E P N M M K F G G H H G F F G G G M H H F IN IN IN IN_PLL_POS IN_PLL_NEG IN_PLL_POS IN_PLL_NEG N_ PLL_LF ISET_PLL V N_M PLL_LF ISET_PLL V XTL_IN XTL_OUT XTL_IN XTL_OUT VO VO O O OUT_POS OUT_NEG OUT_POS OUT_NEG OUT_POS OUT_NEG VO O PLL_LF PLL_LF V V INT_REQ I_S I_ I_ I_SL TO T TK TI I I I T_LOK F F J J H J H L L J K L N P J K P M M P P K L L K E G E J E E F OUT_POS OUT_NEG OUT_POS OUT_NEG OUT_POS OUT_NEG INT_REQ I_S I_ I_ I_SL TO T TK TI PLL_LOK O OUT_POS OUT_NEG OUT_POS OUT_NEG OUT_POS OUT_NEG I_S I_SL PLL_LOK TP I_S I_SL VO JP O Place the bypass caps close to the UT power/ground pins I Test Point TP ITV J H K K H K F E J J K K K L L L L M M M M M M N N N N P N N N J IN_PLL_POS TP IN_PLL_POS TP TP TP TP TP TP SHEMTI, V EV REV Size ocument Number Rev ustom V. ate: Friday, June, Sheet of

3 J IN VV_ R TP IN Series termination resistors close to output driver R OUT OUT TP J OUT RE t OUTPUT SM's R VV_ R VV_ R R R R R R J IN R TP IN OUT nout OUT R R nout OUT R R nout R R R R VV_ VV_ IN J R TP IN OUT R R R R J IN_PLL_P lose to I pins VV_ R R IN_PLL_POS IN_PLL_POS OUT_POS OUT_NEG OUT_POS lose to SM OUT_NEG VV_ R R R R OUT_P R OUT_N J OUT_P OUT_N J OUT_POS OUT_NEG OUT_POS lose to SM OUT_NEG VV_ R R R R OUT_P R OUT_N OUT_P J J OUT_N R J IN_PLL_N R R R R IN_PLL_NEG IN_PLL_NEG lose to SM VV_ J IN_PLL_P VV_ OUT_POS OUT_NEG OUT_POS OUT_NEG R R OUT_P R OUT_N OUT_P J J OUT_N R R R R IN_PLL_POS IN_PLL_POS IN_PLL_N J R R R R R IN_PLL_NEG IN_PLL_NEG SM's for input can be either EN LUNH or STRIGHT depends on which way save space. T during layout SHEMTI, V EV REV Size ocument Number Rev ustom V_IO_Termination. Friday, June, ate: Sheet of

4 .MHz, TXO or OXO ( Place close to the UT) U MLF.MHz OXO_Power u OXO_Power u N V OUT V N Tri-state_Enable N N N N N OUT U M_ TXO R TXO R J R MHz XTL Interface (Place close to the UT and Put xtals on same layer as G pads, shorter trace length, no stubs). MHz ) locks and frequently switched signals should not be routed close to the crystals. ) igital signals should not be routed directly under the crystal or XTLn_IN/OUT pins. ) Keep the crystal bond pads and trace width to the XTLn_IN/OUT pins as small as possible. ) ll metal layers in the P are recommended to be removed under the XTLn_OUT ball, crystal pad and associated trace. ) It is recommended to protect crystal traces with ground traces and guard rings. X XTL_OUT XTL_IN. MHz X XTL_OUT XTL_IN XTL_OUT XTL_IN XTL_OUT XTL_IN XTL_OUT XTL_IN XTL_OUT XTL_IN R JP VV_ V_OXO L LMSN SW SW_PUSHUTTON VV_ U RTX L LMSN u u R K N N V N N N V FILTER RF OUT N R OXO_Power OXO_Power VV_ TP U IUT_SUPPLY RF_OUTPUT N N N N Stratum E OXO R OXO_Power R R OXO R R XO/SM option OSI J VUS - + US PORT R PF L RE LE R R.K XTIN PF Y MHz XTOUT R K V_V V_US R K V R V R U VOUT USM USP OUT# XTIN XTOUT RESET# EES EESK EET V V V u.u VIO VIO V_US TK/SK TI/O TO/I /S GPIOL GPIOL GPIOL GPIOL GPIOH GPIOH GPIOH GPIOH SI/WU UNUSE UNUSE UNUSE UNUSE UNUSE UNUSE UNUSE UNUSE UNUSE UNUSE UNUSE UNUSE SI/WU R K R K V_US VV_ SL S R.K VV_ V_US L Green LE R R R.K R R R SL I_SL SL I_SL I_S US to I JP Header_Pin I_SL I_S U H/SO TEST ft_chip PWREN# SL R UF H/SO JP S I_S S Header_Pin Indicator VV_ VV_ PLL_LOK PLL_LOK U H/SO R K L SL S J ardvark I/I Host dapter SHEMTI, V EV REV Size ocument Number Rev ustom V_ontrol. ate: Friday, June, Sheet of

5 U VREG_LTEQ_. VIN VOUT R JP VV_ VV_ (VV_ is used for the V UT and VV_ is for the rest of the board circuits. We are not suggesting a dedicated LO for the V with this reference design, this is just convenient for the test.) J VV V V u R u SHN SENSE u R R L J GR-G POWER_SOKET V u U VREG_LTEQ_. VIN VOUT SHN SENSE R RE uf u JP R VV_ VV_ R L (Place caps close to and accross power and ground pins) VV_ L JP V nalog Power J V_OXO GR-G J V_OXO GR-G V_OXO u R JP R LMSN L LMSN V V u V igital Power u JP L LMSN VO VO V igital Output Power u R O JP L R u V nalog OUTPUT Power.u.u SHEMTI, V EV REV Size ocument Number Rev Power/. ate: Friday, June, Sheet of