ICS97U V Wide Range Frequency Clock Driver. Pin Configuration. Block Diagram. Integrated Circuit Systems, Inc. 52-Ball BGA.

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1 Integrated Circuit Systems, Inc. ICS97U V Wide Range Frequency Clock river Recommended Application: R2 Memory Modules / Zero elay Board Fan Out Provides complete R IMM logic solution with ICSSSTU32864 Product escription/features: Low skew, low jitter PLL clock driver 1 to 10 differential clock distribution (SSTL_18) Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Auto P when input signal is at a certain logic state Switching Characteristics: Period jitter: 40ps Half-period jitter: 60ps CYCLE - CYCLE jitter 40ps OUTPUT - OUTPUT skew: 40ps Pin Configuration A B C E F G H J K Ball BGA Top View A CLKT1 CLKT0 CLKC0 CLKC5 CLKT5 CLKT6 B CLKC1 CLKC6 C CLKC2 NB NB CLKC7 CLKT2 OS CLKT7 E CLK_INT NB NB FB_INT F CLK_INC NB NB OE FB_INC G A FB_OUTC H AV NB NB FB_OUTT J CLKT3 CLKT8 K CLKC3 CLKC4 CLKT4 CLKT9 CLKC9 CLKC8 Block iagram CLKT0 OE L* or OE CLKC0 OS AV Powerdown Control and Test Logic L* L*, OS or OE PLL bypass CLKT1 CLKC1 CLKT2 CLKC2 CLKC1 CLKT1 CLKT0 CLKC0 CLKC5 CLKT5 CLKT6 CLKC CLK_INT CLK_INC 10K-100k FB_INT FB_INC PLL * The Logic etect (L) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 FB_OUTT CLKC2 CLKT2 CLK_INT CLK_INC A AV 1 10 ICS97U CLKT3 CLKC3 CLKC4 CLKT4 CLKT9 CLKC9 CLKC8 CLKT8 40-Pin MLF CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT OE OS FB_OUTC

2 Pin escriptions Terminal Name A Analog Ground escription Electrical Characteristics Ground AV CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC Analog power Clock input with a (10K-100K Ohm) pulldown resistor Complentary clock input with a (10K-100K Ohm) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output 1.8 V nominal ifferential input ifferential input ifferential input ifferential input ifferential output ifferential output O E Output Enable (Asynchronous) LVCMOS input OS Output Select (tied to or Ground V ) LVCMOS input Q Ground V Q CLKT[0:9] CLKC[0:9] NB Logic and output power Clock outputs Complementary clock outputs No ball 1.8V nominal ifferential outputs ifferential outputs The PLL clock buffer, ICS97U877, is designed for a V Q of 1.8 V, a AV of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF. ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AV). When OE is low, the outputs (except FB_OUTT/ FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to or V Q. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AV is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time t STAB. The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97U877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97U877 is characterized for operation from 0 C to 70 C. 2

3 Function Table AV OE OS Inputs CLK_INT CLK_INT CLKT CLKC Outputs FB_OUTT FB_OUTC PLL H L H L H L H Bypassed/Off H H L H L H L Bypassed/Off L H L H * L(Z) * L(Z) L H Bypassed/Off L L H L *L(Z), CLKT7 active *L(Z), CLKC7 active H L Bypassed/Off 1.8V(nom) L H L H * L(Z) * L(Z) L H On 1.8V(nom) L L H L *L(Z), CLKT7 active *L(Z), CLKC7 active H L On 1.8V(nom) H L H L H L H On 1.8V(nom) H H L H L H L On 1.8V(nom) L L * L(Z) * L(Z) * L(Z) * L(Z) Off 1.8V(nom) H H Reserved *L(Z) means the outputs are disabled to a low stated meeting the I OL limit. 3

4 Absolute Maximum Ratings Supply Voltage ( & AV) V to 2.5V Logic Inputs V to V Q + 0.5V Ambient Operating Temperature C to +70 C Storage Temperature C to +150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0-70 C; Supply Voltage A, = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONITIONS MIN TYP MA UNITS Input High Current (CLK_INT, CLK_INC) I IH V I = V Q or ±250 µa Input Low Current (OE, OS, FB_INT, FB_INC) I IL V I = V Q or ±10 µa Output isabled Low I OL OE = L, V OL = 100mV 100 µa Current Operating Supply I 1.8 C L = 270MHz 300 ma Current I L C L = 0pf 500 µa Input Clamp Voltage V IK V Q = 1.7V Iin = -18mA -1.2 V High-level output voltage V OH I OH = -100 µa V Q V I OH = -9 ma V Low-level output voltage V OL I OL =100 µa V I OL =9 ma 0.6 V Input Capacitance 1 C IN V I = or V Q 2 3 pf Output Capacitance 1 C OUT V OUT = or V Q 2 3 pf 1 Guaranteed by design, not 100% tested in production. 4

5 Recommended Operating Condition (see note1) T A = 0-70 C; Supply Voltage AV, = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONITIONS MIN TYP MA UNITS Supply Voltage V Q, A V V CLK_INT, CLK_INC, FB_INC, Low level input voltage V IL FB_INT 0.35 x V Q V OE, OS 0.35 x V Q V CLK_INT, CLK_INC, FB_INC, High level input voltage V IH FB_INT 0.65 x V Q V OE, OS 0.65 x V Q V C input signal voltage (note 2) V IN -0.3 V Q V ifferential input signal voltage (note 3) C - CLK_INT, CLK_INC, FB_INC, FB_INT AC - CLK_INT, CLK_INC, FB_INC, FB_INT Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. C input signal voltage specifies the allowable C execution of differential input. 3. ifferential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. ifferential cross-point voltage is expected to track variations of V Q and is the voltage at which the differential signal must be crossing. 0.3 V Q V 0.6 V Q V Output differential crossvoltage (note 4) V O V Q / V Q / V Input differential crossvoltage (note 4) V I V Q / V /2 V Q V High level output current I OH -9 ma Low level output current I OL 9 ma Operating free-air temperature V I T A 0 70 C 5

6 Timing Requirements T A = 0-70 C Supply Voltage AV, = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONITIONS MIN MA UNITS Max clock frequency freq op 25 C MHz Application Frequency Range freq App 25 C MHz Input clock duty cycle d tin % CLK stabilization T STAB 15 µs Switching Characteristics 1 T A = 0-70 C Supply Voltage AV, = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONITION MIN TYP MA UNITS Output enable time t en OE to any output ns Output disable time t dis OE to any output ns Period jitter t jit (per) ps Half-period jitter t jit(hper) ps Input slew rate SLr1(i) Input Clock v/ns Output Enable (OE), (OS) 0.5 v/ns Output clock slew rate SLr1(o) v/ns Cycle-to-cycle period jitter t jit(cc+) 0 40 ps t jit(cc-) 0-40 ps ynamic Phase Offset t ( )dyn ps Static Phase Offset 2 t SPO ps Output to Output Skew t skew 40 ps SSC modulation frequency khz SSC clock input frequency deviation % PLL Loop bandwidth (-3 db from unity gain) 2.0 MHz Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design. 6

7 Parameter Measurement Information V V(CLKC) V(CLKC) ICS97U877 Figure 1. IBIS Model Output Load V/2 ICS97U877 C=10pF- SCOPE Z=60Ω R=10Ω Z=50Ω Z = 2.97" Z = 120Ω R = 1MΩ C = 1 pf V(TT) Z=60Ω R=10Ω Z=50Ω Z = 2.97" C=10pF R = 1MΩ C = 1 pf V(TT) Note: V TT = -V/2 Figure 2. Output Load Test Circuit Y, FB_OUTC Y, FB_OUTT tc(n) tc(n+1) tjit(cc) =tc(n) ±tc(n+1) Figure 3. Cycle-to-Cycle Jitter 7

8 Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t ( ) n n=n 1 t ( ) n t ( ) = N (N is a large number of samples) Figure 4. Static Phase Offset t ( ) n+1 Y # Y Y, FB_OUTC Y, FB_OUTT t (skew) Figure 5. Output Skew Y, FB_OUTC Y, FB_OUTT t C(n) Y, FB_OUTC Y, FB_OUTT t (jit_per) = 1 f O t c(n) - 1 f O Figure 6. Period Jitter 8

9 Parameter Measurement Information Y, FB_OUTC Y, FB_OUTT t jit(hper_n) tjit(hper_n+1) 1 fo t jit(hper) = t jit(hper_n) - 1 2xf O Figure 7. Half-Period Jitter 80% 80% VI, VO Clock Inputs and Outputs 20% tslr tslf 20% Figure 8. Input and Output Slew Rates 9

10 CK CK FBIN FBIN t ( ) SSC OFF SSC ON t ( ) SSC OFF SSC ON t ( )dyn t ( )dyn t ( )dyn t ( )dyn Figure 9. ynamic Phase Offset 50% OE t en 50% Y Y/ Y Y OE 50% Y t dis Y 50 % Figure 10. Time delay between OE and Clock Output (Y, Y) 10

11 Figure 11. AV Filtering - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to A trace & connect trace to one via (farthest from PLL). - Recommended bead: Fair-Rite P/N Y0 or equivalent (0.8 Ohm C max, MHz). 11

12 A1 Seating Plane C T b REF Numeric esignations for Horizontal Grid A B C Alpha esignations for Vertical Grid (Letters I, O, Q & S not used) d TYP 1 TOP VIEW - e - TYP E h TYP 0.12 C c REF E1 - e - TYP ALL IMENSIONS IN MILLIMETERS BALL GRI Max. REF. IMENSIONS E T e HORIZ VERT TOTAL d h 1 E1 b c Min/Max Min/Max Min/Max 7.00 Bsc 4.50 Bsc 0.86/ Bsc / / Bsc 3.25 Bsc ** Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEEC Publication 95, MO-205*, MO-225** Ordering Information 97U877yHLF-T Example: y H LF- T esignation for tape and reel packaging Lead Free (Optional) Package Type H = BGA Revision esignator (will not correlate with datasheet revision) evice Type 12

13 Index Area 1 2 E N Top View Seating Plane Anvil Singulation or A1 Sawn Singulation A3 L E2 E2 2 (N-1)x e (Ref.) N (Ref.) N & NE Even 1 2 e (Typ.) 2 If N & NE are Even (NE -1)x e (Ref.) b A 0.08 C e (Ref.) N & NE Odd C Thermal Base Ordering Information 97U877yKLF-T THERMALLY ENHANCE, VERY THIN, FINE PITCH QUA FLAT / NO LEA PLASTIC PACKAGE ALL IMENSIONS IN MILLIMETERS N 40 SYMBOL MIN. MA. N 10 A N E 10 A x E BASIC 6.00 x 6.00 A Reference 2 MIN. / MA / 3.05 b E2 MIN. / MA / 3.05 e 0.50 BASIC L MIN. / MA / MIN. / MA. E2 MIN. / MA. SPECIAL NON-JEEC ALL IM. SAME ECEPT AS BELOW: 4.35 / / 5.35 Source Reference: MLF2 SER Example: y K LF- T esignation for tape and reel packaging Lead Free (Optional) Package Type K = MLF Revision esignator (will not correlate with datasheet revision) evice Type 13

ICSSSTUB32871A. 27-Bit Registered Buffer for DDR2. Integrated Circuit Systems, Inc. Pin Configuration. 96 Ball BGA (Top View)

ICSSSTUB32871A. 27-Bit Registered Buffer for DDR2. Integrated Circuit Systems, Inc. Pin Configuration. 96 Ball BGA (Top View) Integrated Circuit Systems, Inc. ICSSSTUB32871A 27-Bit Registered Buffer for R2 Recommended Application: R2 Memory Modules Provides complete R IMM solution with ICS98ULPA877A, ICS97ULP877, or ITCSPUA877A