Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header

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1 esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use of these schematics. 0 OVER Size ocument Number Rev XPLORER. ate: Monday, March, 0 Sheet of

2 GPIO0[] USER_SWITH RESET SWITH V R 0K SW SWT-G 00nF USER SWITH V R 0K USER_SWITH SW SWT-G 00nF S_0 S_ S_ S_ S_SK S_M V U J H S_T0 SPIFI_SK J S_T SPIFI_S K S_T SPIFI_MOSI K S_T SPIFI_MISO K S_LK SPIFI_SIO S_M SPIFI_SIO LP0_0 FLSH E SPIFI_SK SPIFI_S SPIFI_MOSI SPIFI_MISO SPIFI_SIO SPIFI_SIO V + uf/.v S R S_ S_ S_M S_SK S_0 S_ J T /T M V LK VSS T0 T SH00 SHL SHL SHL SHL SHL SHL SHL V 0 00nF SPIFI_MOSI SPIFI_MISO SPIFI_SIO SPIFI_SIO IO_0 IO_ IO_ IO_ U V I(IO0) O(IO) WP#/IO HOL#(IO) LK S# SPIFI_SK SPIFI_S S_0 S_ S_ S_ S_M R R R R R 0K 0K 0K 0K 0K SFL0P0XMFI0 GPIO[] S_M VIN_V US_V VIN_V US_V POWER VIN_V U PMEG00EV V US_V U VIN VOUT + 0uF/0V VO NXZ V + 0uF/0V LE R 0 V F LMHG0SN F LMHG0SN V 0nF nf E E F F0 K U V VSS VREG VREG VREG VIO VIO LP0_0 WKEUP0 VSSIO_ VSSIO_ VSSIO_ VSSIO_ VSSIO_ VSSIO_ G J J WKEUP0 TP 00nF V 0 00nF 00nF 00nF 00nF 0 FLSH,S R,POWER Size ocument Number Rev XPLORER. ate: Monday, March, 0 Sheet of

3 E_RX0 E_RX E_RS_V K G H ENET_RX0 ENET_RX ENET_RS UE ENET_TX_EN ENET_TX_LK ENET_TX ENET_TX0 ENET_MIO ENET_M LP0_0 G K K0 J0 H0 G0 V E_TXEN E_TX_LK E_TX E_TX0 E_MIO E_M E_RXER TP F LMPGSN ETHERNET 0uF 00nF 00nF V GPIO0[] E_TX0 E_MIO GPIO[0] GPIO0[] GPIO0[] GPIO0[] ETH_RST# E_TX0 E_MIO E_M E_RS_V E_RX0 E_TXEN E_RX R 0K R 0K 0uF 00nF V R 0k E_TX0 E_TX E_TXEN E_RX0 E_RX E_RS_V E_RXER E_MIO E_M V R 0K ETH_RST# NET_T NET_SPEE U TX0 TX TXEN RX0/MOE0 RX/MOE LN0 0 RS_V/MOE RXER/PHY0 MIO M nint/reflk0 nrst LE/REGOFF LE/nINTSEL XTLLKIN V V VIO VR XTL RIS 00nF 00nF R R 00nF R R.R.R 00nF.R.R TXP TXN RXP RXN 0 T+ T- R+ R- 0 00nF pf pf pf pf NL V 00nF NET_T NET_SPEE R 0 R0 0 0 J V RJ/MG X E_TX_LK R K V Y V E/ V 0nF OUT X SFL-0MHZ-L-T ETHERNET ROUTING GUIELINES =>Keep the trace length difference between TX+ and TX- (or RX+ and RX-) in 00 mils. => Keep RX+/- signal on the top layer, the RX+/- signal should avoid any vias, if possible. void right angle signal trace. =>The crystal/oscillator clock and the switching noise from digital signals should be far away from TX+/-, RX+/- pairs. =>Keep TX, RX differential signals running symmetric, equal length, and closely. The trace spacing between TX+ and TXor between RX+ and RX- pair should be in ~ 0 mils. The better spacing between TX+/- and RX+/- pairs should be larger than 00 mils =>The trace length from LN0 to the transformer should not be longer than inches, keep the trace as straight as possible, and keep it parallel for differential pairs. =>The termination resistors.o and capacitors of TX± and RX± pairs should be placed near the transformer side and should be shorter than 00 mils. 0 ETHERNET Size ocument Number Rev XPLORER. ate: Monday, March, 0 Sheet of

4 U OE GPIO0[] U_RST V F0 R LMHG0SN V_udio UG LP0_0 V R K V R0 K I0_S I0_SL IS0_RX_WS IS0_RX_SK IS0_RX_S IS0_TX_S IS0_TX_WS IS0_TX_SK I0_S I0_SL E G H J G F Y V U_RST IS_TX_S IS_TX_WS IS_TX_SK IS_RX_S IS_RX_WS IS_RX_SK I0_S I0_SL I0_S I0_SL IS_RX_WS IS_RX_SK IS_RX_S IS_TX_S IS_TX_WS IS_TX_SK E/ OUT SFL-.MHZ-L-T V V 0uF.uF/V 0 00nF K VP RESET SYSLK TI VOUTLHP WSI KI VREF(HP) TO WSO VOUTR KO LMOE VOUTL LT/S LLOK/SL VINL 0 0 VN V(HP) U0 VSS(HP) V() VREF EXP_P SEL_L_II VSS() V() VOUTRHP VSS() RT VINR VINM 0 V VSS U VINR VINM VINL V US_V R R0 R 0uF R0 K 00nF R NP R0, R uf/.v uf/.v 0uF R 0 R 0 00nF 0 0uF VOUTRHP VOUTLHP VREFHP VOUTR VOUTL VINL VINR VINM J 00nF SJ--SMT 0uF 00nF VOUTR VOUTL TP VREFHP VOUTRHP VOUTLHP TP J SJ--SMT 0 UIO Size ocument Number Rev XPLORER. ate: Monday, March, 0 Sheet of

5 R0 0K R 0K US0_PWR_EN US0_PWR_FULT US_PWR_FULT US_PWR_EN US SETION US Power enable and fault pins are monitored/controlled using GPIO. R 0K US_VUS R 0K US_M U EN FLG_ FLG_ EN OUT_ OUT_ LM-H IN US_V + and - are ifferential Pair with 0 ohm impedance. R US_P R U US_V F PMEG00EV U PMEG00EV LMHG0SN F LMHG0SN US_V SHL SHL VUS M P I US0_VUS US_VUS J ZX--P LMHG0SN V F F US0_V K R US0_PWR_EN US0_PWR_FULT US0_P US0_M US0_VUS US0_I LMHG0SN F F G G E E E F U LP0_0 US0_V US_M US_P US_V GPIO[] GPIO[] GPIO[] GPIO[] US0_VV_RIVER US_M US0_VV US_P US0_VSS_TERM US_VUS US0_VSS_REF US0_RREF US0_PWR_EN US0_PWR_FULT US0_P US0_M US0_VUS US0_I US_M US_P US_V US_PWR_EN US_PWR_FULT US_VUS US0_PWR_FULT E0 E 0 US_M US_P US_VUS pf R K 00nF F LMHG0SN J US0_VUS US0_M US0_P + and - are ifferential Pair with 0 ohm impedance. US0_I SHL SHL VUS M P I ZX--P R K SHL SHL pf R K SHL SHL R K US0_PWR_EN /0 HOST/EVIE US_PWR_EN HOST/EVIE US ROUTING GUIELINES F NOTE:- When both US0 and US are in Host mode external V to be given to J pin. =>Route US trace pairs together [ M & P]. =>o not route US traces under crystals, oscillators,magnetic devices or Is that use and/or duplicate clocks. =>Route high-speed US signals using a minimum of vias and corners. =>Use 0-mil minimum spacing between high-speed US signal pairs and other signal traces for optimal signal quality. LMHG0SN 0 US Size ocument Number Rev XPLORER. ate: Monday, March, 0 Sheet of

6 TP TRST V V R 0K U GEN VT SWIO/TMS TRST RTX N/TI G TMS/SWIO SWLK/TLK H TI RTX SWO/TO H TK/SWLK RT_LRM TO/SWO JTG J RESET LP0_0 0 ON0 XTL XTL SWIO/TMS SWLK/TLK SWO/TO N/TI VT RTX RTX RT_LRM XTL XTL TP Y XTL pf pf XTL R R 00K 00K M-.000MHZ--T RTX pf Y S0-.KHZ-T RTX pf GPIO0[] GPIO0[] GPIO[] GPIO[0] OOT SELET SWITH V R 00K R 00K To oot from Quad SPI flash configure boot switch to 0 J IN IN IN IN HS-0 OUT OUT OUT OUT R 0K R 0K R 0K R 0K GPIO[] GPIO[] GPIO[] GPIO[0] GPIO0[] GPIO0[] GPIO0[] VIN_V US_V GPIO0[] GPIO0[] E_TX0 E_MIO GPIO0[] US_M US_P GPIO[] GPIO[] GPIO[] GPIO[] GPIO[] GPIO[0] GPIO0[] GPIO0[] GPIO0[] VIN_V US_V GPIO0[] GPIO0[] N_R N_T GPIO0[] US_M US_P GPIO[] GPIO[] N IS MULTIPLEXE WITH ETHERNET LINKY LE GPIO[] GPIO[] V R 0 LE LE R 0 GPIO0[] GPIO0[] GPIO0[] GPIO[] GPIO[] GPIO[] GPIO[] GPIO[] GPIO[] E H 0 H F UF GPIO0[] GP_LKIN GPIO0[] U0_RX GPIO0[] U0_TX U_TX U_RX GPIO[] GPIO[] GPIO[] GPIO[] GPIO[] GPIO[] GPIO[] GPIO0[] GPIO0[] GPIO[] GPIO[] GPIO[0] 0_0 SSP_MISO 0_ SSP_MOSI 0_ SSP_SK 0_ SSP_SSEL I_SL I_S LP0_0 H F F H J G F K K 0 J J K J U0_RX U0_TX U_TX U_RX GPIO[] GPIO[] GPIO0[] GPIO0[] GPIO[] GPIO[0] MISO MOSI SK SSEL I_SL I_S TP VIN_V VT MOSI MISO SK SSEL U0_TX U0_RX GPIO[] GPIO[] U_TX U_RX GPIO[] GPIO0[] GPIO0[] GPIO[] GPIO0[] GPIO0[] GPIO0[] 0 0 J X_L US_M US_P V US_V US_M US_P N_RX N_TX I_S I_SL GPIO0[] GPIO[0] GPIO[] GPIO0[] GPIO[] GPIO[] GPIO[] GPIO[] GPIO[] GPIO[0] GPIO0[] GPIO[] 0 0 J0 X_R R N_RX R N_TX N_R N_T NOTE: * N cannot be used when Ethernet is enabled. * Load R and R to use N * lines V tolerant 0 JTG,OOT SW,LINKY LE,HEER Size ocument Number Rev XPLORER. ate: Monday, March, 0 Sheet of