Virtex 5 FF1760 DUT. Differential SMA Clocks 2X D. Single Ended Socket Clocks 2X. Upstream Connector. Upstream. Power Bus and Switches 5V

Size: px
Start display at page:

Download "Virtex 5 FF1760 DUT. Differential SMA Clocks 2X D. Single Ended Socket Clocks 2X. Upstream Connector. Upstream. Power Bus and Switches 5V"

Transcription

1 PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE -0 Power us and Switches V OR V JK RIK VINT VINT JK VO VO JK Virtex FF0 UT PGE Switches User Reset Program PGE ONE INIT LE LE PGE VUX VV VUX JK VV onfiguration Platform Flash SPI PI JTG System ce ownstream ownstream onnector Single Ended Socket locks X ifferential SM locks X User LE's LL UT I/O TEST POINTS PGE - PGE - PGE PGE PGE PGE SH P/N 0 RT P/N 0 F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER LOK IGRM ate: --00_0: Size: 0 rawn y

2 V J H-X V_EN V_TMP PN0-0S-.S() PN-0P-.S() SYSTEM E UPSTREM TK TO TI TMS TMS OWNSTREM_TI TO TK 0 P P PN0-S-.S() PN-P-.S() UPSTREM ONNETORS UPSTREM_IN OUT_USY ONE ONE LK LK OUT_USY RWR_# PROG PROG INIT INIT VO_0 LK Termination R 00 /W R 00 /W FX_M0 FX_M FX_M S_# 0 0 P P OWNSTREM ONFIG J _IN 0 H-X -: SERIL -: PRLLEL V R0 0 /0W ON_OR_TO J H-X JTG JUMPER ON OR JTG HIN SELETION PROM JTG -: Enable -: isable PROM_TO TI J H-X FPG JTG -: Enable -: isable FPG_TO ON_OR_TO FPG_TI -: SERIL HINING TO NEXT OR -: TERMINTION OF LST OR IN THE HIN TEST POINTS J J J J SYSTEM E OWNSTREM OWNSTREM ONNETORS FLYING WIRE ONFIGURTION PORT INIT LE ONE LE USER LE'S SWITHES VO_0 R.K /W R.K /W R.K /W VO_0 V J S_# TI PROG 0 TO INIT TK ONE TMS OUT_USY RWR_# HSWP_EN LK 0 _IN 0 0 FX_M FX_M FX_M0 0 0 H-X M M M0 R.K /W INIT VO_0 R.K /W V LE-GRN-SMT R 0 /W S Q VO_0 ONE R 0 /W V LE-GRN-SMT R 0 /W S Q LE-GRN-SMT LE-GRN-SMT UT UT UT UT UT UT UT R R R R00 R0 R0 R /W /W /W /W /W /W /W S LE-GRN-SMT R0 00 /W S LE-GRN-SMT S LE-GRN-SMT R0 00 /W S LE-GRN-SMT S LE-GRN-SMT R0 00 /W S LE-GRN-SMT UT S LE-GRN-SMT R0 00 /W S LE-GRN-SMT UT S UT LE-GRN-SMT R 00 /W S LE-GRN-SMT UT UT S S LE-GRN-SMT R 00 /W LE-GRN-SMT UT 0 UT S0 LE-GRN-SMT R0 00 /W S LE-GRN-SMT UT UT R0 00 /W S R0 00 /W S ate: SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER Size: --00_:0 PROG UT VO_ R.K /W R.K /W rawn y Program USR Reset SH P/N 0 RT P/N 0 F P/N 00 IN ONN, PORTS, STTUS LES, SWITHES SW EVQ-L0K SW EVQ-L0K 0

3 XX XX IN OUT GN VO_0 VO_ VO_0 V VO_0 VV VO_0 EN_EXT_SEL REV_SEL0_ REV_SEL_ 0 VO_0 GN _ VINT GN VO _0 VO_ GN _ VJ_ GN_ TO_ TMS_ TK_0 TI GN VINT E LK_ OE/RESET EO 0 LKOUT_ VO_ GN_ F USY_ VINT GN I_ GN I_0 OUTS OUTF IN U_ U_ U_ U_ U_ U_ U0_ U_ T_IN LOK SELET T_OUT V HOL GN WRITE VV 0 0 V0 V VPP VQ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q WE WP V RST OE E WIT LK RFU VSS0 VSS VSS --00_0: ate: Size: rawn y VO_0 VO_0 TO_0 _OUT_USY_0 TI_0 TMS_0 M_0 M_0 M0_0 TK_0 R_FUSE_0 RSV RWR 0 S 0 INIT 0 LK_0 ONE_0 _IN_0 HSWPEN_0 PROGRM 0 VTT_0 VREFN_0 VREFP_0 VN_0 VP_0 VSS_0 V_0 XN_0 XP_0 FF0 NK 0 SPI INTERFE SPI INTERFE NOTE: MOE SPI INTERFE (OPTIONL) PROM EOMPRESION ONFIGURTION PROM -: PRLLEL PI INTERFE (SPI_MOSI) (FS0_#) SYSTEM MONITOR SUPPLY -: SERIL -: FILTERE VUX -: V FROM HR -: FILTERE POWER -: FIXE POWER SUPPLY -: FIXE POWER SUPPLY -: VREFIN FROM HR VO_, VO_, N VO_ MUST E TIE TOGETHER FOR PROPER OPERTION (FS0_#) (SPI_MOSI) PRLLEL LE ONNETOR VTT Supply FPG NK0 ONFIGURTION UT 0 J H-X G0 L H H G F F0 H G E0 V R0 T0 U F T R T T R Y Y U SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 RT P/N 0 F P/N 00 SH P/N 0 ONFIGURTION R.K /W FLSH_OE_# VO_ /W.K R /W.K R /W.K R 0 J -0 _IN UT U JSFP0T VO_ F HZ00E0R-0 UT UT 0 VSS VREF_P VSS V_0 V 0.0UF 0.0UF V UT UT FLSH_ FLSH_ UT UT 0 U0 MP-VMFG H-X J U MX0 INIT PROM_OE 00NF V YV R0 0 /0W 00NF V YV 0 0.UF V 0 0.UF V 0 0.UF V 00 0.UF V 0.UF V 0.UF V 0.UF V 0.UF V 0.UF V 0.UF V V 0.UF 0.UF V R.K /W R.K /W R0.K /W VTT 00 J H-X R0.K /W VREFOUTV VREFOUTV VREF_P_R HZ00E0R-0 F VO_0 V H-X J H-X J0 VSS UF V V 0.0UF J H-X U XFP-VOG 0-0 J J H-X EN_EXT_SEL_# REV_SEL0 REV_SEL J H-X PROM_LKOUT PROM_LK PROM_0 VJ_PROM J H-X VO_PROM VINT_PROM TI PROG OUT_USY J H-X _IN 0 TK TMS PROM_TO ONE LK.UF 0V TNT INIT TI TO TK TMS UT UT 0 UT 0 UT 0 0 FLSH_VPP 0 UT 0.UF 0V TNT 0V 0UF.UF 0V 0.0UF V LK VO_ UT IN LK UT 0 VUX VV U REF0IZT VSS VREFINV VREF_P /W.K R V 0.0UF R0 K /W R0 K /W R 00 /W /W 00 R R NP VP FPG_TO OUT_USY FPG_TI TMS M M M0 TK RSV INIT LK ONE _IN HSWP_EN PROG VTT XN XP SM_VN SM_VP RFUSE RWR_# S_# VN UT UT UT R.K /W

4 VO_ U VO_ U VO_ 0UF 0V TNT 0 0V.UF 0V 0.UF V 0.0UF J VO_ E VO_ FF0 NK IO_L0P R IO_L0N R IO_LP M IO_LN N IO_LP P IO_LN 0_ P IO_LP P IO_LN R IO_LP N IO_LN_VREF_0 P IO_LP N IO_LN P IO_LP N IO_LN M IO_LP N IO_LN 0_ P IO_LP P0 IO_LN N0 IO_LP P IO_LN 0 R UT 0 UT UT UT 0 0 PI INTERFE -0 VO_ 0UF 0V TNT 0V.UF 0V 0.UF V 0.0UF V VO_ VO_ FF0 NK IO_L0P_G K IO_L0N_G K IO_LP_G L IO_LN_G K IO_LP_G M IO_LN_G_0_ N0 IO_LP_G N IO_LN_G M IO_LP_G_ P0 IO_LN_G_VREF_ N IO_LP_G_ M IO_LN_G_ M IO_LP_G_ M IO_LN_G_ N IO_LP_G_VRN_ N IO_LN_G_VRP_ N IO_LP G_ L IO_LN G_ M IO_LP G_ P IO_LN G_ N 0 LK0 LK LK LK LVS_P LVS_N LK LK LVTTL LVTTL LVS_P LVS_N PI INTERFE Q0-Q SM LOKS SOKET LOKS SM LOKS VO_ U VO_ 0UF 0V TNT 0V.UF 0V 0.UF V 0.0UF R VO_ V VO_ FF0 NK IO_L0P RS_ H IO_L0N RS0_ J IO_LP H0 IO_LN H IO_LP J IO_LN J IO_LP K0 IO_LN_0_ J0 IO_LP_FS K IO_LN_VREF_FOE MOSI_ K IO_LP_FWE L IO_LN_SO L0 IO_LP J IO_LN K IO_LP J IO_LN K IO_LP L IO_LN FS_ L IO_LP FS_ J IO_LN_0_FS0_ J UT UT UT UT UT 0 UT UT UT UT UT 0 UT UT 0 PI INTERFE - PI FLSH_E_# & SPI SELET PI INTERFE OE & SPI_MOSI PI INTERFE FLSH_WE_# PI INTERFE Q0-Q PI REVISION SELET PINS UT 0 FLSH_ UT UT J 0 H-X R00.K /W UT FLSH_ UT UT R.K /W -: Selects R from FPG to FLSH R -: Selects RS from FPG to FLSH R -: Pulldown for RS applications -: Selects R from FPG to FLSH R -: Selects RS0 from FPG to FLSH R -0: Pulldown for RS applications SH P/N 0 RT P/N 0 F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER ONFIGURTION ate: --00_:0 Size: 0 rawn y

5 UPPER LOKS OTTOM LOKS VO_ VO_ VO_ U OE0_R 0 Ohm Routing 0 Ohm Routing 0 /0W X OE_ V_ OE_ GN R GN GN SIG GN GN GN GN SIG GN GN V_ OUT -- J 000 J 000 R0 LVTTL0_R /W LK0 LVTTL0 J0 0 V 0.UF H-X FX LOW SPEE 0 OHM LOK ONNETION OE_R 0 /0W X OE_ V_ OE_ GN V_ OUT 0 R VO_ LVTTL_R LVTTL V 0.UF /W J LK H-X FX LOW SPEE 0 OHM LOK ONNETION J Ohm ifferential Routing 00 Ohm ifferential Routing GN GN LVS0_N SIG LVS_N GN GN R NOTE: R NOTE: 00 PLE RESISTOR J 00 PLE RESISTOR LOSE TO FPG 000 LOSE TO FPG /W /W GN GN LVS0_P SIG LVS_P GN GN R -- 0UF 0V TNT 0V.UF 0V V 0.UF 0.0UF J VO_ E VO_ FF0 NK IO_L0P G_ K IO_L0N G_ K IO_LP G_ M IO_LN G_ N IO_LP_G_VRN_ K IO_LN_G_VRP_ J IO_LP_G_ L IO_LN_G_ M IO_LP_G_ L IO_LN_G_VREF_ L IO_LP_G_ K IO_LN_G_ K IO_LP_G_ M IO_LN_G_ L IO_LP_G_ J0 IO_LN_G_ K0 IO_LP_G_ N IO_LN_G_ M IO_LP_G_ L IO_LN_G_ L0 LVS0_P LVS0_N LVTTL0 LVTTL LK LK LK LK LK LK LK0 LK LK LK LK LK LK LK LVS_P LVS_N SM LOKS SOKET LOKS SM LOKS OE_R 0 /0W X OE_ V_ OE_ GN 0 Ohm Routing R GN GN SIG GN GN GN GN SIG GN GN V_ OUT -- J 000 J 000 VO_ R LVTTL_R /W LK LVTTL J 0 V 0.UF H-X FX LOW SPEE 0 OHM LOK ONNETION OE_R 0 Ohm Routing 0 /0W X OE_ V_ OE_ GN V_ OUT -- R LVTTL_R 0 V 0.UF H-X FX LOW SPEE 0 OHM LOK ONNETION J Ohm ifferential Routing GN 00 Ohm ifferential Routing GN LVS_N SIG LVS_N GN GN R NOTE: R0 NOTE: 00 PLE RESISTOR J 00 PLE RESISTOR LOSE TO FPG 000 LOSE TO FPG /W /W GN GN LVS_P SIG LVS_P GN GN R VO_ /W LK LVTTL J ate: FX LOK ONFIGURTION -, -: LOW SPEE 0 OHM LOK ONNETION -, -: HIGH SPEE 00 OHM IFFERENTIL LOK ONNETION TO IFFERENTIL PIR -, -: HIGH SPEE 00 OHM IFFERENTIL LOK ONNETION TO IFFERENTIL PIR -, -0: LOW SPEE 0 OHM LOK ONNETION LK LVS0_N HSLK_Q_N LVS_N LK LK0 LVS_N HSLK_Q_N LVS_N LK SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER --00_:0 J 0 J H-X 0 H-X LK LVS0_P HSLK_Q_P LVS_P LK LK LVS_P HSLK_Q_P LVS_P LK SH P/N 0 RT P/N 0 F P/N 00 SOKET LOKS, SM IFF LOKS Size: 0 rawn y

6 0 VO_ VO_ VO_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SM0N_ IO_LP_SM0P_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN SMN_ IO_LP SMP_ IO_L0N SMN_ IO_L0P SMP_ IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN SM0N_ IO_LP SM0P_ IO_LN SMN_ IO_LP SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_VREF_ IO_LP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_L0N_SMN_ IO_L0P_SMP_ NK FF0 ate: Size: rawn y LE'S LE'S USR RESET LE'S SYSTEM MONITOR MLE ONNETOR SYSTEM MONITOR FILTERS SM_R_N SM_R_N SM P SM_R_P SM_R_P SM_R_P SM_R_P SM_R_N SM0_R_N --00_:0 RT P/N 0 SH P/N 0 SYSTEM MONITOR SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER F P/N 00 0 V U U T T R P P N M M L K L L0 K0 0 0 E0 J0 H0 J J H G G F0 F F E U Y U0 V Y W W V0 V U U T T T0 R0 P P R Y Y Y 0 Y0 W0 P0 N0 N M M L L L0 K J J H G F G F U UT UT 0 UT UT UT 0 SM_R_N SM_R_P VSS VSS R K /W SM N SM P SM N SM P SM N VSS J H-X UT 0 UT 0 SM_R_P SM_R_P SM_R_N SM_R_N 0 0.0UF V UT UT /W K R R K /W 0 0.0UF V VO_ TNT 0V 0UF.UF 0V 0.UF 0V 0.0UF V VO_.UF 0V TNT 0V 0UF 0.UF 0V 0.0UF V /W K R R K /W UT UT 0.0UF V /W K R R K /W SM_R_P SM_R_N UT 0.0UF V /W K R R K /W SM_R_P SM_R_N UT 0.0UF V /W K R R0 K /W SM_R_P SM_R_N UT UT 0.0UF V /W K R R K /W SM0_R_P SM0_R_N UT UT 0.0UF V /W K R R K /W SM_R_N 0 0.0UF V /W K R R K /W 0 0.0UF V /W K R R K /W UF V /W K R R K /W 0.0UF V /W K R R K /W 0.0UF V /W K R R0 K /W 0.0UF V /W K R R K /W 0.0UF V /W K R SM0_R_P SM_R_P SM_R_N SM_R_P UT 0 UT 0 SM_R_P SM_R_N UT 00 UT 0 SM_R_P SM_R_N UT UT SM_R_P SM_R_N UT UT SM_R_P SM_R_N SM P SM N SM0_R_N UT UT /W K R R0 K /W 0 0.0UF V UT 0 SM_R_P SM_R_N UT 0 /W K R R K /W 0 0.0UF V UT SM_R_P SM_R_N UT 0 SM_VP SM_VN VSS XP XN VSS VSS V VREFINV VSS VSS VSS VREFOUTV VSS VSS VSS VSS VO_ VO_ SM_R_P SM_R_N SM_R_N SM_R_N SM0_R_P SM_R_P SM_R_N UT UT UT UT UT UT UT UT UT VREF UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT SM_R_N SM_R_P SM_R_N SM_R_P SM_R_P SM_R_N SM_R_P UT 0 SM_R_N UT 0 SM_R_P SM_R_P SM_R_N SM_R_P SM_R_N SM_R_P SM_R_N SM0_R_P SM0_R_N UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT VREF UT UT

7 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 ate: Size: rawn y FLSH_WP_# PI INTERFE FLSH_V_# FLSH_RST_# FLSH_WIT FLSH_LK FLSH_OE_# --00_:0 RT P/N 0 SH P/N 0 UT INTERFE F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 W Y Y Y Y V W W W V V U U T U T R P P R P N M N M L K M L H G J J F G F E U U0 P R P R T U M L T T0 N M T R0 N P T T R R R R P N T T N0 P0 T T L M R P L0 K0 K K J0 J J J U G0 H H G L L0 J H J0 K0 G H H J G H G G F G G H H0 G J J H J K K M N M L N P P P N0 P0 N M U W T Y K L M L K J J K M L T T T U R P R0 T0 R R P R R R P N R P P N N N M M P P L K M L U F H0 H P R G G N N H G L M K J K K J J M M L K N P J H L M J J K K G H L L H G N M U UT UT UT UT UT UT UT 0 UT UT VREF UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 00 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT FLSH_LK_TMP UT VREF UT 0 UT UT UT UT UT UT UT UT VREF UT 00 UT UT UT UT UT 0 UT 0 UT UT UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT VREF UT 0 UT UT UT 0 UT 0 UT UT UT 0 UT 0 UT 0 UT 00 UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT VREF UT VREF UT UT UT UT UT UT UT UT UT 00 UT 0 UT UT 0 UT UT 0 UT UT 0 UT 0 UT UT 0 UT UT UT 0 UT 0 UT UT UT 0 UT 0 UT UT UT VREF UT 0 UT UT UT UT UT 0 UT UT UT UT UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 VO_ VO_ VO_ 0UF 0V TNT 0UF 0V TNT VO_ 0 0UF 0V TNT 0V 0.UF V 0.0UF 0V.UF 0.0UF V 0 0.UF 0V TNT 0V 0UF.UF 0V VO_ 0V.UF 0V 0.UF V 0.0UF 0V.UF 0V 0.UF V 0.0UF VO_ VO_ VO_ VO_ 0.0UF V 0.UF 0V.UF 0V TNT 0V 0UF R /W UT VO_ UT UT UT 0 UT UT UT UT UT UT VREF UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT VREF UT 00 UT 0 UT 0 UT 0

8 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK ate: Size: rawn y --00_:0 RT P/N 0 SH P/N 0 UT INTERFE F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 H J F N M R R M N N P L K L L H J K J G H H G F F F E E E 0 0 U G0 H E L M M N P N M L H J K K K J H G R T U V0 T0 R0 P0 N0 F G G F E E E U V R T 0 W0 W Y Y0 Y W Y V W W W V U T U R R T T M N P N K K L L G H J H E E F G U P R M W W W Y Y W V U T U T U V K K0 J0 H0 J K L M M N N P P R R R E0 E F0 F G G H H U G0 E U U T T N P P R L M M M J K K L G H J J H G G F F E E U UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT 0_VREF UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT 0_VREF UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT 0_VREF UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT VREF UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0_VREF UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT VO_ VO_ VO_ VO_ TNT 0V 0UF 0UF 0V TNT VO_ V 0.0UF 0 0V 0.UF 0V.UF 0UF 0V TNT 0V.UF 0V 0.UF V 0.0UF 0.0UF V 0.UF 0V.UF 0V TNT 0V 0UF VO_ VO_ VO_ 0.UF 0V 0.UF 0V TNT 0V 0UF 0.0UF V.UF 0V 0.UF 0V 0.0UF V VO_ VO_

9 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_0 VO_0 VO_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VRP_0 IO_LP_VRN_0 IO_LN 0 IO_LP 0 IO_L0N 0 IO_L0P 0 IO_LN 0 IO_LP 0 IO_LN 0 IO_LP 0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_L0N_0 IO_L0P_0 FF0 NK 0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 ate: Size: rawn y --00_:0 RT P/N 0 SH P/N 0 UT INTERFE SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 F P/N 00 L M J K L L L K J J H M N N M N P P P G H G H F F F E T R R T U U V V E E E U P L M U V T T T U V V P P P R M N N M K L L K G H F G G H0 J H K J G H F G F F0 E E E0 F U G0 E T U U T R R P P L L J K J K K L E E F F F E E F J H G G H G G H P N M M M M N N U P L M V0 V V V T U U U T U R R T R R0 T0 P N N P M M N P L L M M J K K J H J H G E F F G U K L H Y W Y W V V V E E F G F G H V U T R U T T U J K J H J K L L P N M L M N P R U UT VREF UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 00 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT 00 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 00 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT 00 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT 0UF 0V TNT 0.0UF V VO_ VO_ VO_ VO_0 TNT 0V 0UF.UF 0V 0.UF 0V 0.0UF V VO_ VO_ 0.UF 0V.UF 0V TNT 0V 0UF 0UF 0V TNT 0V.UF 0V 0.UF V 0.0UF V 0.0UF 0V 0.UF 0V.UF 0UF 0V TNT VO_0 VO_ UT VO_ 0V.UF 0V 0.UF VO_ V 0.0UF

10 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK ate: Size: rawn y --00_:0 0 RT P/N 0 SH P/N 0 UT INTERFE SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 F P/N 00 G0 E U F E U R W T K J J J0 L0 K0 L L M M P0 N N0 M P N P P T R R0 R T T0 U V U U V V0 T U R R U T V U U V U U0 P R M L M L K J J K M N P R P R N P T T U V V V U U R R T U T U V V J H G H G F F G U H J F G F E E K K J H G F E E0 H0 H F F0 G F E E G H G H J J0 J K L0 L K0 L M N L M N0 P0 P P U IO_ IO_E IO_ IO_0 UT UT 0 UT UT UT UT UT UT UT UT VREF UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT VO_ VO_ VO_ VO_ 0V.UF V 0.0UF 0V 0.UF 0UF 0V TNT 0.UF 0V 0.0UF V 0.UF 0V TNT 0V 0UF VO_ 0V.UF VO_ V 0.0UF 0V 0.UF 0 0UF 0V TNT 0V.UF VO_ V 0.0UF 0V 0.UF 0UF 0V TNT VO_ VO_ TNT 0V 0UF 0.UF 0V 0.0UF V VO_.UF 0V UT UT 0 UT UT UT UT UT UT UT UT VREF UT UT UT 0 UT UT UT UT UT UT UT UT 0 UT IO_ IO_ IO_ IO_ IO_ IO_ IO_ UT VREF IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_

11 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_0 VO_0 VO_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VRP_0 IO_LP_VRN_0 IO_LN 0 IO_LP 0 IO_L0N 0 IO_L0P 0 IO_LN 0 IO_LP 0 IO_LN 0 IO_LP 0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_L0N_0 IO_L0P_0 NK 0 FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK ate: Size: rawn y --00_:0 RT P/N 0 SH P/N 0 UT INTERFE SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 F P/N 00 F 0 0 U G0 H E0 0 F F0 E E F F E F E E F E E F 0 F E E F0 E0 E F F F F E E U U0 V Y Y W W Y Y 0 W0 Y0 W Y W W Y W Y W Y Y W W V U V W T W Y0 0 Y W W Y Y W Y W Y Y W W Y 0 Y0 W0 W W Y U IO_ IO_ IO_Y IO_Y UT IO_ IO_ IO_0 IO_ IO_ IO_ IO_Y0 IO_W0 IO_W IO_W IO_Y UT 0 UT UT UT UT UT UT VREF UT UT UT 0 UT UT UT UT UT UT UT UT VREF UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT VREF UT UT UT VREF UT UT UT UT UT UT 0 VO_ VO_ 0V.UF V 0.0UF 0 0V 0.UF 0UF 0V TNT.UF 0V 0.0UF V 0.UF 0V TNT 0V 0UF 0V.UF VO_ V 0.0UF 0V 0.UF 0UF 0V TNT 0V.UF 0 VO_0 V 0.0UF 0V 0.UF 0UF 0V TNT VO_ VO_0 VO_ VO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_0 IO_0 IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_E IO_ IO_E IO_F IO_ IO_ IO_F IO_F IO_F IO_E IO_E0 IO_F0 IO_ IO_E IO_E IO_F IO_ IO_ IO_ IO_0 IO_F IO_E IO_E IO_F IO_ IO_ IO_E IO_E IO_F IO_E IO_F IO_F IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_E IO_E IO_ IO_ IO_F0 IO_F IO_0 IO_E0

12 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK ate: Size: rawn y --00_:0 RT P/N 0 SH P/N 0 UT INTERFE SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 F P/N 00 W T Y Y Y Y Y Y Y Y Y0 0 Y Y Y Y Y U Y U0 V W V U V W W V V W U U V W U U W0 W V0 V U U W W V V V W W W U U U V W0 V0 U V W V U IO_V IO_V IO_ VO_ VO_ 0V.UF V 0.0UF 0V 0.UF 0UF 0V TNT.UF 0V 0.0UF V 0 0.UF 0V TNT 0V 0UF VO_ VO_ IO_Y IO_Y IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_Y IO_ IO_Y IO_Y IO_ IO_ IO_ IO_ IO_0 IO_Y0 IO_Y IO_Y IO_Y IO_Y IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_Y IO_Y IO_ IO_ IO_ IO_Y IO_ IO_W IO_V IO_U IO_V0 IO_W0 IO_V IO_U IO_U IO_U IO_W IO_W IO_W IO_V IO_V IO_V IO_W IO_W IO_U IO_U IO_V IO_V0 IO_W IO_W0 IO_U IO_U IO_W IO_V IO_U IO_U IO_W IO_V IO_W IO_W IO_V IO_U IO_V IO_W IO_V

13 GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN00 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN00 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN FF0 GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN0 GN00 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN0 GN GN GN GN GN GN GN GN GN GN FF0 VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT0 VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT FF0 VUX0 VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX0 VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX FF0 ate: Size: rawn y.0v ULK-RIL HIGH FREQUEY RIL.V FPG ORE Y-PSS HIGH FREQUEY RIL FPG VUX Y-PSS --00_:0 RT P/N 0 SH P/N 0 FPG EOUPLING PITORS F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 V H F T Y E 0 0 W0 W U0 U F R U Y G E W U H F Y V T G E W U R H F Y V T J G E W U R H F Y V T G E W U R H F V T G0 E0 0 0 W0 U0 R0 H F Y V T G E W U H F Y V T G E W U Y V E W Y V U E W U R K E 0 M0 H0 F0 0 0 Y0 V0 T0 M0 0 W J G E W U R P J T L H F Y V T L F N G E W U N Y K F Y V T R K U M G E W U M G P J Y V P L G E W U R L V N H Y V T N H R K E Y R K E 0 M0 0 U0 M0 0 W J W J T F T F N N Y K Y K U G U G P P L L V N H V N H Y R K E Y R K E U V N H V N H Y R K E R E 0 M0 0 M0 0 W J W J T F T F N N Y K Y K U G U G P W P J L F T L V N H V N H R K E W R K E 0 M0 0 0 Y0 V0 M0 0 W P J E W U P J T F Y V T L F N G E W U N Y K H F Y V T K U M G E W U R M G P H F Y V T P L G E W U R L V N H F V T H R K G U V 0.0UF UF V V 0.0UF 0.0UF V 0.UF 0V V 0.0UF 0UF 0V TNT 0 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.UF 0V 0.UF 0V 0.UF 0V 0UF 0V TNT VINT VINT V 0.0UF 0.UF 0V 0UF 0V TNT 0.UF 0V VINT VUX 0.UF 0V 0.UF 0V 0.UF 0V 0 0UF 0V TNT 0UF 0V TNT 0.UF 0V 0UF 0V TNT 0 0.UF 0V 0.UF 0V 0.UF 0V 0.UF 0V 0.UF 0V 0.UF 0V 0 0.UF 0V 0.UF 0V 0.UF 0V 0.UF 0V 0.UF 0V 0.UF 0V 0.UF 0V 0.UF 0V VUX VUX V 0.0UF 0 V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF V 0.0UF 0.0UF V

14 VO_ VO_ IO_LN 0 IO_LP IO_LN IO_LP IO_LN 0_ IO_LP IO_LN IO_LP IO_LN IO_LP IO_LN_VREF_0 IO_LP IO_LN IO_LP IO_LN 0_ IO_LP IO_LN IO_LP IO_L0N IO_L0P NK FF0 VO_ VO_ IO_LN_0_FS0_ IO_LP FS_ IO_LN FS_ IO_LP IO_LN IO_LP IO_LN IO_LP IO_LN_SO IO_LP_FWE IO_LN_VREF_FOE MOSI_ IO_LP_FS IO_LN_0_ IO_LP IO_LN IO_LP IO_LN IO_LP IO_L0N RS0_ IO_L0P RS_ NK FF0 VO_ VO_ IO_LN_G_ IO_LP_G_ IO_LN_G_ IO_LP_G_ IO_LN_G_ IO_LP_G_ IO_LN_G_ IO_LP_G_ IO_LN_G_ IO_LP_G_ IO_LN_G_VREF_ IO_LP_G_ IO_LN_G_ IO_LP_G_ IO_LN_G_VRP_ IO_LP_G_VRN_ IO_LN G_ IO_LP G_ IO_L0N G_ IO_L0P G_ FF0 NK VO_ VO_ IO_LN G_ IO_LP G_ IO_LN G_ IO_LP G_ IO_LN_G_VRP_ IO_LP_G_VRN_ IO_LN_G_ IO_LP_G_ IO_LN_G_ IO_LP_G_ IO_LN_G_VREF_ IO_LP_G_ IO_LN_G IO_LP_G IO_LN_G_0_ IO_LP_G IO_LN_G IO_LP_G IO_L0N_G IO_L0P_G NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 ate: Size: rawn y VO_0 VO_0 TO_0 _OUT_USY_0 TI_0 TMS_0 M_0 M_0 M0_0 TK_0 R_FUSE_0 RSV RWR 0 S 0 INIT 0 LK_0 ONE_0 _IN_0 HSWPEN_0 PROGRM 0 VTT_0 VREFN_0 VREFP_0 VN_0 VP_0 VSS_0 V_0 XN_0 XP_0 FF0 NK 0 G0 L H H G F F0 H G E0 V R0 T0 U F T R T T R Y Y U --00_:0 RT P/N 0 SH P/N 0 UT TEST PINS F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 G0 H H G L L0 J H J0 K0 G H H J G H G G F G G H H0 G J J H J K K M N M L N P P P N0 P0 N M U W T Y K L M L K J J K M L T T T U R P R0 T0 R R P R R R P N R P P N N N M M P P L K M L U F H0 H P R G G N N H G L M K J K K J J M M L K N P J H L M J J K K G H L L H G N M U V N P M L N N N M M M N P0 M N N0 M K L K K U E J L0 L M N K0 J0 L M K K L L M L J K N M K K U V R J J L L K J K J L0 L K K J0 K0 J J H H0 J H U E J R P N0 P0 P N M N P N P N R P P P N M R R U VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VTT PROG HSWP_EN _IN ONE LK INIT S_# RWR_# RSV RFUSE TK M0 M M TMS FPG_TI OUT_USY FPG_TO 0 UT UT UT 0 0 UT UT UT UT UT UT UT 0 UT UT UT UT UT 0 UT 0 LVS0_P LVS0_N LVTTL0 LVTTL LK LK LK LK LK LK LK0 LK LK LK LK LK LK LK LVS_P LVS_N LK 0 LVS_N LVS_P LVTTL LVTTL LVS_P LVS_N LK LK LK0 LK LK UT VREF UT UT UT UT UT UT UT UT UT 00 UT 0 UT UT 0 UT UT 0 UT UT 0 UT 0 UT UT 0 UT UT UT 0 UT 0 UT UT UT 0 UT 0 UT UT UT VREF UT 0 UT UT UT UT UT 0 UT UT UT UT UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT UT UT 0 UT UT UT UT UT UT VREF UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT VREF UT 00 UT 0 UT 0 UT 0 UT 0 UT 0 UT UT UT 0 UT 0 UT UT UT 0 UT VREF UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT UT UT 0 UT 0 UT UT UT 00 UT VREF UT UT UT UT UT UT UT UT UT UT 0

15 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN SM0N_ IO_LP SM0P_ IO_LN SMN_ IO_LP SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_VREF_ IO_LP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_L0N_SMN_ IO_L0P_SMP_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SM0N_ IO_LP_SM0P_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_SMN_ IO_LP_SMP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN SMN_ IO_LP SMP_ IO_L0N SMN_ IO_L0P SMP_ IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 ate: Size: rawn y --00_:0 RT P/N 0 SH P/N 0 UT TEST PINS F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 Y U0 V Y W W V0 V U U T T T0 R0 P P R Y Y Y 0 Y0 W0 P0 N0 N M M L L L0 K J J H G F G F U G0 E U U T T N P P R L M M M J K K L G H J J H G G F F E E U V U U T T R P P N M M L K L L0 K0 0 0 E0 J0 H0 J J H G G F0 F F E U W Y Y Y Y V W W W V V U U T U T R P P R P N M N M L K M L H G J J F G F E U U0 P R P R T U M L T T0 N M T R0 N P T T R R R R P N T T N0 P0 T T L M R P L0 K0 K K J0 J J J U UT R 0 /0W UT UT UT UT UT UT UT UT UT UT UT UT VO_ VO_ VO_ /0W 0 R VO_ R 0 /0W /0W 0 R SM N SM P UT 0 UT 00 UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT VREF UT VREF UT UT 0 UT 0 UT UT UT UT UT UT UT UT UT VREF UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT VREF UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT 0 UT UT VREF UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 00 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT VO_ UT UT 0 UT UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT UT UT UT UT VREF UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT 0 UT 00 SM P SM N UT 0 UT

16 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_0 VO_0 VO_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VRP_0 IO_LP_VRN_0 IO_LN 0 IO_LP 0 IO_L0N 0 IO_L0P 0 IO_LN 0 IO_LP 0 IO_LN 0 IO_LP 0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_L0N_0 IO_L0P_0 FF0 NK 0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 ate: Size: rawn y --00_:0 RT P/N 0 SH P/N 0 UT TEST PINS F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 L M J K L L L K J J H M N N M N P P P G H G H F F F E T R R T U U V V E E E U UT UT UT UT UT 0 UT 0 UT 0 UT 0 UT 0 P L M V0 V V V T U U U T U R R T R R0 T0 P N N P M M N P L L M M J K K J H J H G E F F G U G0 H E L M M N P N M L H J K K K J H G R T U V0 T0 R0 P0 N0 F G G F E E E U K L H Y W Y W V V V E E F G F G H V U T R U T T U J K J H J K L L P N M L M N P R U H J F N M R R M N N P L K L L H J K J G H H G F F F E E E 0 0 U V R T 0 W0 W Y Y0 Y W Y V W W W V U T U R R T T M N P N K K L L G H J H E E F G U P R M W W W Y Y W V U T U T U V K K0 J0 H0 J K L M M N N P P R R R E0 E F0 F G G H H U VO_ VO_0 VO_ VO_ VO_ UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT 0_VREF UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT 0_VREF UT UT UT UT UT UT UT UT UT UT VREF UT UT UT UT UT UT UT UT UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 00 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT 00 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT VO_ UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0_VREF UT 0 UT UT UT UT UT UT UT UT UT VO_ UT UT UT UT UT UT UT UT UT UT 0_VREF UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT 0 UT 0 UT 0 UT 0 UT 0 UT 00 UT UT UT UT UT UT UT UT

17 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK ate: Size: rawn y --00_:0 RT P/N 0 SH P/N 0 UT TEST PINS F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 G0 E U F E U R W T K J J J0 L0 K0 L L M M P0 N N0 M P N P P T R R0 R T T0 U V U U V V0 T U R R U T V U U V U U0 P R M L M L K J J K M N P R P R N P T T U V V V U U R R T U T U V V J H G H G F F G U H J F G F E E K K J H G F E E0 H0 H F F0 G F E E G H G H J J0 J K L0 L K0 L M N L M N0 P0 P P U G0 E T U U T R R P P L L J K J K K L E E F F F E E F J H G G H G G H P N M M M M N N U P L M U V T T T U V V P P P R M N N M K L L K G H F G G H0 J H K J G H F G F F0 E E E0 F U VO_ VO_ VO_ UT UT UT 0 UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT VO_ IO_ IO_E IO_ IO_0 UT UT 0 UT UT UT UT UT UT UT UT VREF UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT VREF UT UT UT 0 UT UT UT UT UT UT UT UT 0 UT IO_ IO_ IO_ IO_ IO_ IO_ IO_ UT VREF IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ VO_ VO_ VO_ UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 00 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT 0 UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT

18 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ NK FF0 VO_0 VO_0 VO_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VRP_0 IO_LP_VRN_0 IO_LN 0 IO_LP 0 IO_L0N 0 IO_L0P 0 IO_LN 0 IO_LP 0 IO_LN 0 IO_LP 0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_L0N_0 IO_L0P_0 NK 0 FF0 VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK VO_ VO_ VO_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRP_ IO_LP_VRN_ IO_LN IO_LP IO_L0N IO_L0P IO_LN IO_LP IO_LN IO_LP IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VREF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_L0N_ IO_L0P_ FF0 NK ate: Size: rawn y --00_:0 RT P/N 0 SH P/N 0 UT TEST PINS F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 IO_ W T Y Y Y Y Y Y Y Y Y0 0 Y Y Y Y Y U Y U0 V W V U V W W V V W U U V W U U W0 W V0 V U U W W V V V W W W U U U V W0 V0 U V W V U F 0 0 U G0 H E0 0 F F0 E E F F E F E E F E E F 0 F E E F0 E0 E F F F F E E U U0 V Y Y W W Y Y 0 W0 Y0 W Y W W Y W Y W Y Y W W V U V W T W Y0 0 Y W W Y Y W Y W Y Y W W Y 0 Y0 W0 W W Y U VO_0 UT IO_ IO_ IO_0 IO_ IO_ IO_ IO_Y0 IO_W0 IO_W IO_W IO_Y UT 0 UT UT UT UT UT UT VREF UT UT UT 0 UT UT UT UT UT UT UT UT VREF UT UT UT 0 UT UT UT UT UT UT UT VO_ IO_ IO_ IO_Y IO_Y UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT UT UT UT UT UT UT UT UT UT 0 UT VREF UT UT UT VREF UT UT UT UT UT UT 0 IO_E IO_ IO_E IO_F IO_ IO_ IO_F IO_F IO_F IO_E IO_E0 IO_F0 IO_ IO_E IO_E IO_F IO_ IO_ IO_ IO_0 IO_F IO_E IO_E IO_F IO_ IO_ IO_E IO_E IO_F IO_E IO_F IO_F IO_E IO_E IO_ IO_ IO_F0 IO_F IO_0 IO_E0 VO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_0 IO_0 IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ VO_ IO_V IO_V IO_W IO_V IO_U IO_V0 IO_W0 IO_V IO_U IO_U IO_U IO_W IO_W IO_W IO_V IO_V IO_V IO_W IO_W IO_U IO_U IO_V IO_V0 IO_W IO_W0 IO_U IO_U IO_W IO_V IO_U IO_U IO_W IO_V IO_W IO_W IO_V IO_U IO_V IO_W IO_V VO_ VO_ IO_ IO_Y IO_Y IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_Y IO_ IO_Y IO_Y IO_ IO_ IO_ IO_ IO_0 IO_Y0 IO_Y IO_Y IO_Y IO_Y IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_Y IO_Y IO_ IO_ IO_ IO_Y IO_

19 LE-GRN-SMT J J R 00 /W --00 S RP V VIN 0UF 0V TNT 0UF SHIEL R UT_METET_V0_VUX SUPPLY.K.V MX /W U VIN VOUT SHN SENSE 0UF V TNT V TNT R.K /W 0UF VIN V TNT 0MSQE R.K /W UT_PWRN_V_ SW UT_PWRN_V0_.V MX U VIN VOUT SHN SENSE T GN U VIN VOUT SHN SENSE T GN T GN.V LTE-. LTEQ#PF LTE-. VV 00UF 0V TNT R 00 % /0W R. % /0W R 00 % /0W R 0 % /0W R R. % /0W.K /W R 00 % /0W V 0UF 00UF 0V TNT 00UF 0V TNT 0UF PTV000W TRK VI MX INHIIT 0V TNT VV 0 0UF GN UT_METET_V0_ V 0V TNT 0 0UF 0V TNT VV_ 0 0UF.V TNT J GN ORE SUPPLY.0V U VO VO JUST H-X R.K % /W VUX J RSV VUX.V TO PROVIE POWER SHORT PIN & SHORT PIN & H-X J VV J0 VINT PLE OPPER SHPE WITH VIS VV ROUN EH POWER PIN ON J TO PROVIE POWER SHORT PIN & SHORT PIN & UT_METET_V0_,0 00UF 0V TNT UF.V TNT J0 V I/O SELETION J VO_0 VO_ VO_ VO_ VO_ 0 VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_0 VO_0 VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_0 VO_0 VO_ VO_ VO_ H-X H-X VINT J --00 VO_0 VO_ VO_ VO_ VO_ 0 VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_0 VO_0 VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_0 VO_0 VO_ VO_ VO_ VV 0 0 V V 0UF 0UF VO H-X VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN0 VIN VIN VIN VIN VIN VIN VIN VIN PGN PGN PGN PGN PGN PGN E PGN E PGN E PGN E PGN0 E PGN E PGN E PGN F PGN F PGN F PGN F PGN F PGN F PGN F PGN0 F PGN F PGN G PGN G PGN PGN PGN PGN0 PGN PGN PGN PGN PGN VOSNS- VOSNS+ SENSE LINES ONNET T LO J VO U LTM0 R H G G G G G G VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS VPS M J J K /0W H-X G 0 INTV VF F RV E SGN H MRG MRG0 FSET MPGM OMP RUN TRK/SS PLLIN PGOO PGN0 PGN PGN PGN PGN PGN PGN PGN G H H H H H H H H VOUT_LL IFFVOUT L K ate: R VOUT M VOUT M0 VOUT M VOUT0 M VOUT M VOUT M VOUT M VOUT M VOUT M VOUT M VOUT M VOUT L VOUT L0 VOUT0 L VOUT L VOUT L VOUT L VOUT L VOUT L VOUT L VOUT L VOUT L VOUT K VOUT0 K0 VOUT K VOUT K VOUT K VOUT K VOUT K VOUT K VOUT K VOUT K VOUT K VOUT0 J0 VOUT J VOUT J VOUT J VOUT J VOUT J VOUT J VOUT J VOUT J VOUT J SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER Size: /W.K% --00_:0 R NP % /W YV V UF VO SUPPLY.V 0 TO PROVIE ON OR REGULTION POWER VV J R 00K /W 0 0UF VV 0V TNT H-X YV V UF rawn y SHORT PIN & SHORT PIN & VO.V PLE OPPER SHPE WITH VIS ROUN EH POWER PIN ON J & J GN FPG POWER SUPPLY VO 0UF 0V TNT 0UF 0V TNT SH P/N 0 RT P/N 0 F P/N 00 J 0 NPO 0V 00PF J --00 J VV --00 VO H-X

20 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V ate: Size: rawn y --00_:0 0 RT P/N 0 SH P/N 0 POWER LE INITORS F P/N 00 SHEM, ROHS OMPLINT, VIRTEX FF0 UGHTER 0 /0W 0 R /0W 0 R /0W 0 R R 0 /0W /0W 0 R R 0 /0W /W 0 R R 0 /W /W 0 R R 0 /W /W 0 R R 0 /W /W 0 R R 0 /W /W 0 R /W 0 R R 0 /W /W 0 R R 0 /W R 0 /W /W 0 R R 0 /W /W 0 R R 0 /W /W 0 R R 0 /W /W 0 R0 R 0 /W /W 0 R R 0 /W /W 0 R R 0 /0W /0W 0 R Q LE-GRN-SMT S0 R 0 /0W S LE-GRN-SMT Q R 0 /0W S LE-GRN-SMT Q /0W 0 R LE-GRN-SMT S VINT S LE-GRN-SMT Q R 0 /0W S LE-GRN-SMT Q VUX R 0 /0W S LE-GRN-SMT Q Q LE-GRN-SMT S /0W 0 R Q0 LE-GRN-SMT S Q LE-GRN-SMT S R0 0 /0W S LE-GRN-SMT Q R 0 /0W S0 LE-GRN-SMT Q R 0 /0W S LE-GRN-SMT Q Q Q LE-GRN-SMT S R 0 /0W S LE-GRN-SMT Q S LE-GRN-SMT Q R 0 /0W VO VO_0 VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ Q LE-GRN-SMT S /0W 0 R Q LE-GRN-SMT S /0W 0 R R 0 /0W S LE-GRN-SMT Q S LE-GRN-SMT Q R 0 /0W S0 LE-GRN-SMT Q VO_ VO_ Q0 LE-GRN-SMT S R 0 /0W S LE-GRN-SMT Q VO_ VO_ Q LE-GRN-SMT S /0W 0 R0 VO_ Q LE-GRN-SMT S /0W 0 R Q LE-GRN-SMT S /0W 0 R VO_ R 0 /W /W 0 R0 VO_ R0 0 /0W S LE-GRN-SMT Q Q LE-GRN-SMT S /0W 0 R Q0 LE-GRN-SMT S VO_ VO_ /W 0 R R 0 /W R 0 /0W S LE-GRN-SMT Q VO_ R 0 /0W S LE-GRN-SMT Q VO_ VO_ Q LE-GRN-SMT S /0W 0 R S LE-GRN-SMT Q VO_ VO_0 Q LE-GRN-SMT S /0W 0 R VO_ VO_ Q LE-GRN-SMT S /0W 0 R S0 LE-GRN-SMT Q R 0 /0W /W 0 R R 0 /W /W 0 R0 R 0 /W /W 0 R R 0 /W /W 0 R R 0 /0W

Virtex 5 FF1738 DUT. Single Ended Socket Clocks 2X. Differential SMA Clocks 2X. Differential SMA MGT Clocks 2X D. Upstream Connector.

Virtex 5 FF1738 DUT. Single Ended Socket Clocks 2X. Differential SMA Clocks 2X. Differential SMA MGT Clocks 2X D. Upstream Connector. PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE 0- Power us and Switches

More information

Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector.

Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector. PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE - Power us and Switches

More information

CAPACITIVE LOADS ALL UNUSED I/O'S 10pF LOADS PAGES AFXII RING PAGES 8-10 PAGE 5 FF1738 PAGE 4 XGI. DDR2 MEMORY 64 bit wide 128MB MHz

CAPACITIVE LOADS ALL UNUSED I/O'S 10pF LOADS PAGES AFXII RING PAGES 8-10 PAGE 5 FF1738 PAGE 4 XGI. DDR2 MEMORY 64 bit wide 128MB MHz MGT HRTERIZTION OR FOR V FXII OMPTILE POWER IN.0V PITIVE LOS LL UNUSE I/O'S 0pF LOS PGES - GTP/GTX0 PGE GTP/GTX PGE FXII RING PGES -0 FPG POWER SOURE ON OR REGULTION ORE.0V @ 0 MPS GTP/GTX PGE VO.V T MPS

More information

DOCUMENT NUMBER PAGE SECRET

DOCUMENT NUMBER PAGE SECRET OUMENT NUMER PGE SERET / SERET OUMENT NUMER PGE / Spartan onfiguration SPI Flash Q S V W/VPP HOL VSS U MPVME R 0 R.K 0.U 9 IO_LP 0 IO_LN VREF_ G IO_L9P_ G IO_L9N_ F IO_L0P_ F IO_L0N_ IO_L9P_ IO_L9N_ 0

More information

DB46 Top Level U_PSU PSU.SCHDOC. U_DB_Common DB_Common. U_Bypass_Board DB_Bypass. U_DB46_Hardware_Kit DB46_Hardware_Kit.SchDoc.

DB46 Top Level U_PSU PSU.SCHDOC. U_DB_Common DB_Common. U_Bypass_Board DB_Bypass. U_DB46_Hardware_Kit DB46_Hardware_Kit.SchDoc. U ommon _ommon U_PSU PSU.SHO U_ypass_oard _ypass U_6_Hardware_Kit 6_Hardware_Kit.Schoc Project Title 6 - Virtex SX Size: ssy: -80-00 Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: 6_Top.Schoc 6 Top

More information

Power USB I/F. USB->Uart AX309. Power LED :25:33 I:\AX\AX309\2.0\1_POWER.SchDoc VBUS VBUS D- D+ Fuse VCC GND D3V3 U

Power USB I/F. USB->Uart AX309. Power LED :25:33 I:\AX\AX309\2.0\1_POWER.SchDoc VBUS VBUS D- D+ Fuse VCC GND D3V3 U X0.0 0-- :: I:\X\X0\.0\_POWER.Schoc ate: R K Power LE LE SW SW V P P P V V F Fuse U SRV0- VUS P M RX TX LE RX LE TX R K R K VUS - I J US->Uart US I/F E 00uF/V OUT IN = U -. V E 00uF/V OUT IN = U -. V E

More information

DB30 Top Level DB30 - Daughter Board Spartan3

DB30 Top Level DB30 - Daughter Board Spartan3 U ommon _ommon U_PSU PSU.SHO U_ypass_oard _ypass U_0_Hardware_Kit 0_Hardware_Kit.Schoc ate: 0 Top Level 0 - aughter oard Spartan ssy: -80-000 Revision: 07 //008 Time: :0:6 PM 0_Top.Schoc Sheet of ltium

More information

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115 PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.

More information

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO

More information

DO NOT POPULATE FOR 721A-B ASSY TYPE

DO NOT POPULATE FOR 721A-B ASSY TYPE V R 0 R 0 R 0 R 0 R 0 R 0 TP TP pf 000pF 000pF 000pF R R R R R K % 0.0uF R.0K % 000pF IFFOUT pf R K % R 0 0 UVJ R K % U LTUH PLLIN PLLFLTR F IFF IFFOUT SENSE SENSE SENSE RUN/ UVJ SGN LKOUT OOST TG G OOST

More information

SVS 5V & 3V. isplsi_2032lv

SVS 5V & 3V. isplsi_2032lv PU 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF FLSH.0uF.0uF.0uF 0.0uF ata uffer.0uf.0uf.0uf.0uf SVS V & V.0uF.0uF.0uF isplsi_0lv.0uf.0uf

More information

P50V +IN 4 -VS AD8065AR. Cap Semi SH_CLEAR. C19 Cap Semi 0.1uF R210. Res3 15K, 1% P50V U VS -IN P50V. Vout +IN -VS AD8065AR SUB_TO_ADC

P50V +IN 4 -VS AD8065AR. Cap Semi SH_CLEAR. C19 Cap Semi 0.1uF R210. Res3 15K, 1% P50V U VS -IN P50V. Vout +IN -VS AD8065AR SUB_TO_ADC P0V PV J00 R_R R0 Res 00.uF JP0 Header R0 Res 0k 0 ode T 0.uF P0V R0 U0 Res.0K SH_UF 0R U0 OM V+ SH_MIN NO IN SH_SWITH SH_SWITH IN OM R0 GN NO Res 0 PI_ P0V R0 SH_MIN Res 0 0 pf mca SH_LER SH_LER U0 0R

More information

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1. Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT

More information

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown

More information

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History 0-SH-0 R-0 VEG STP0 (VI to PTx) Reference esign P# 00- Revision History SHEMTI SHEET ate uthor Version omments 0. ontents, Revision History Sept., 00 Tony W. Rev. Initial schematic. 0. Overview Oct., 00

More information

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N P REVISION REOR J SP88 0 - RE N_JK P 90-00_-POS TP # - Remove these components to stack north # - Populate these components to stack north Use k Resistors or adjust as needed Header - Molex 90-0 PITORS,

More information

THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia

THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia MicroL MicroLon.Sch Timers_nalog Timers_nalog.Sch IO ufferingsch IO uffering.sch Power Supply Power Supply.Sch Mitsubishi ackplane oard ate: THE UNIVERSITY OF NEWSTLE University rive allaghan NSW 0 ustralia

More information

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5. Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P

More information

U1-1 R5F72115D160FPV

U1-1 R5F72115D160FPV pf R NF_ X MHz, pf ON_XTL ON_EXTL R R NF_,,,, R NF_ R NF_ R R,,,, M M M_LK M_LK SEMn TI TMS TK TRSTn K R K R K R K R EXTL XTL M M M_LK M_LK TESTM SEMn TI TMS_WTX TK_WSK TRSTn_WRX U- RFFPV VREF VREFVSS

More information

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103 core Tiny0.sch M000 M000-etc.sch -etc.sch US HU US-HU.sch Tiny0SK 0 M_ VV V V V V V V V V V VN VSYN VLK VUS OTGI OTGM OTGP IN0 S_LK S_n S_T0 S_T OUT0 INT INT INT RST ( 红色 ) Tiny0 Tiny0 P Power Supply S

More information

OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP

OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP MU ROOTIS / ORO MU_NRESET R_[0..] R_[0..] R_ R_ R_ R_ R_ R_0 R_0 R_ R_ R_ R_ R_ R_ OTG_S_VUS OTG_S_N OTG_S_P OTG_S_I OTG_S_O OTG_S_PWR OTG_S_I OTG_S_N OTG_S_P OTG_S_O OTG_S_VUS UT_USER UT_USER SW_USER

More information

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2.

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2. +.0V IN J PJ-0 _ONN VUS JP JUMPERT VUS_FP 00 F FERRITE_E..V U TPS0 GN F TGN PF R.K % VP. R K %.V /.V ORE.V I/O U TPS0 JP VP JP HR VP_GL U TPS0 R.K LM0EM -. JP HR VORE_GL VORE. GN F TGN 0 PF R.K % R K %.

More information

Generated by Foxit PDF Creator Foxit Software For evaluation only.

Generated by Foxit PDF Creator Foxit Software   For evaluation only. I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software

More information

MT9V128(SOC356) 63IBGA HB DEMO3 Card

MT9V128(SOC356) 63IBGA HB DEMO3 Card MT9V(SO) IG H MO ard Page escription Page lock iagram Pinout Sensor Power Supply VideoOut_lock_Reset xternal Interface Rev Who ate escription Rev 0.0 jwrede 0/0/0 ase Schematic for ustom esign Rev 0. aralex

More information

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE

More information

Quickfilter Development Board, QF4A512 - DK

Quickfilter Development Board, QF4A512 - DK Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U

More information

Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09

Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09 Table of ontents Notes F & PL MRM, S & SFLSH OPTIONL PORT Rev X0 escription onvert into FSL template Revisions X ll parts FL //0 X Replaced U with the correct part //0 X X Replaced some components with

More information

PTN3356 Evaluation and Applicaiton Board Rev. 0.10

PTN3356 Evaluation and Applicaiton Board Rev. 0.10 E PTN Evaluation and pplicaiton oard Rev. 0.0 REVISION STORY : ------------------------------------- 0. June 0, 0 - ase on PTN_ONLY_REV.SN 0. July, 0 - OM changes due to long lead time items, LEs 0. July,

More information

Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA

Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive

More information

Reference Schematic for LAN9252-HBI-Multiplexed Mode

Reference Schematic for LAN9252-HBI-Multiplexed Mode Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information

CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2

CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2 VUS R V_IN V TO.V SETION.V SI_RX SI_TX 0E R PINOUT HEK MINISM00F- Resettable Fuse F 00m WHITE 00nF U GN EN IN IN TPS PG nc OUT OUT 0k R 0.V 00nF Power_Good MIRO US IS INITE S ON TX RX 0.uF VUS TR RI GN

More information

Renesas Starter Kit for RL78/G13 CPU Board Schematics

Renesas Starter Kit for RL78/G13 CPU Board Schematics Renesas Starter Kit for RL/G PU oard Schematics REV REF TE RWN Y 0.0 raft.0.0 TES.00 Release.0.0 YOI.0 Release 0.0.0 YOI PGE ESRIPTION INEX RL/G Microcontroller Switches, LEs, RESET, PSU E, Serial Port

More information

MSP430F16x Processor

MSP430F16x Processor MSP0x Processor V_. V_ V_. U Vcc Vcc R 0K SW, ETHER_T_00, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0 P.0/TLK P./T0 P./T P./T P./SMLK P./T0 P./T P./T /RST/NMI 0.u P UTTON_

More information

SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:

SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE: R 0K0 RST U S_ PF/0V PF/0V 0FS FS T T 0SLK N SOT N SOT Y mhz U LS0 debug port 0 do not stuff R WR S PS X/Y IN/IN IR 0IR MO J R M R 0K0 R0 K00 R 0K0 dsck dr dsi dso / G 0 U LS0 R 0K0 SI_RX SI_TX SI_LK TFS

More information

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B IS_IRQ V._0._0._0 O NOT IS_IRQ R K_0._0.0_0 J J.0_0 0 RV_RESET V RV_RESET V TP J IS TEST._0 TP V X [0..] [0..] GN GN -I/O H K RESRV V 0 IRQ V -V REQ -V U 0WS 0 0 V 0 -IO_HRY._0 GN -I/O H RY 0 -SMEMW EN

More information

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2 SEGMENT LE ISPLY R MUX MUX MUX MUX R nf SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ U R xt P P P P P P P P MX MX ss SL S P P P P P P P P nf S SEG_SL SEG_S SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_I_SL_

More information

SCHEMATIC REV. DRAWING NO. 9268CE01C REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O REV JP# * SEE ASSEMBLY INSTRUCTIONS

SCHEMATIC REV. DRAWING NO. 9268CE01C REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O REV JP# * SEE ASSEMBLY INSTRUCTIONS THIS RWING IS THE PROPERTY OF NLOG EVIES IN. IT IS NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR USE IN FURNISHING INFORMTION TO OTHERS, OR FOR NY OTHER PURPOSE ETRIMTL TO THE INTERESTS OF NLOG EVIES.

More information

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT LTER YLONE III EP evelopment & Education OR SHEMTI ONTENT PGE TOP MEMORY OVER PGE, TOP SRM,FLSH 0 ~ 0 0 ~ 0 ISPLY VG, LE, SEGMENT 0 ~ 0 IN/OUT LOK, PS, RS, UTTON, SWITH, ONNETOR,S R 0 ~ FPG yclone II EP

More information

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use

More information

Sheet_Symbol_Overspeed. HA_Vel_Feedback Dec_Vel_Feedback. HA_Overspeed_N Dec_Overspeed_N

Sheet_Symbol_Overspeed. HA_Vel_Feedback Dec_Vel_Feedback. HA_Overspeed_N Dec_Overspeed_N NOTES: ISION LOK. Unless otherwise stated: Resistors are mw, % tolerance. apacitors are V, % tolerance.... J Port and Net Name scopes for this project are: Port NOT Global (connected via Sheet Symbols)

More information

PCB NO. DM205A SOM-128-EX VER:0.6

PCB NO. DM205A SOM-128-EX VER:0.6 V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V

More information

FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13

FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13 Table of ontents Title lock iagram KEZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Initial raft Revisions. Remove Motor ontrol onnector J. Remap J, J, J, J pinout. dd one series resister

More information

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1. R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H

More information

VREF XREF=1/A1,1/B2,7/A2 C103 AVDD 0.1U VDDCORE DRVDD VDDIO ENC+ ENC- AIN+ OVR EC2 XREF=2/B2 XREF=2/B2 XREF=2/B2 XREF=2/A1 XREF=1/A1,7/B1 XREF=2/B2

VREF XREF=1/A1,1/B2,7/A2 C103 AVDD 0.1U VDDCORE DRVDD VDDIO ENC+ ENC- AIN+ OVR EC2 XREF=2/B2 XREF=2/B2 XREF=2/B2 XREF=2/A1 XREF=1/A1,7/B1 XREF=2/B2 --00_: RV;E,F,G,H,J,K,L,M,N,P,R V;H,H,J,J,K,K,L,L,M,M,N,N,P,P V;,,,,,,,E,E,F,F,G,G SMOE MOE S EXP EXP EXP0 HIPI HIIPI HIPI HIPI0 EXTFILTER GN_ GN_0 IN- IN+ EN- EN+ VREF V_ES N RY PLK PULK LK SYN SYN SYN

More information

Sheet_Symbol_Overspeed. HA_Vel_Feedback Dec_Vel_Feedback. HA_Overspeed_N Dec_Overspeed_N

Sheet_Symbol_Overspeed. HA_Vel_Feedback Dec_Vel_Feedback. HA_Overspeed_N Dec_Overspeed_N NOTES: ISION LOK. Unless otherwise stated: Resistors are mw, % tolerance. apacitors are V, % tolerance... Port and Net Name scopes for this project are: Port NOT Global (connected via Sheet Symbols) Net

More information

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion

More information

LLP ATCA CARRIER PAGE:

LLP ATCA CARRIER PAGE: PG SHMTI SRIPTION PG FPG0 MIN NK, NK, NK, NK PG FPG0 MIN NK, NK PG FPG0 MIN NK, NK PG FPG0 MIN NK, NK0 PG FPG0 MIN NK, NK PG FPG0 MGT 0 PG FPG0 MGT 0 PG FPG0 MGT 0 PG0 FPG0 MGT 0 PG FPG0 MGT 0 PG FPG0

More information

ALEX +12VBUS PTC 1A J17 PTTOUT U1B 3V3 C IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR RUP3

ALEX +12VBUS PTC 1A J17 PTTOUT U1B 3V3 C IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR RUP3 F PT VUS J J V_LEX V LEX LEX_SPI_SO LEX_SPI_SO R R LEX_SPI_SK LEX_SPI_SK LEX_SPI_RX_LO LEX_SPI_RX_LO R LEX_SPI_TX_LO LEX_SPI_TX_LO R FW_PWR REV_PWR 0 LEX HR 0P LEX J HR P R PWR IN THRU HEER x/sm PTTOUT

More information

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766 OMMON_H_V MT (LQFP) V emo oard for Sanyo Slim H PUH INX & PO, ST F, SVO & MPG - MT MMOY - SM, FLSH/POM VIO OUT UIO WM NM TYP VI igital V SUPPLY V igital.v MT FV Servo.V MT LO_V Laser iode.v F V PIKUP H

More information

FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved

FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate

More information

DP CoiNel Technology Solutions LLP GND GND GND GND. ETH_RST is connected to P1.28 GND GND GND GND GND GND GND GND GND ED 1. Vcc O 3 GND IOGND 35

DP CoiNel Technology Solutions LLP GND GND GND GND. ETH_RST is connected to P1.28 GND GND GND GND GND GND GND GND GND ED 1. Vcc O 3 GND IOGND 35 V K R L FR nf nf Vcc E O MHZ_LK ENET_REF_LK ENET_MIO ENET_M MHZ_LK.K R Y OS_MHz LE_LK LE_SPEE LE_T nf is connected to P. ENET_TX ENET_TX ENET_RS ENET_RX ENET_RX ENET_REF_LK ENET_M ENET_MIO nf ENET_TX ENET_TX

More information

A Power, JTAG, LEDs FPGA_TCK FPGA_TDO FPGA_TMS FPGA_TRST FPGA_TDI nanofip_misc.sch

A Power, JTAG, LEDs FPGA_TCK FPGA_TDO FPGA_TMS FPGA_TRST FPGA_TDI nanofip_misc.sch opyright ERN. This documentation describes Open Hardware and is licensed under the ERN OHL v... You may redistribute and modify this under the terms of the ERN OHL v... (http://ohwr.org/ernohl). This documentation

More information

FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M.

FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M. Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Revisions Initial raft ate 0/0/ pproved M. NORMN Release to production 0/0/ M. NORMN X hanges made

More information

01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES

01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES Table of ontents 0 TITLE PGE 0 MU 0 EUG INTERFE 0 SUPPLY 0 POWER RIGE 0 MOSFET RIVERS / VI SENSING utomotive Product Group 0 William annon rive West ustin, T 9 esigner:. ZUZEK rawn by:. ZUZEK pproved:

More information

CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H

CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H V N N V N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H N_L N_L J ON N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H

More information

Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11

Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11 Table of ontents Notes lock iagram isplay and Tower onnectors MU & apacitive Touch kt Rev X X escription Revisions Initial Release ate -JUL- pproved hanged Power L colours-jul- Removed J and J dded J &

More information

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board ZRMZN0000KITG rimzon evelopment oard Kit PUG000-0 Product User Guide Introduction Zilog s ZRMZN0000KITG rimzon evelopment oard Kit is designed for use as a target with the rimzon In-ircuit Emulator (ZRMZNIE0ZEMG).

More information

S08P-LITE. 1 Title Page 2 Block Diagram 3 MCU & Arduino Headers 4 OSBDM & Power Supply 5 On-board Peripherials S08P-LITE. 23-Jun-17. V3.

S08P-LITE. 1 Title Page 2 Block Diagram 3 MCU & Arduino Headers 4 OSBDM & Power Supply 5 On-board Peripherials S08P-LITE. 23-Jun-17. V3. Title Page lock iagram MU & rduino Headers OSM & Power Supply On-board Peripherials Revisions Rev escription ate -Jun- V.0 -Feb- pproved Microcontroller Product Group 0 William annon rive West ustin, T

More information

Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.

Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information. PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional)

More information

FREEDOM KL26Z. Table of Contents 1 Title 2 Block Diagram 3 KL26Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply FRDM-KL26Z.

FREEDOM KL26Z. Table of Contents 1 Title 2 Block Diagram 3 KL26Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply FRDM-KL26Z. Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev Revisions & hange Log escription ate Initial raft Feb// pproved listair * MU Pin assignments changed for Feb// listair

More information

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1 isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty

More information

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector. R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument

More information

SCHEMATIC AD9265 CMOS EVALUATION BOARD REV. DRAWING NO. AD9265CE01A REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O

SCHEMATIC AD9265 CMOS EVALUATION BOARD REV. DRAWING NO. AD9265CE01A REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O THIS RWING IS THE PROPERTY OF NLOG EVIES IN. IT IS NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR USE IN FURNISHING INFORMTION TO OTHERS, OR FOR NY OTHER PURPOSE ETRIMENTL TO THE INTERESTS OF NLOG EVIES.

More information

DNI = DO NOT INSTALL PLACE R3, R9, R47 & R49 ON THE TRACE - NO STUB R18 TO SHARE PADS W/ T5 R18 0. Date: Tuesday, March 26, 2013

DNI = DO NOT INSTALL PLACE R3, R9, R47 & R49 ON THE TRACE - NO STUB R18 TO SHARE PADS W/ T5 R18 0. Date: Tuesday, March 26, 2013 = O NOT INSTLL J INP S J S IN IN+ IN- R R T T-T+ INP IN.uF V.uF V T T-T+ INPP IN.uF.uF IN_P.uF IN_ R. R. R. R..pF INP IN SH SH PLE R, R, R & R ON THE TRE - NO STU J S INP J S IN IN- IN+ R R T T-T+ IN INP.uF

More information

CONTENTS: REVISION HISTORY: NOTES:

CONTENTS: REVISION HISTORY: NOTES: ONTENTS: PGE - ONTENTS PGE - POWER, XOS PGE - SI, SI, JTG PGE - S/eMM, US, HMI, GPIO, OMPOSITE PGE - SOIMM REVISION HISTORY: V.0 - /0/0 NOTES: These reduced schematics omit core SMPS and LPR circuitry

More information

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES: +V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R0 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V 0.uF U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V

More information

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0 Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP

More information

NOTE: This page is a hierarchical representation of the design. Only the connectors are physical components.

NOTE: This page is a hierarchical representation of the design. Only the connectors are physical components. NOTES: ISION LOK. Unless otherwise stated: Resistors are mw, % tolerance. apacitors are V, % tolerance.... Port and Net Name scopes for this project are: Port NOT Global (connected via Sheet Symbols) Net

More information

PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]

PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31] V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH

More information

X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies

X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies Table of ontents lock iagram Type- onnector US/US PTN0 P TP Shield Headers P Source and Sink LS V, V0, V Supplies Rev escription ate pproved Prototype Release -Mar- K ring up to NL and make updates requested

More information

HF SuperPacker Pro 100W Amp Version 3

HF SuperPacker Pro 100W Amp Version 3 HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project

More information

Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page

Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page Intel Edison reakout Sept/0 V to V rick Power Supply V power supply and battery recharger SPI GPIO Intel Edison PWM I S URT 0 0" header US 0TG URT Level Shifter URT US FTI P P lient US Micro Type- lient

More information

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES: +V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V SHN 0

More information

Host MSP430. dacqs_host_board 12/7/2016 9:26 PM. U1 Value +3V3 AVCC_HOST UART_1_TX UART_1_RX MSP_SCLK UART_2_TX UART_2_RX CUTDOWN_EN MSP_SS

Host MSP430. dacqs_host_board 12/7/2016 9:26 PM. U1 Value +3V3 AVCC_HOST UART_1_TX UART_1_RX MSP_SCLK UART_2_TX UART_2_RX CUTDOWN_EN MSP_SS +V Host MSP +V R MSP_SS MSP_MOSI MSP_MISO V_HOST MOTOR_T_VSNS_ OMMS_MOSI OMMS_MISO OMMS_SLK OMMS_SS URT TX URT RX V V V V P._T._M_RTLK VRF-_VRF- P._T._TLK_OUT VRF+_VRF+ P._T._TLK_OUT P._T._UST P._T._UST

More information

XIO2213ZAY REFERENCE DESIGN

XIO2213ZAY REFERENCE DESIGN XIOZY REFERENE ESIGN XIOZY Reference Size ocument Number Rev ate: Wednesday, September, 00 Sheet of TP+ TP- TP+ TP- TPIS TP+ TP- TP+ TP- TPIS TP0+ TP0- TP0+ TP0- TPIS0 REFLK+ REFLK- V_ V_ V_ORE PLLV_ORE

More information

MUSIC. California Institute of Technology. HEMT Power Supply Precision Voltage Source. D. Miller 8/17/2011 REVISION RECORD LTR DATED: C31 5V_ID 10K

MUSIC. California Institute of Technology. HEMT Power Supply Precision Voltage Source. D. Miller 8/17/2011 REVISION RECORD LTR DATED: C31 5V_ID 10K REVISION REOR EO NO: PPROVE: TE: V_I R 0K.V_REF V 0.uF _SHN V_IN GN GN U GN V_OUT_F V_OUT_S GN LT 0uF R 0k 0uF IN IN VOS_TRIM VOS_TRIM U N OPE OUT.V_REF R 0k 0uF IN IN VOS_TRIM VOS_TRIM U N OPE OUT 9 00pF

More information

CD300.

CD300. 00 Service Information www.laney.co.uk 9 9 -V J R9 N N N R R K K U/0V I R K U/0V R R R K K K N N R0 V U/0V 0 U/0V R 0K R 0K U/0V W 00K R9 M I R 00 U/0V 9 W W0K R 0K R K 0 0 R K W W0K K R0 MP K U/0V R 0K

More information

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used!

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used! JP RS_SELET V For max ROUT is low when RIN is disconnected enabling the MX (RS-) This will not work if MX is used! V On Front Panel -F (To Pg.) RS- RE_ RE_ RV_Y RV_Z 0.uF V U MXUK STR U- H G U MX 0 Y Z

More information

[1] [1] C7 10nF. C4 10nF SCL [2] SDA [2] CS_SD PWR_PRSNT [4] INT_BTN0 [2] INT_BTN1 [2] LOADER_EN [4] [1] TXLED [1] J11 [1] RST +3V3 RST

[1] [1] C7 10nF. C4 10nF SCL [2] SDA [2] CS_SD PWR_PRSNT [4] INT_BTN0 [2] INT_BTN1 [2] LOADER_EN [4] [1] TXLED [1] J11 [1] RST +3V3 RST 0 [] [] [] [] [] [] [] [] [] [] [] [] MOSI MISO SK 0 H H N_MS TMS RX TX SL J P_MOSI P_MISO P_SK P_ P_IO0 P_IO P_IO P_ P_ 0 P0_GN P_NT P_GN/NT P_RXL/SS P_TXL P_IO P_(SL) P_(S) P_ P_0 0 P0_ P_ P_IO P_R+

More information

20-JUNE-14 SCHEMATIC HSC REV. DRAWING NO.

20-JUNE-14 SCHEMATIC HSC REV. DRAWING NO. THI RWING I THE PROPERTY OF NLOG EVIE IN. IT I NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR UE IN FURNIHING INFORMTION TO OTHER, OR FOR NY OTHER PURPOE ETRIMTL TO THE INTERET OF NLOG EVIE. THE EQUIPMT

More information

HIgh Voltage chip Analysis Circuit (HIVAC)

HIgh Voltage chip Analysis Circuit (HIVAC) ate: esigner: RWING NO: SLE: SHEET: OF TOP MK HIgh Voltage chip nalysis ircuit (HIV) March H_I_RSEL H_I_RSEL H_I_SEL H_I_ H_I_ H_I_ H_I_SEL H_I_SW H_I_S H_I_S H_I_S H_I_P H_I_P H_I_P H_I_P H_I_PSH H_I_PSL

More information

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface.

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface. S J TXR0 TXR TXR TXR[:0] TXR TXR LK TX[:0] TX0 TX TX0 TX TX TX TX TX TX TX TX TX TX TX TX TX R 0K R 0K J J0 PIV R 0K TXPR R0. H/E0 H/E H/E TXLV TXSO J J HRST HLK HPERR HGNT HISEL HEVSEL HSTOP HTRY HIRY

More information

A_SYNCOUT1_P A_SYNCOUT1_N A_SYNCOUT2_P A_SYNCOUT2_N A_SYNCOUT3_P A_SYNCOUT3_N

A_SYNCOUT1_P A_SYNCOUT1_N A_SYNCOUT2_P A_SYNCOUT2_N A_SYNCOUT3_P A_SYNCOUT3_N ate: //00 heet of File: :\User\..\MFO.choc rawn y: NIN_P NIN_N NOUT_P NOUT_N N_N N_P LE OLK_P OLK_N NTROUT_P NTROUT_N IN_P LK_P LK_N NV_P IN_N NV_N VO MFO.choc TK TI TO TK TI TO LK _IN ONE HWP INIT_ M

More information

ALEX +12VBUS PTC 1A J17 PTT U1B. 126 IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR. IO_VB1N1_9/DIFFIO_L7p/DQS2L/CQ3L/CDPCLK0 RUP3

ALEX +12VBUS PTC 1A J17 PTT U1B. 126 IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR. IO_VB1N1_9/DIFFIO_L7p/DQS2L/CQ3L/CDPCLK0 RUP3 F PT VUS J J HEER X V_LEX V LEX LEX_SPI_SO LEX_SPI_SO R R LEX_SPI_SK LEX_SPI_SK LEX_SPI_RX_LO LEX_SPI_RX_LO R LEX_SPI_TX_LO LEX_SPI_TX_LO R FW_PWR REV_PWR 0 LEX HR 0P LEX J HR P R PWR IN THRU FW_PWR REV_PWR

More information

ADC IF1_P IF1_N INT_OSC_EN INT_OSC_EN ADC_PWDN ADC_PWDN INT_OSC_EN ADC_PWDN UC_CTRL[1-2] UC_DATA[0-7] FPGA_PROG[1-5] RF_POWER_DET

ADC IF1_P IF1_N INT_OSC_EN INT_OSC_EN ADC_PWDN ADC_PWDN INT_OSC_EN ADC_PWDN UC_CTRL[1-2] UC_DATA[0-7] FPGA_PROG[1-5] RF_POWER_DET MIXER FPG RF RF_MP_OUT RF_MP_OUT RF_POWER_ET RF_MP_ MIXER LOP LON IF_P IF_N IF_P IF_N T_OS_EN _PWN IF_P IF_N T_OS_EN _PWN _LK _[0-] _OR _LK _[0-] _OR LK_REF _LK _[0-] _OR LK_REF RF_G_TRL RF_G_TRL RF_G_TRL

More information

P&E Embedded Multilink Circuitry

P&E Embedded Multilink Circuitry MP PWM_LE MP PWM_LE.Sch MP Power MP Power.Sch MP USER_LE MP USER_LE.Sch P&E Embedded Multilink ircuitry MP MU MP MU.Sch MP_9_Temp_Sensor MP_9_Temp_Sensor.Sch RESET KG RESET_TO_TGT_PSS GN_TO_TGT_PSS TGT_TX

More information

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP

More information

All use SMD component if possible

All use SMD component if possible R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off

More information

SCHEMATIC REV. DRAWING NO. 9649EE01 REVISIONS JUMPER TABLE CONTROL CHART A A DE N V C L O

SCHEMATIC REV. DRAWING NO. 9649EE01 REVISIONS JUMPER TABLE CONTROL CHART A A DE N V C L O THIS RWING IS THE PROPERTY OF NLOG EVIES IN. IT IS NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR USE IN FURNISHING INFORMTION TO OTHERS, OR FOR NY OTHER PURPOSE ETRIMTL TO THE INTERESTS OF NLOG EVIES.

More information

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7 Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM

More information

FX18 DDR0/DDR1. PCIe/SD/SPI/CONFIG

FX18 DDR0/DDR1. PCIe/SD/SPI/CONFIG ate: feb 0 Kiad... ev: V Size: Id: / Title: alatea ile: alatea.sch Sheet: / License: Y-S PowerSypply PowerSypply.sch X NK()/NK(X) 0/ PIe/S/SPI/ONI NK()/NK0(X)/TP P OUPLIN POW SUPPLY.sch 0_[0..] 0_[0..]

More information

SYMETRIX INC th Avenue West Lynnwood, WA USA

SYMETRIX INC th Avenue West Lynnwood, WA USA ENE MI J XLR-FEMLE NOTE: ENE MI R K00 R K00 J (h ) isables phantom power for all mics. Remove R and/or R to disable phantom power for ense Mic and/or only. J XLR-FEMLE NP NP 0 NP R K00 R K00 NP R 0 NP

More information

Desired Part Placement. Max current set to 3A (motor Drive is 2.5A) SCI-DRV8814-MVK Mike Claassen B1 Dawn Ritz 40V. VDC_In GND. Board Test Points TP1

Desired Part Placement. Max current set to 3A (motor Drive is 2.5A) SCI-DRV8814-MVK Mike Claassen B1 Dawn Ritz 40V. VDC_In GND. Board Test Points TP1 SI_x_NLG_H_[:] P P SI_x_SPI_MISO SI_x_SPI_MOSI SI_x_SPI_LK SI_x_SPI_S FE/SI_OM_ FE/SI_OM_ FE/SI_OM_ FE/SI_OM_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_

More information

R5 330K R49 100K Q4 BC549 R12 2K2 U2B TL074 R50 100K R28 3K3. VR7 47KB via J38 R48 100K C BASSDRUM_TRIG. VR6 10K via J39 R29 100K R51 22K Q11 BC559

R5 330K R49 100K Q4 BC549 R12 2K2 U2B TL074 R50 100K R28 3K3. VR7 47KB via J38 R48 100K C BASSDRUM_TRIG. VR6 10K via J39 R29 100K R51 22K Q11 BC559 00 - SS RUM SSRUM_TRIG nf R K R K N R R K R 0 R K R K nf N R R K 0.uF EY R K R 0K R VR via J R U TL0 R R0 R VR via J EPTH R U TL0 R K PITH VR K via J R R K 0 R 0K R K nf N U TL0 R K R0 K R K R ISTORTION

More information

RTL8211DG-VB/8211EG-VB Schematic

RTL8211DG-VB/8211EG-VB Schematic RTL8G-V/8EG-V Schematic REV..8 Page Index. Page. PHY. MI. M. Power. History RTL8G/8EG Size ocument Number Rev.8 TITLE PGE ate: Sheet of External clock and rystal RTL8G/8EG GMII/RGMII Interface LK_M ENSWREG

More information

D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF.

D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF. POWER_KEY POWER_OFF US_IN WKEUP H_ET HG_STTUS PLYKEY +VRT VT VUS +VRT LI_.V LI_.V VUS VT VTT VTT VTT +V +V +V +V VTT V +V T uf uf R k R k uf uf R k R k VIN VOUT U XPM U XPM Vbat ON ON ON ON KW ON/OFF KW

More information

SYMETRIX, INC th Avenue West Lynnwood, WA USA

SYMETRIX, INC th Avenue West Lynnwood, WA USA HNNEL INPUT LNE J XLRFEM L/UNL J /" TRS SIEHIN SEN/RETURN J /" TRS S/_IN_H R 00K0 0pF R K00 0pF 0 0pF R K00 0pF TO LOGMP INPUT R K0 0pF 0pF R K 0pF R K0 00PF.NP R K0 00PF R K0 U.NP R 00.0 HNNEL MSTER OUTPUT

More information