P50V +IN 4 -VS AD8065AR. Cap Semi SH_CLEAR. C19 Cap Semi 0.1uF R210. Res3 15K, 1% P50V U VS -IN P50V. Vout +IN -VS AD8065AR SUB_TO_ADC

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1 P0V PV J00 R_R R0 Res 00.uF JP0 Header R0 Res 0k 0 ode T 0.uF P0V R0 U0 Res.0K SH_UF 0R U0 OM V+ SH_MIN NO IN SH_SWITH SH_SWITH IN OM R0 GN NO Res 0 PI_ P0V R0 SH_MIN Res 0 0 pf mca SH_LER SH_LER U0 0R P0V SH_VIEO U00 0R U0 0R P0V SH_TO_ SH_TO_SU 00 ode S0 R0 Res 0 ohm R0 Res 0 ohm (NP) L_IFF_IN L_SING_IN P0V UT UT U0 0R P0V JP00 Header _SU FPG UF SH_TO_SU JP cheesy flter :P VI_ R Header Res _R R Res K, % R Res K, % R Res K, % R0 RPot 00 J VUT R_R _P R0 Res K, % U0 0R P0V SU_TO_ R00 RPot k 0.uF R0 Res K, % U0 P0V 0R 0 0.uF PV 0.uF 0 ode S0 0.uF 0.uF R Res 0 ohm R Res 0 ohm (NP) 0.uF 0.uF R_IFF_IN R_SING_IN ate: //00 Sheet of Fle: M:\projects\analog_support.SHO rawn y:

2 PV PV 00 0.uF U0 OE Vcc P00 GNOUT OSILLTOR SM_R _LK_EXT _LK_INT _LK JP0 Header 0 0.uF U0 OE Vcc GN OUT OSILLTOR SM_R _LK_EXT _LK_INT _LK JP0 Header R Res 0 (NP) P0 R Res 0 (NP) ate: //00 Sheet of Fle: M:\projects\clocks.SHO rawn y:

3 track and hold unty gan buffers expt wth res, wth current mrror -bt hyst. reset swtch voltage subtractor dummy H area for experments L_VREF L_IFF_IN L_SING_IN S S L_ R0 00 ohm % L_ R0 00 ohm % L_ R 00 ohm % L_ R 00 ohm % L_0 R 00 ohm % L_ R 00 ohm % SE_N L_ SWE_N R0 00 ohm % L_ R 00 ohm % L_ R 00 ohm % L_ R 00 ohm % L_ R 00 ohm % L_ R 00 ohm % L_ R 00 ohm % L_ R 00 ohm % L_0 R 00 ohm % _L0P_/VRN L0N_/VRP LP_/VREF LN LP LN_/VREF L0P L0N LP LN LP LN LP LN LP LN LP LN L0P L0N_/VREF L0P_/VREF L0N LP LN LP LN_/VREF LP LN LP LN LP LN L0P L0N LP LN_ /VREF L0P_/VRN L0N_/VRP_ FPG_P_ST_N_IN FPG_P_SEL_N_IN FPG_P_0 FPG_P_RV_N FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_USY_N_OUT FPG_P_K_OUT /VREF_0 _L0N_0/VRP_0 _L0P_0/VRN_0 /VREF_0 _LN_0 _LP_0 _LN_0 _LP_0 _L0N_0 _L0P_0 _LN_0 _LP_0/VREF_0 _LN_0/GLK _LP_0/GLK NK NK _L0P_/S L0N_/RWR L0P_/VRN L0N_/VRP LP LN_/VREF LP_/ _LN_/ _LP_/ _LN_/ _LP_/GLK _LN_/GLK /VREF_ 0 _LN_/GLK _LP_/GLK _LN_/VREF LP LN LP LN LP L0N_/VREF L0P L0N_/VRP L0P_/VRN_ NK 0 NK NK FPG_P_EN_OUT SH_SWITH FPG_P_IR FPG_P_ERR_OUT FPG_P_UTO_N_IN FPG_P_INIT_IN FPG_P_SEL_OUT PV bts0-, trm, x -bt NK JP00 R00 Header Res. % NK NK _LP_/GLK0 _LN_/GLK _LP_/OUT/USY _LN_/INIT_ /VREF L0P_/ _L0N_/ _LP_/ _LN_/IN/0 _LP LN_ /VREF L0P_/VRN L0N_/VRP_ /VREF_ FPG OUT R0 Res. % FPG RW _L0N_/VRP L0P_/VRN_ /VREF LN LP L0N L0P LN LP LN LP LN_/VREF LP LN LP LN LP L0N L0P_/VREF L0N_/VREF L0P LN LP LN LP LN LP_/VREF LN LP LN LP L0N L0P LN LP LN LP_/VREF L0N_/VRP L0P_/VRN_ U0 XS00-PQ S S S R_SING_IN R_IFF_IN R_ R_ R_ R_ SOE_N R_0 R_ S R_ R_ R_ R_ R_ R_ R_ R_ R_0 0 Q00 HF0 R_VREF R0 R0 R0 R0 R0 R R R R R R R R R0 R R 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % 00 ohm % FPG OUT PV R0 RPot K PV R0 RPot K U00 0R U0 0R U0 0R P0V P0V P0V FPG UF R_VREF L_VREF _K SRM_LK _LK R 0 R 0 R 0 S S S S S S0 S S S P Rule SRM_LK _LK _ K PROG_INIT_N SH_LER S0 S P Rule PROG_IN S S Impedance onstrant [Mn = 0.00 Max = 0.00 ] Routng Topology [Topology - asy-smple] ate: //00 Sheet of Fle: M:\projects\fpga_man.Schoc rawn y:

4 ate: //00 Sheet of Fle: M:\projects\fpga_support.SHO rawn y: M M0 M ONE 0 LK 0 TO TK TMS 0 HSWP_EN 0 PROG_ 0 TI 0 VINT 0 VINT VINT VINT VUX VUX VUX VUX VUX VUX VUX VUX GN GN GN GN GN 0 GN GN GN GN GN GN GN GN GN GN 0 GN GN GN GN GN GN GN GN GN 0 GN GN GN GN 0 VO_ VO_ VO_ VO_ VO_ 0 VO_ VO_ VO_ VO_ 0 VO_ VO_ VO_ VO_ VO_ VO_0 VO_0 0 U0 XS00-PQ0 0 LK TI TMS TK F OE/RES E 0 GN EO TO VINT VO VJ 0 U0 XF0S PV PV PROG_IN PROG_LK PROG_LK JTG_TI JTG_PRM_TO JTG_PRM_TO JTG_TO JTG_TK JTG_TK JTG_TMS JTG_TMS PROG_PROG_N PROG_PROG_N PROG_INIT_N PROG_ONE PROG_ONE.K R Res.K R Res PV PV.K R0 Res PV PV FPG_M0 FPG_M FPG_M PV S00 SW-IP FPG_HSWP_EN FPG_M0 FPG_M FPG_M FPG_HSWP_EN PV PV 0.uF 0 0.uF 0.uF 0.uF 0.uF.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0 0.uF 0.uF.uF.uF 0.uF 0 0.uF 0 0.uF 0 0.uF 0 0.uF 0 0.uF 0 0.uF 0.uF.uF.uF.uF 0.uF 0 PV PV PV r r r r r r r r RP00 TS_0 00 R Res 00 (NP) R Res 00 (NP) R Res JTG_TK P Rule JTG_TMS JTG_TI P Rule P Rule P Rule Supply Nets [Voltage =.00] P Rule Supply Nets [Voltage =.00] P Rule P Rule GN Vref GN TMS/PROG GN TK/LK GN TO/ONE GN TI/IN 0 GN N/N GN N/INIT J00 XILINX_JTG_HR JTG_TO JTG_TI JTG_TK JTG_TMS PV

5 ate: //00 Sheet of Fle: M:\projects\mem_dac.SHO rawn y: QPc Qc Qc Qc Qc Qc Qc 0 Qc Qc Qd Qd 0 Qd Qd Qd Qd Qd Qd QPd 0 MOE S S S S S S0 NU NU 0 NU S S S S S S S S 0 QPa Qa Qa Qa Qa Qa Qa 0 Qa Qa ZZ Qb Qb 0 Qb Qb Qb Qb Qb Qb QPb 0 S S S REXP V/L OE KE R/W LK 0 Wa Wb Wc Wd E E E S S 00 U0 Y SRM_LK SWE_N SOE_N SE_N cutally WE_N ctually S_N ctually SP ctually V PV PV PV PV 0.uF 0 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0 0.uF 0 0.uF 0 PV S0 S S S S S S S S S S0 S S S S S S S S FPG_P_0 FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ 0(LS) V OM 0 LKV LK+ LK- LKOM MOE MOE V V OM UT 0 UT OM REF FSJ SLEEP OM (MS) 0 OM PLE U0 FPG_P_0 FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ PV PV_ PV 0 ohm R Res _K 0.uF 0.K R Res UT UT. ohm R Res. ohm R Res FSJ REF.uF, 0V 0 0.uF 0 000pF 0 PV_ 00 ohm L00 Inductor Iron PV S0 S S S S S S S S S S0 S S S S S S S S _K SE_N SRM_LK SWE_N SOE_N

6 PV JP00 Header PV_S 00 0uF, 0V 0 0.0uF 00mm^ copper top/bottom for HS U00 OUT IN SENSE/J GN GN GN YP SHN LTS-. PV 0 uf, 0V P0V 0uF, 0V 0.0uF 00mm^ copper top/bottom for HS U0 OUT IN SENSE/J GN GN GN YP SHN LTS- uf, 0V PV P connector PS0000UPS-PP Header JP0 Vn Vbas T On/Off GN U0 PQ0FZZZ 0 ap Pol 0uF, 0V JP0 PWR. F00 RW_PWR 0 SM0 0.uF, 0V PV 00 0 PV 0 uf, 0V L00 Inductor Iron 00 ohm VIN_PV 0 uf, 0V U0 +Vn - GN * L0 PV_RW PV_S Inductor Iron 00 ohm 0 ap Pol uf, 0V 0uF, 0V verfy + to footprnt correspondence 0 ap Pol 0uF, 0V PV 0 uf, 0V 0 uf, 0V PV caps across pns, ate: //00 Sheet of Fle: M:\projects\power.SHO rawn y:

7 ate: //00 Sheet of Fle: M:\projects\pport.SHO rawn y: 0 0 J00 onnector P_ST_N_IN P_UTO_N_IN P_0 P_ P_ P_ P_ P_ P_ P_ P_ERR_OUT P_INIT_IN P_SEL_N_IN P_K_OUT P_USY_N_OUT P_EN_OUT P_SEL_OUT OE T/R 0 0 V 0 GN 0 U0 MVHMS PV V GN Y 0 U00E SNVH U00 SNVH U00 SNVH U00 SNVH U00F SNVH V GN Y U0F SNVH U0 SNVH 0 U0E SNVH U0 SNVH P_R_ERR_OUT P_R_K_OUT P_R_USY_N_OUT P_R_EN_OUT P_R_SEL_OUT P_ERR_OUT P_K_OUT P_USY_N_OUT P_EN_OUT R00 Res P_SEL_OUT FPG_P_ERR_OUT FPG_P_K_OUT FPG_P_USY_N_OUT FPG_P_EN_OUT FPG_P_SEL_OUT P_R_0 P_R_ P_R_ P_R_ P_R_ P_R_ P_R_ P_R_ P_ P_ P_ P_ P_ P_ P_ P_0 PV PV P_ST_N_IN P_UTO_N_IN P_SEL_N_IN P_INIT_IN FPG_P_ST_N_IN FPG_P_UTO_N_IN FPG_P_INIT_IN FPG_P_SEL_N_IN FPG_P_0 FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_ FPG_P_[0..] FPG_P_RV_N FPG_P_IR onsder puttng R- network on nputs look n dgkey catalog S00 SW-P S0 SW-P S0 SW-P S0 SW-P P_ST_N_IN P_UTO_N_IN P_INIT_IN P_SEL_N_IN 00 ode T PV S0 GRN S0 GRN S00 RE S0 RE S0 M S0 GRN 00 LEs 0 R0 Res 0 R0 Res 0 R0 Res 0 R0 Res 0 R0 Res 0 R0 Res P_SEL_OUT P_EN_OUT P_USY_N_OUT P_K_OUT P_ERR_OUT PROG_ONE S0 LU 0 R0 Res 0.uF 00 0.uF 0 0.uF 0 PV r r r r r r r r RP0 TS_0 r r r r r r r r RP0 TS_0 r r r r r r r r RP0 TS_0 r r r r r r r r RP00 TS_0 PV FPG_P_K_OUT FPG_P_ERR_OUT FPG_P_USY_N_OUT FPG_P_EN_OUT FPG_P_SEL_OUT FPG_P_RV_N FPG_P_IR FPG_P_[0..]

8 U_analog_support analog_support.sho U_pport pport.sho U_clocks clocks.sho U_fpga_man fpga_man.schoc U_mem_dac mem_dac.sho U_fpga_support fpga_support.sho U_power power.sho ate: //00 Sheet of Fle: M:\projects\top.Schoc rawn y:

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