PCLKS SYNCHS PDATS[3:0] PCODES[3:0] STATCLKS CMDCLKS PCLKW SYNCHW PDATW[3:0] PCODEW[3:0] Sheet_2 CMDCLKS STATCLKW CMDDATW STATDATW PDACK[1:0]

Transcription

1 STTTW STTLKW POW[:0] PTW[:0] SYNHW PLKW Sheet_ STTTS STTLKS POS[:0] PTS[:0] SYNHS PLKS Sheet_ Spareates PLKS SYNHS PTS[:0] POS[:0] STTLKS STTTS MLKS MTS Sheet_ PLKW PLKS SYNHW SYNHS PTW[:0] PTS[:0] POW[:0] POS[:0] Sheet_ MLKS STTLKW MLKW MLKS STTLKS MTS STTTW MTW MTS STTTS PRQ[:0] PK[:0] T MMS IOS PIRQ[:0] L[:] S[:0] S[:0] SMMR SMMW SMMR SMMW PK[:0] PK[:0] L[:] S[:0] S[:0] L[:] S[:0] S[:0] SMMR SMMW IF_ntl RSTS MMR RSTS RSTS MMW RSTW RSTW RSTW IS_&_PWR_IF MMR N MMR MMW SH MMW PRQ[:0] PRQ[:0] N L N T_IF SH T SH T USLK L L PIRQ[:0] FRMSYNH XTRST XTRST RSTRV PIRQ[:0] USLK USLK RSTRV RSTRV MMS IOS FRMSYNH MMS IOS FRMSYNH MLKW MTW MLKW MTW PLKW SYNHW PTW[:0] POW[:0] STTLKW STTTW XTRST TU Interface oard Schematic Size ocument Number Rev ate: Monday, ecember, 00 Sheet of

2 PIRQ[:0] T ONX S[:0] N S[:0] L[:] IRQ IRQ IRQ J PIRQ0 PIRQ PIRQ S J RSTRV S S S 0 0 S SH L S L S L S0 XTRST J PK0 S PK IS_ S S NOT: xternal Reset reuses the +V pin L ONX S of the P0 connector. It is jumped to S 0 0 J the push-button reset on the PU card. S0 PRQ[:0] Place one 0uF cap next to connector, 0UF V 0UF V and one on other side TU Interface oard Schematic - IS & Pwr onnectors J -M board Size ocument Number Rev see Sh. ONX PRQ0 PRQ K RQ K RQ 0 0 PK[:0] L0 L L L S S S0 S S S S S MMR MMW IOS MMS S S S S S S S S S S0 S S S S 0 0 J IS_ 0 0 NOT: Power, received on this board (V), is routed to the Motherboard via the P-0 connector. SMMW SMMR USLK ate: Monday, ecember, 00 Sheet of

3 pattern R0 0 implemented.0m N J U0 U0 0 HWRSTL R ON 0.uF.K J ON0 J TST onnector if it fits... not needed if FP TP TK TO TI TMS ON Xilinx oundary Scan/onfig Tool R 0.0K Y N RSTS 0.uF PLKS SLK 0 PTS0 N OUT SYNHS 0 PTS[:0] PTS PTS OSILLTOR -.MHz 0 PTS 0 MTS MLKS STTLKS PIRQ0 U STTTS PIRQ[:0] 0 0 POS[:0] POS0 PIRQ XS0-PQ0I POS PIRQ 0 POS 0 PRQ[:0] PRQ0 POS PRQ PK0 FRMSYNH PK[:0] PK RSTW 0 0 L PLKW SH SYNHW 0 PTW0 0 PTW[:0] PTW PTW PTW MMR POW0 POW[:0] POW SMMR MMW 0 POW 0 POW T USLK 0 0 MLKW S MTW S S0 STTTW S STTLKW R R R S S - do not populate - do not populate - do not populate S 0 0 MMS S 0 0 IOS SMMW 0 0 S[:0] RSTRV ecouple PQ0 0PF - do not populate 0PF - do not populate 0PF - do not populate 0 Termination option for P0 bus J0 Locate near net destination at U Master Serial Mode: MO pin connects directly to ground - Jumper should be installed for JP configuration from tmel PROM S0 S S S S S S S 0 S S ON0 S S S S S S0 S 0.uF 0V 0.uF 0V 0.uF 0V 0.uF 0V S S0 S S S S R R R S R.K.K.K S 00 S S TP TP S 0.uF 0V 0.uF 0V 0.uF 0V 0.uF 0V S[:0] N L L U L L0 T 0 TP L LK L RST_O N L O L[:] SRN PRORM RY 0 0.uF 0V 0.uF 0V 0.uF 0V 0.uF 0V WP TML PROM onfiguration Option - WP 0 also generates the RST signal N (RY) used for programming TLVPL 0.uF 0V ON INIT LK IN TU Interface oard Schematic - ontrol 0.uF 0V 0.uF 0V 0.uF 0V 0 0.uF 0V Size ocument Number Rev see Sh. Monday, ecember, 00 ate: Sheet of

4 POSN0 R 0K U POS0 POS[:0] PTS[:0] R 0 U R PTSP0 PTS0 Y POSN[:0] K U R PTSN0 MLKSP MLKS Y R 0 R 0 MLKSN PTSP PTS Z Y R PTSN R 0 R U Y 0 PTSP 0 PTS Z Y R 0K R PTSN POSN POS MLKWP MLKW Y 0 R 0 R0 0 MLKWN PTSP PTS Z PTSN Y R R PTSN[:0] Y R 0 Z K PTSP[:0] M M U R 0K POSN POS onnect pins & to the ground plane using external layer vias MTS RSTS U 00 U R 0 R MTSN RSTSN PLKSP PLKSN SYNHSP SYNHSN R 0 R0 0 R 0 R 0 0 U Y Y Y Y PLKS SYNHS POSN R K R 0K R K U POS 00 M U onnect pins,, & to the ground or power planes using external layer vias STTLKSN R 0K U 0 STTLKS MTW MTWN R PTW[:0] R 0 R0 0 U PTWP0 PTW0 Y K 00 PTWN0 R 0 R 0 U PTWP PTW Y PTWN RSTW 0 RSTWN R 0 R UF 0 R PTWP 0 PTW Y R 0K PTWN STTTSN STTTS 00 R 0 R 0 PTWP PTW Y PTWN R0 PTWN[:0] R 0 K R PTWP[:0] 0K U FRMSYNH FRSYNHN U POW[:0] R R 0K POWN0 POW0 0 R POWN[:0] K R 0 U PLKWP Y PLKW PLKWN R 0 J U Y PLKSP R 0K 0 R POW 0 POWN RSTSN PLKSShield SYNHWP 0 PLKSN Y SYNHW SYNHWN STTTSN SYNHSP R 0 R0 SYNHSShield MTSN Y K SYNHSN STTLKSN PTSP0 MLKSP PTS0Shield Mlk0Shield PTSN0 MLKSN PTSP POSN[:0] POSN PTSShield M U POSN0 PTSN R 0K POSN PTSP POWN POW POSN PTSShield PTSN onnect pins,, & to the ground or power planes using external layer vias PTSP R PTSShield K 0 PTSN 0 ResetRtn PTSN[:0] 0 FrameSynRtn PTSP[:0] PLKWP 0 XTRSTN PLKWShield FRSYNHN PLKWN U SYNHWP R 0K SYNHWShield ssign W = amera 0; S = amera POWN POW SYNHWN RSTWN PTWP0 PTW0Shield STTTWN R PTWN0 0 PTWP MTWN K STTLKWN PTWShield PTWN MLKWP PTWP PTWShield MLKWN PTWN POWN[:0] U PTWP POWN0 R 0K PTWShield POWN STTLKWN 0 STTLKW PTWN 0 POWN 0 POWN N R R 00 XTRSTN XTRST PTWP[:0] K M PTWN[:0] 0 xternal Reset 0.uF 0V 0.uF 0V 0.uF 0V 0.uF 0V 0. uf onnection to P/0 N PU ard UF R 0K STTTWN STTTW M NOT: river signal shields are connected to chassis ground; receiver signal shields are unterminated R K Signals received withxx must be "reinverted" in the FP. amera (T signals);. JPL computer (Framesynch);. Telemetry Unit (XTRST) 0.uF 0V 0.uF 0V 0.uF 0V 0.uF 0V 0.uF 0V TU Interface oard Schematic - T Interface Size ocument Number Rev see Sh. Monday, ecember, 00 ate: Sheet of

5 JV U0 JV U 0 JV U 00 JV U0 JV U 0 JV UF 00 U JV U0 JV 0 0 JV0 U0F JV U 0 0 UF JV 0 Jump spare inputs to ground on component side, with a set of vias (so that etch can later be cut/jumped TU Interface oard Schematic - Spares Size ocument Number Rev see Sh. ate: Monday, ecember, 00 Sheet of