DB30 Top Level DB30 - Daughter Board Spartan3

Transcription

1 U ommon _ommon U_PSU PSU.SHO U_ypass_oard _ypass U_0_Hardware_Kit 0_Hardware_Kit.Schoc ate: 0 Top Level 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:6 PM 0_Top.Schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

2 PWRNET i GN NT7 GN U_PSU_MX8_V_LT PSU_MX8_V_LT V PWRNET i TP0 GN GN V V PWRNET PWRNET i i V V0 TP V TP V _M 0uF 0V Shared ypass aps _M 0uF 0V GN V0 U_PSU_MX8860_J PSU_MX8860_J VIN nfult VSET VOUT V V V PWRNET i V TP V0 RT 00K % PWRNET i TP V nalog power for the FPG VUX is set to a nominal.v by the feedback resistors. ate: Power Supply Top Level 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:6 PM PSU.SHO Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

3 V0 GN _PS 0uF 0V GN _PS.uF 0V 6_PS uf 0V R_PS 0R % Vfilt _PS 70pF 0V OMP 6 U_PS MX8EEE IN IN V SHN OMP LX LX LX LX F PGN PGN 6 8 LX L_PS u,, R, SM F R_PS K7 % R_PS 7K % GN R_PS K7 % 9 8_PS R_PS GN TOFF 7 0uF 0V TOFF 00K % FSEL 7_PS 0 REF_V uf V REF GN GN GN GN GN _PS uf 0V V GN _PS 0uF 0V ate: //008 Time: :0:6 PM Sheet of PSU_MX8_V_LT.Schoc Power Supply MX8 (V) 0 - aughter oard Spartan ssy: Revision: 07 ltium Limited L, Rodborough Road NSW 086 ustralia

4 VIN _L.uF 0V _L 0.0uF 0V U MX8860EU8+ IN OUT 7 6 nshn GN OUT nfult SET 8 R_L 00K % nfult VSET R_L 00K % Higher level has resistor (R) between VSET and VOUT. _L.uF 0V VOUT GN GN GN GN GN The voltage provided by the MX8860 linear regulator is determined by the addition of a resistor between VOUT and VSET. This additional resistor (R) is located on the higher-level schematic. The voltage produced by the MX8860 is calculated as follows: VOUT =. * ( + R / 00k) If R = 0k, If R = 00k, If R = 6k, VOUT =. * ( + 0k/00k) =.0 Volts VOUT =. * ( + 00k/00k) =.0 Volts VOUT =. * ( + 6k/00k) =.0 Volts Note that if VSET is grounded (on the higher-level schematic), VOUT=.8 Volts Note also that VIN must be a minimum of 0.8 Volts above VOUT. ate: Power Supply MX8860 (V) 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:6 PM PSU_MX8860_J.Schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

5 V _M 0uF 0V _M 0uF 0V GN These decoupling capacitors are intended to assist the voltage rails on the P - where the decoupling capacitors for the FPG are not close. ate: oard ypass apacitors 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:6 PM _ypass.schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

6 Top Level Schematic For aughter oard esign oth FPG-Only and FPG + MU This evice Sheet is the same for all designs. It relies on being instantiated in a project that contains a device-specific sheet named EVIES.Schoc. U_Memory_ommonus_aughteroard N_ommonMemory U_EVIES EVIES.Schoc U_Motheroardonnectors _Motheroardonnectors MEM US U_RESET_SW SLEEP_N SW U_RESET_SW SLEEP_N SW UZZER UZZER U_ommonMemory_Termination N_ommonMemory_Termination MEM N IP USER_LE USER N IP USER_LE USER JTG JTG I I U_SRM_K6R06V-T0T_6Kx6 SRM_6Kx6_TSOP KEYOR MOUSE KEYOR MOUSE SRM SRM RS RS SPI SPI U_SRM_K6R06V-T0T_6Kx6 SRM_6Kx6_TSOP LOKS PROGRM LOKS PROGRM SRM SRM TFT TFT EXT_ EXT_ EXT_ EXT_ EXT_ EXT_ U_aughteroard_LES _LES STTUS_LE STTUS_LE STTUS_LE ONE_WIRE P ONE_WIRE_I ONE_WIRE_P ONE_WIRE P ONE_WIRE_I ONE_WIRE_P ate: aughter oard Top Level 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:6 PM _ommon.schoc Sheet 6 of ltium Limited L, Rodborough Road NSW 086 ustralia

7 U_FPG FPG.SHO US SRM SRM MEM_OMMON SRM SRM U_RESET_SW SW UZZER N U_RESET_SW SW UZZER N IP USER_LE IP USER_LE USER USER I I STTUS_LE STTUS_LE KEYOR MOUSE RS TFT KEYOR MOUSE RS TFT EXT_ EXT_ EXT_ EXT_ EXT_ EXT_ SPI SPI ONE_WIRE P ONE_WIRE_I ONE_WIRE_P ONE_WIRE P ONE_WIRE_I ONE_WIRE_P LOKS PROGRM JTG LOKS PROGRM JTG SLEEP_N evice Specific Section of aughter oard esign This schematic sheet (plus any child sheets) will contain the device specific parts of any daughter board designs. This will include any FPG or MU devices as well as dedicated power supplies, connectors etc. ate: FPG, LEs and SRM Memory 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:6 PM EVIES.Schoc Sheet 7 of ltium Limited L, Rodborough Road NSW 086 ustralia

8 //008 :0:7 PM FPG.SHO ate: Revision: Sheet of Time: FPG onnections ssy: 0 - aughter oard Spartan ltium Limited L, Rodborough Road NSW 086 ustralia FPG_TK FPG_TI FPG_TMS FPG_TO FPG_PROGRM FPG_M0 FPG_M FPG_M FPG_LK FPG_ONE V FPG_PROGRM FPG_TO FPG_INIT FPG_PROG_PWR_ON SRM_NS SRM_[8..0] SRM_[..0] SRM_NHE SRM_NWE SRM_NOE FPG_ONE FPG_I FPG_I0 FPG_I FPG_I STTUS_LE FPG_I = 0x0 (Xilinx) TMS ONE M LK M0 M TK HSWP_EN TI PROG_ TO U_FPG_Power FPG_Non.Schoc FPG_ONE UGLK[..0] UGLK0 FPG_LK REF_LK FPG_LK FPG_IN FPG_INIT UGLK UGLK i Net lass i Net lass i Net lass i Net lass i Net lass i Net lass i Net lass UZZER UZZER N_RX N_TX IP[7..0] SL S SPI_LK SPI_IN SPI_OUT SPI_MOE SPI_SEL [..0] FPG_LK REF_LK FPG_LK FPG_IN FPG_ONE FPG_I[..0] FPG_INIT FPG_M[..0] FPG_PROG_LK FPG_PROG_PWR_ON FPG_PROGRM FPG_TK FPG_TI FPG_TO FPG_TMS FPG_LK ONE_WIRE_I ONE_WIRE_I SW[..0] ONE_WIRE P ONE_WIRE P EXTEN_0 RS_TX US_ S SL ONE_WIRE P EXTEN_8 EXTEN_9 EXTEN_0 EXTEN_ LE LE LE0 LE IP 9 NEXUS_TO EXTEN_7 EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_7 EXTEN_8 EXTEN_8 EXTEN_ RS_RTS RS_TS KLOK MOUSELOK EXTEN_6 EXTEN_7 U_TFT_IRQ U_TFT_POL U_TFT_MUX U_TFT_M U_TFT_ISP_ON SRM_NLE SRM_NHE LE LE7 IP0 IP LE LE6 IP EXTEN_9 EXTEN_6 EXTEN_ N_TX RS_RX KT MOUSET US_6 EXTEN_ EXTEN_8 EXTEN_6 EXTEN_ EXTEN_ EXTEN_0 EXTEN_7 EXTEN_ EXTEN_ EXTEN_ EXTEN_8 EXTEN_6 EXTEN_ EXTEN_ EXTEN_9 EXTEN_7 EXTEN_ EXTEN_ EXTEN_9 EXTEN_6 EXTEN_ EXTEN_ EXTEN_0 EXTEN_9 EXTEN_7 SPI_LK SPI_SEL SPI_MOE EXTEN_ EXTEN_ EXTEN_6 EXTEN_ EXTEN_8 EXTEN_7 EXTEN_ SPI_IN US_SRM_LK SPI_OUT EXTEN_8 EXTEN_0 EXTEN_9 EXTEN_ EXTEN_9 EXTEN_ EXTEN_ EXTEN_ EXTEN_8 EXTEN_ EXTEN_ EXTEN_ EXTEN_7 EXTEN_ EXTEN_0 EXTEN_6 EXTEN_6 EXTEN_7 EXTEN_ EXTEN_ EXTEN_9 EXTEN_8 NEXUS_TMS NEXUS_TK EXTEN_ NEXUS_TI EXTEN_ EXTEN_0 EXTEN_ EXTEN_ EXTEN_ EXTEN_6 EXTEN_ EXTEN_ IP U_TFT_LIGHT EXTEN_ EXTEN_ U_TFT_LUE i Net lass US_SRM_FEEK SRM_NS SRM_[8..0] SRM_[..0] SRM_NHE SRM_NWE SRM_NOE i Net lass R K7 % R K7 % R K7 % R K7 % R7 00R % R8 00R % R9 00R % R0 00R % R 00R % R 00R % R8 00R % R 00R % R 00R % R 00R % R0 00R % _LP_0/GLK6 _LN_0/GLK7 _LP_0/VREF_0 _LN_0 E _L0P_0 F _L0N_0 G _L9P_0 _L9N_0 _L8P_0 E _L8N_0 F _L7P_0 H _L7N_0 G H _L6P_0/VREF_0 _L6N_0 _LP_0 _LN_0 E _LP_0 F _LN_0 G H _LP_0 0 _LN_0 0 _LP_0 0 _LN_0 0 _L9P_0 E0 _L9N_0 F0 /VREF_0 G0 _L8P_0 9 _L8N_0 9 _L7P_0 9 _L7N_0 E9 _L6P_0 F9 _L6N_0 G9 _LP_0 8 _LN_0 8 8 _LP_0 8 _LN_0 E8 _LP_0 F8 _LN_0 G8 _L0P_0 7 _L0N_0 7 _L09P_0 7 _L09N_0 E7 /VREF_0 F7 6 _L08P_0 6 _L08N_0 6 _L07P_0 6 _L07N_0 E6 _L06P_0 _L06N_0 _L0P_0/VREF_0 _L0N_0 _L0P_0/VRN_0 _L0N_0/VRP_0 E /VREF_0 NK 0 U XS00-FG676 _LN_/GLK _LP_/GLK _LN_/VREF LP_ E F _L0N_ G _L0P_ H _L9N L9P_ /VREF L8N_ E _L8P_ F _L7N_ G _L7P_ H _L6N_ 6 _L6P_ 6 6 _LN_ E6 _LP_ F6 _LN_ G6 _LP_ H6 _LN_ 7 _LP_ 7 /VREF_ 7 _LN_ 7 _LP_ E7 _L9N_ F7 _L9P_ G7 _L8N_ 8 _L8P_ 8 /VREF_ 8 E8 _L6N_ F8 _L6P_ G8 _LN_ 9 _LP_ 9 _LN_ 9 _LP_ 9 _LN_ E9 _LP_ F9 G9 _L0N_/VREF_ 0 _L0P_ 0 _L09N_ 0 _L09P_ E0 F0 _L08N L08P L07N L07P L06N_/VREF L06P L0N_ E _L0P_ F _L0N L0P L0N_/VRP L0P_/VRN_ E NK U XS00-FG676 _L0N_/VREF_ P6 _L0P_ P _L9N_ P _L9P_ P _L8N_ P _L8P_ P _LN_ P0 _LP_ P9 _LN_ R6 _LP_/VREF_ R _LN_ R _LP_ T _LN_ R _LP_ R _LN_ R0 _LP_ R9 _L9N_ T6 _L9P_ T _L8N_ T _L8P_ T _L7N_ T0 _L7P_ T9 _L6N_ U6 _L6P_ U _LN_ U _LP_ U _LN_ U _LP_/VREF_ U _LN_ V _LP_ V _LN_ V _LP_ V _L0N_ U0 _L0P_ V0 _L9N_ W6 _L9P_ W _L7N_ W _L7P_/VREF_ W _L6N_ V _L6P_ W _LN_ Y6 _LP_ Y _L0N_ W _L0P_ W0 _L09N_ 6 _L09P_/VREF L08N_ Y _L08P_ Y _L07N L07P L06N_ 6 _L06P L0N_ Y _L0P_ Y0 _L0N_ 6 _L0P L0N_/VREF L0P L0N_/VRP L0P_/VRN_ NK U XS00-FG676 _L0N_/VRP L0P_/VRN_ /VREF L0N_ E _L0P_ F _L0N_ E _L0P_ F _L06N_/VREF L06P_ E F _L07N L07P L08N L08P_ E F 0 _L09N_ 0 _L09P_ 0 _L0N_ E0 _L0P_ F0 _LN_ Y9 _LP_ 9 _LN_ 9 _LP_ 9 9 _LN_ E9 _LP_ F9 _L6N_ Y8 _L6P_ 8 _L7N_ 8 _L7P_ 8 _L8N_ 8 _L8P_ E8 /VREF_ Y7 _L9P_ 7 _L9N_ 7 _LP_ 7 _LN_/VREF_ 7 _LN_ E7 _LP_ F7 W6 _LN_ Y6 _LP_ 6 _LN_ 6 _LP_ 6 _L6N_ E6 _L6P_/VREF_ F6 W _L7N_/IN/0 Y _L7P_/ W _L8N L8P L9N_ E _L9P_ F _L0N_/ Y _L0P_/ /VREF LN_/INIT LP_/OUT/USY _LN_/GLK E _LP_/GLK0 F NK UE XS00-FG676 F _L0P_/S L0N_/RWR L0P L0N_ E /VREF_ F _L0P_ 6 _L0N_ 6 _L06P L06N_ E _L07P_ 6 _L07N_ 6 _L08P_ E6 _L08N_ F6 7 _L09P_ 7 _L09N_ 7 _L0P_/VRN_ E7 _L0N_/VRP_ F7 Y8 _LP_ 8 _LN_/VREF_ 8 _LP_ 8 _LN_ 8 _LP_ E8 _LN_ F8 _L6P_ Y9 _L6N_ _L8P_ 9 _L8N_ E9 _L9P_/VREF_ Y0 _L9N_ 0 _LP_ 0 _LN_ 0 0 _LP_ E0 _LN_ F0 _LP_ W _LN_ Y _LP LN L6P_ E _L6N_ F _L7P_ W _L7N_/VREF_ Y _L8P_/7 _L8N_/6 _L9P_/VREF_ E _L9N_ F _L0P_ W _L0N_ Y _LP_/ _LN_/ _LP_/GLK _LN_/GLK E /VREF_ F NK UF XS00-FG676 _L0N_6/VRP_6 _L0P_6/VRN_6 _L0N_6 _L0P_6 _L0N_6/VREF_6 _L0P_6 _L0N_6 _L0P_6 N _L06N_6 Y7 _L06P_6 Y6 _L07N_6 _L07P_6 _L08N_6 Y _L08P_6 Y _L09N_6/VREF_6 _L09P_6 _L0N_6 Y _L0P_6 Y _LN_6 W7 _LP_6 W6 _L6P_6 W _L6N_6 V6 _L7N_6 W _L7P_6/VREF_6 W _L9N_6 W _L9P_6 W _L0N_6 V7 _L0P_6 U7 _LN_6 V _LP_6 V _LN_6 V _LP_6 V _LN_6 U6 _LP_6 U _LN_6/VREF_6 U _LP_6 U _L6N_6 U _L6P_6 U _L7N_6 T8 _L7P_6 T7 _L8N_6 T6 _L8P_6 T _L9N_6 T _L9P_6 T _LN_6 R8 _LP_6 R7 _LN_6 R6 _LP_6 R _LN_6 T _LP_6 R _LN_6/VREF_6 R _LP_6 R _LN_6 P8 _LP_6 P7 _L8N_6 P6 _L8P_6 P _L9N_6 P _L9P_6 P _L0N_6 P _L0P_6/VREF_6 P NK 6 UG XS00-FG676 _L0P_7/VRN_7 F6 _L0N_7/VRP_7 F _L0P_7 E _L0N_7 E _L0P_7 _L0N_7/VREF_7 _L0P_7 G7 _L0N_7 G6 _L06P_7 E _L06N_7 E _L07P_7 F _L07N_7 F _L08P_7 G _L08N_7 G _L09P_7 F _L09N_7 F _L0P_7/VREF_7 H7 _L0N_7 H6 _LP_7 G _LN_7 G _L6P_7/VREF_7 H _L6N_7 J6 _L7P_7 H _L7N_7 H _L9P_7 H _L9N_7/VREF_7 H _L0P_7 J7 _L0N_7 K7 _LP_7 J _LN_7 J _LP_7 J _LN_7 J _LP_7 K6 _LN_7 K _LP_7 K _LN_7 K _L6P_7 K _L6N_7 K _L7P_7/VREF_7 L8 _L7N_7 L7 _L8P_7 L6 _L8N_7 L _L9P_7 L _L9N_7 L _LP_7 M8 _LN_7 M7 _LN_7 M6 _LP_7 M _LP_7 L _LN_7 M _LP_7 M _LN_7 M _LP_7 N8 _LN_7 N7 _L8P_7 N6 _L8N_7 N _L9P_7 N _L9N_7 N _L0P_7 N _L0N_7/VREF_7 N NK 7 UH XS00-FG676 SRM_NLE SRM_NLE SRM_7 EXTEN_ EXTEN_ EXTEN_ US_9 EXTEN_6 U_TFT_L U_TFT_L EXTEN_7 U_TFT_L EXTEN_8 U_TFT_STH EXTEN_9 EXTEN_ U_TFT_STV EXTEN_0 EXTEN_ U_TFT_GREEN EXTEN_ EXTEN_6 U_TFT_GREEN EXTEN_ EXTEN_ EXTEN_7 U_TFT_GREEN EXTEN_8 EXTEN_ U_TFT_GREEN EXTEN_9 EXTEN_6 U_TFT_GREEN EXTEN_ EXTEN_9 EXTEN_7 U_TFT_GREEN0 EXTEN_0 EXTEN_8 U_TFT_LUE EXTEN_9 U_TFT_LUE EXTEN_0 U_TFT_LUE SRM_0 EXTEN_ SRM_9 SRM_8 SRM_8 SRM_ SRM_ SRM_ SRM_ EXTEN_ EXTEN_ UZZER SW0 SW SW SW SW SRM_NS SRM_ SRM_ SRM_ SRM_ SRM_ SRM_6 IP7 IP SRM_NOE SRM_7 SRM_0 SRM_ SRM_ SRM_ U_RESET_SW IP6 SRM_ SRM_NHE SRM_6 SRM_ SRM_ SRM_ SRM_ SRM_ EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_6 EXTEN_7 EXTEN_8 SRM_0 SRM_NLE EXTEN_9 U_TFT_RE0 U_TFT_RE U_TFT_RE U_TFT_RE U_TFT_RE U_TFT_LUE0 SRM_NWE SRM_ SRM_6 SRM_7 SRM_8 SRM_9 SRM_0 SRM_ SRM_ SRM_ SRM_NS SRM_NOE SRM_6 SRM_ SRM_ SRM_ SRM_9 SRM_8 SRM_ SRM_0 SRM_ SRM_ SRM_6 SRM_ SRM_ SRM_7 SRM_0 SRM_ SRM_8 SRM_ SRM_NWE SRM_7 SRM_9 SRM_8 SRM_ SRM_6 SRM_0 SRM_ SRM_ SRM_ SRM_ SRM_ SRM L0N_/VRP L0P_/VRN_ 6 _L0N_ E _L0P_ E _L0P_ 6 _L0N_/VREF L0N_ E _L0P_ E6 N F _L06N_ G0 _L06P_ G _L07N_ F _L07P_ F _L08N_ G _L08P_ G _L09N_/VREF_ F _L09P_ F6 _L0N_ G _L0P_ G6 _LN_ H0 _LP_ H _L6N_ H _L6P_ J _L7P_/VREF_ H _L7N_ H _L9N_ H _L9P_ H6 _L0N_ J0 _L0P_ K0 _LN_ J _LP_ J _LN_ J _LP_ J _LP_ K _LN_/VREF_ K _LN_ K _LP_ K _L6N_ K _L6P_ K6 _L7N_ L9 _L7P_ L0 _L8N_ L _L8P_ L _L9N_ L _L9P_ L6 _LN_ M9 _LP_ M0 _LN_ M _LP_ M _LP_ M _LN_ L _LP_ M6 _LN_/VREF_ M _LN_ N9 _LP_ N0 _L8N_ N _L8P_ N _L9N_ N _L9P_ N _L0N_ N _L0P_/VREF_ N6 NK U XS00-FG676 N_RX EXTEN_0 EXTEN_0 SRM_0 SRM_7 SRM_ 7 6 EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_7 EXTEN_6 EXTEN_9 EXTEN_8 EXTEN_0 EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_6 EXTEN_ EXTEN_8 EXTEN_7 EXTEN_9 EXTEN_0 EXTEN_ GN EXTEN_0 EXTEN_ EXTEN_ EXTEN_ EXTEN_ US_7 US_FLSH_NS US_ US_ US_ US_NOE US_ US_NE US_NE0 US_SRM_NS US_NE US_NE US_ US_0 US_6 US_8 US_ US_7 US_9 US_8 US_8 US_9 US_7 US_0 US_6 US_ US_0 US_ US_6 US_SRM_NS US_SRM_NS US_SRM_NRS US_ US_ US_ US_0 US_9 US_ US_7 US_ US_ US_ US_ US_0 US_ US_8 US_ US_ US_0 US_ US_7 US_ US_NWE US_FLSH_NUSY US_ US_ US_9 US_8 US_ US_FLSH_NRESET US_ US_6 US_ US_ US_SRM_KE US_ US_ US_SRM_LK US_SRM_FEEK NT8 NT NT NT NT NT6 ONE_WIRE_P ONE_WIRE_P ONE_WIRE U_W_S06_EPROM W_S06_EPROM I P P ONE_WIRE [8..0] [..0] NS NWE NOE NHE NLE SRM [8..0] [..0] NS NWE NOE NHE NLE SRM US_[..] US_[..0] US_NOE US_NWE US_NE[..0] US_SRM_NS US_FLSH_NS US_SRM_NS US_SRM_KE US_SRM_LK US_SRM_NS US_SRM_NRS US_FLSH_NRESET US_FLSH_NUSY US_[..] US_[..0] US_NE[..0] US_NWE US_NOE US_FLSH_NS US_FLSH_NRESET US_FLSH_NUSY US_SRM_NS US_SRM_KE US_SRM_LK US_SRM_NS US_SRM_NRS US_SRM_NS HOST MEMORY RESOURES MEM_OMMON UGHTER OR MEMORY RESOURES REF_LK FPG_LK FPG_LK MOE SEL LK IN OUT IN ONE INSTLLE I[..0] LK PROGRM M[..0] INIT PROG_PWR_ON PROG_LK TMS TO TI TK TMS TO TI TK HR SOFT UGHTER OR I/O JTG PROGRM SPI US LOKS JTG PROGRM SPI LOKS NEXUS_TK NEXUS_TI NEXUS_TO NEXUS_TMS U_RESET_SW HOST PERIPHERLS Host Reset Status LEs L[7..0] USER_LE SW [..0] RE[..0] GREEN[..0] LUE[..0] M POL L[..] STV STH ISP_ON LIGHT IRQ MUX U_TFT_MUX U_TFT_RE[..0] U_TFT_GREEN[..0] U_TFT_LUE[..0] U_TFT_M U_TFT_POL U_TFT_L[..] U_TFT_STV U_TFT_STH U_TFT_ISP_ON U_TFT_LIGHT U_TFT_IRQ TFT TFT L ISPLY INTERFE T LOK KLOK KT MOUSELOK MOUSET RS_TS RS_RTS RS_RX RS_TX RS KEYOR MOUSE RX TX RTS TS T LOK LE[7..0] U_RESET_SW IP USER [..0] [7..0] TX RX N SL S I EXT_ EXT_ EXT_ EXTEN_[9..0] EXTEN_[9..0] EXTEN_[9..0] [9..0] [9..0] [9..0] ONE-WIRE ONNETNS U_ypass_V ypass_fpg_v.schoc U_ypass_V ypass_fpg_v.schoc U_ypass_V ypass_fpg_v.schoc

9 9 0 - aughter oard Spartan 07 //008 :0:7 PM FPG_Non.Schoc ate: Revision: Sheet of Time: FPG Power and Programming ssy: ltium Limited L, Rodborough Road NSW 086 ustralia TMS ONE M LK M0 M TK HSWP_EN TI PROG_ TO TMS ONE M LK 6 M0 E M F TK HSWP_EN TI PROG_ TO UI XS00-FG676 GN GN 6 GN GN GN GN GN GN GN GN GN K GN K GN K GN K6 GN L0 GN L GN L GN L GN L GN L GN L6 GN L7 GN M GN M0 GN M GN M GN M GN M GN M GN M6 GN M7 GN M GN N GN N GN N GN N GN N GN N6 GN P GN P GN P GN P GN P GN P6 GN R GN R0 GN R GN R GN R GN R GN R GN R6 GN R7 GN R GN T0 GN T GN T GN T GN T GN T GN T6 GN T7 GN U GN U GN U GN U6 GN GN GN GN GN GN GN E GN E GN F GN F6 UJ XS00-FG676 VO_6 Y VO_6 V8 VO_6 U8 VO_6 T9 VO_6 T VO_6 R9 VO_6 P0 VO_6 P9 VO_ 0 VO_ W8 VO_ W7 VO_ V6 VO_ 6 VO_ V VO_ U VO_ V VO_ G VO_ J9 VO_ K9 VO_ L8 VO_ L VO_ M8 VO_ N7 VO_ N8 VO_0 J VO_0 K VO_0 J VO_0 VO_0 J VO_0 H0 VO_0 H9 VO_0 7 VO_7 G VO_7 J8 VO_7 K8 VO_7 L9 VO_7 L VO_7 M9 VO_7 N0 VO_7 N9 VO_ 7 VO_ W9 VO_ W0 VO_ V VO_ VO_ V VO_ U VO_ V VO_ P8 VO_ P7 VO_ R8 VO_ T VO_ T8 VO_ U9 VO_ V9 VO_ Y VO_ J VO_ K VO_ J VO_ 6 VO_ J6 VO_ H7 VO_ H8 VO_ 0 UK XS00-FG676 VUX VUX 9 VUX 8 VUX VUX VUX 6 VUX J VUX J6 VUX V VUX V6 VUX E VUX E6 VUX F VUX F9 VUX F8 VUX F VINT H8 VINT H9 VINT J9 VINT J0 VINT J7 VINT J8 VINT K9 VINT K0 VINT K7 VINT K8 VINT U9 VINT U0 VINT U7 VINT U8 VINT V9 VINT V0 VINT V7 VINT V8 VINT W8 VINT W9 UL XS00-FG676 V V V V GN GN

10 V 0uF 0V GN V 0uF 0V 0uF 0V 0uF 0V V GN 0.uF 6V 6 0.uF 6V 7 0.uF 6V 8 0.uF 6V 9 0.uF 6V 0 0.uF 6V 0.uF 6V 0.uF 6V V GN 0nF 6V 0nF 6V 0nF 6V 6 0nF 6V 7 0nF 6V 8 0nF 6V 9 0nF 6V 0 0nF 6V GN ate: FPG ypass V 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM ypass_fpg_v.schoc Sheet 0 of ltium Limited L, Rodborough Road NSW 086 ustralia

11 V 0uF 0V 0uF 0V 0uF 0V V GN 0.uF 6V 0.uF 6V 6 0.uF 6V 7 0.uF 6V 8 0.uF 6V 9 0nF 6V 0 0nF 6V 0nF 6V V GN 0nF 6V 0nF 6V 0nF 6V 0nF 6V 6 0nF 6V 7 0nF 6V 8 0nF 6V 9 0nF 6V GN ate: FPG ypass V 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM ypass_fpg_v.schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

12 FPG ypass V ate: 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM ypass_fpg_v.schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V 0nF 6V uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V 0.uF 6V uF 0V 0uF 0V 0uF 0V 0uF 0V 0uF 0V 0uF 0V 0uF 0V 0uF 0V V GN V GN 0.uF 6V 0.uF 6V 0.uF 6V V GN V GN The FPG bypass capacitors are physically grouped as 0nF and 00nF pairs on all major accessible power pins on the FPG.

13 V U S06 Vcc T N P GN P 6 I P P ONE_WIRE GN V V GN 0.uF 6V GN 0nF 6V ate: -Wire us I 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM W_S06_EPROM.Schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

14 STTUS LE POWER LE _SL V V V GN 0.uF 6V R_SL 70R % R_SL 70R % LE_PWR STTUS_LE U_SL SN7LVG0V N V GN Y LE_PGM LE_SL GREEN LE_SL RE GN GN ate: aughter oard LEs 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM _LES.Schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

15 HOSTMEMORY US_[..] US_[..0] US_SRM_NS US_SRM_NS US_SRM_NRS US_SRM_KE US_SRM_LK US_[..] US_[..0] US_[6..] US_[..0] SRM [6..] [..0] SRM_NS SRM_NS SRM_NRS SRM_KE SRM_LK NE[..0] NWE M_SRM OM_SRM SRM_MT8L6M6TG_6Mx SRM MEM US_FLSH_NS US_FLSH_NRESET US_FLSH_NUSY US_[..] US_[..0] FLSH [..] [..0] FLSH_NS FLSH_NRESET FLSH_NUSY NOE NWE M_FLSH OM_FLSH FLSH_S9GL6NFFIV0_6Mx6 FLSH SRM US_SRM_NS US_NE[..0] US_NOE US_NWE US_[0..] US_[..0] [0..] [..0] NS NE[..0] NOE NWE M_SRM OM_SRM SRM_6Kx_TSOP_ SRM ommon-us Memory lock 6K x -bit SRM ( Myte) 6M x -it SRM (6 Myte) 6M x 6-it Flash ( Myte) ate: ommon-us Memory lock 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM N_ommonMemory.Schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

16 FLSH FLSH [..0] [..] FLSH_NS NOE NWE FLSH_NRESET US_[..0] US_[..] US_ US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_ US_ V E E7 8 8 F G F7 U S9GL6NFFIV E# OE# WE# WP#/ RESET# YTE# Q0 Q Q Q Q Q Q6 Q7 Q8 Q9 Q0 Q Q Q Q Q/- V V V RY/Y# E H E H H E H6 E6 F G F G F G6 F6 G7 G 8 F E8 H7 H US_0 US_ US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_ US_ US_ V GN N N N N N N N N N N N 8 F8 G8 H8 E G H FLSH_NUSY V V V V V V GN 0nF 6V GN 0nF 6V GN 0nF 6V GN 6 0.uF 6V GN 0.uF 6V GN 0.uF 6V ate: //008 Time: :0:7 PM Sheet 6 of FLSH_S9GL6NFFIV0_6Mx6.Schoc 6M x 6 Flash Memory (G) 0 - aughter oard Spartan ssy: Revision: 07 ltium Limited L, Rodborough Road NSW 086 ustralia

17 7 0 - aughter oard Spartan 07 //008 :0:7 PM SRM_MT8L6M6TG_6Mx.Schoc ate: Revision: Sheet of Time: 6M x SRM TSOP x ssy: ltium Limited L, Rodborough Road NSW 086 ustralia [6..] [..0] NE[..0] NWE SRM_NS SRM_NRS SRM_KE SRM_LK SRM_NS SRM US_SRM_LK US_SRM_KE US_SRM_LK US_SRM_KE GN GN US_[6..] US_[..0] US_NE[..0] US_SRM_NS US_SRM_NRS V Q0 VQ Q Q Q 6 Q 7 Q 8 VQ 9 Q 0 Q6 Q Q7 V QML WE 6 S 7 RS 8 S V KE 7 LK 8 QMH 9 N 0 Q8 VQ Q9 Q0 Q 6 Q 7 Q 8 VQ 9 Q 0 Q Q Q U SRM-6Mx6 V Q0 VQ Q Q Q 6 Q 7 Q 8 VQ 9 Q 0 Q6 Q Q7 V QML WE 6 S 7 RS 8 S V KE 7 LK 8 QMH 9 N 0 Q8 VQ Q9 Q0 Q 6 Q 7 Q 8 VQ 9 Q 0 Q Q Q U SRM-6Mx6 US_SRM_LK US_SRM_KE US_NWE US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_0 US_ US_ US_ US_ US_6 US_ US_7 US_8 US_9 US_0 US_ US_ US_ US_ US_ US_ US_6 US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_SRM_NS US_NWE US_SRM_NS US_SRM_NRS US_NE0 US_NE US_NE US_NE US_SRM_NS US_NWE US_SRM_NS US_SRM_NRS US_ US_ US_ US_ US_SRM_NS V 0.uF 6V 7 0nF 6V 6 0nF 6V 0nF 6V 8 0nF 6V 0.uF 6V 0.uF 6V 0.uF 6V US_6 US_8 US_7 US_0 US_9 US_ US_ US_ US_ US_ US_6 US_8 US_7 US_ US_0 US_9 US_ US_6 GN V GN V GN V GN V GN V GN V GN V GN V V SRM

18 8 is connected so that Kx6 device can be fitted U SRM-6Kx6 U SRM-6Kx6 SRM SRM [0..] [..0] NS NWE NOE NE[..0] SRM_[0..] SRM_[..0] SRM_NS SRM_NWE SRM_NOE SRM_NE[..0] V GN SRM_ SRM_ SRM_ SRM_ SRM_6 SRM_NS 6 SRM_0 7 SRM_ 8 SRM_ 9 SRM_ 0 SRM_ SRM_ SRM_6 SRM_7 6 SRM_NWE 7 SRM_7 8 SRM_8 9 SRM_9 0 SRM_0 SRM_ 0 S 0 V 6 7 WE OE HE LE V N SRM_9 SRM_8 SRM_7 SRM_NOE SRM_NE SRM_NE0 SRM_ SRM_ SRM_ SRM_ SRM_ SRM_0 SRM_9 SRM_8 SRM_0 SRM_6 SRM_ SRM_ SRM_ SRM_ GN V V GN SRM_ SRM_ SRM_ SRM_ SRM_6 SRM_NS 6 SRM_6 7 SRM_7 8 SRM_8 9 SRM_9 0 SRM_0 SRM_ SRM_ SRM_ 6 SRM_NWE 7 SRM_7 8 SRM_8 9 SRM_9 0 SRM_0 SRM_ 0 S 0 V 6 7 WE OE HE LE V N SRM_9 SRM_8 SRM_7 SRM_NOE SRM_NE SRM_NE SRM_ SRM_0 SRM_9 SRM_8 SRM_7 SRM_6 SRM_ SRM_ SRM_0 SRM_6 SRM_ SRM_ SRM_ SRM_ GN V V V V V V V V V 0.uF 6V 0.uF 6V 0nF 6V 6 0nF 6V 0.uF 6V 0.uF 6V 7 0nF 6V 8 0nF 6V GN GN GN GN GN GN GN GN 6K x SRM - TSOP x ate: //008 Time: :0:7 PM Sheet 8 of SRM_6Kx_TSOP_.Schoc 0 - aughter oard Spartan ssy: Revision: 07 ltium Limited L, Rodborough Road NSW 086 ustralia

19 6 7 8 MEM HOSTMEMORY US_[..] US_[..0] US_NE[..0] US_NOE US_NWE US_SRM_NS US_SRM_NS US_SRM_NRS US_SRM_KE US_SRM_LK US_FLSH_NS US_FLSH_NRESET US_SRM_NS US_[..] US_[..0] US_NE[..0] US_NOE US_NWE US_SRM_NS US_SRM_NS US_SRM_NRS US_SRM_KE US_SRM_LK US_FLSH_NS US_FLSH_NRESET US_SRM_NS THESE SIGNLS TERMINTE T THE SRM EVIE V V V US_FLSH_NUSY RN RESNET x 00R RN RESNET x 00R RN7 RESNET x 00R US_NE US_NE0 US_NWE US_SRM_NS US_SRM_NRS US_SRM_NS US_NE US_NE US_SRM_KE US_SRM_LK RN RESNET x 00R RN6 RESNET x 00R RN8 RESNET x 00R GN GN GN ll devices using controlled impedance outputs from the source (ie. FPG) should use 0 ohm ( parallel 00 ohm resistors) termination. The Flash should be located closest to the source (FPG). The SRM should be located next furthest from the source (FPG). The SRM should be located next furthest from the source (FPG). Terminations are to be located at the furthest distance from the source (FPG). Note that pins,6,7 and 8 of the following resnet "groups" are pin-swappable within that "group": - all "power" resnets that terminate the FLSH-only signals (ie. RN and RN). - all "ground" resnets that terminate the FLSH-only signals (ie. RN and RN). - all "power" resnets that terminate the FLSH-SRM-only signals (ie. RN and RN7). - all "ground" resnets that terminate the FLSH-SRM-only signals (ie. RN6 and RN8). - all "power" resnets that terminate the FLSH-SRM-SRM signals (ie. RN9, RN, RN, RN, RN7, RN9, RN, RN, RN, RN7, RN9, RN, RN, RN). - all "ground" resnets that terminate the FLSH-SRM-SRM signals (ie. RN0, RN, RN, RN6, RN8, RN0, RN, RN, RN6, RN8, RN0, RN, RN, RN6). To remove any confusion by the P assembler, the following devices have been deleted entirely from the design: RN to RN6, and RN7 to RN. Note that high current (up to. mps) is drawn from the V rail when all 9 pairs of resnets are loaded. The addition of up to. watts of heat was significantly warming the P. Testing has confirmed that the loading of only pairs of resnets (RN/, RN/6 and RN7/8) provides good operation at speeds up to 96MHz. This consumes up to 0.0 amps, ie. up to 0.6 watts of heat. The loading of the pairs of resnets terminates only the output control signals from the FPG to the SRM. The bidirectional data bus and address bus is not terminated. Signals that do not connect to the SRM (ie. signals to the slower flash and SRM devices only) are also not terminated. 6 ate: Memory ommonus Terminations 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM Sheet 9 of N_ommonMemory_Termination.Schoc 7 ltium Limited L, Rodborough Road NSW 086 ustralia 8

20 U_SM SRM-6Kx6 SRM SRM-6Kx6 [8..0] [..0] NS NWE NOE NHE NLE SRM_[8..0] SRM_[..0] SRM_NS SRM_NWE SRM_NOE SRM_NHE SRM_NLE V GN SRM_0 SRM_ SRM_ SRM_ SRM_ SRM_NS 6 SRM_0 7 SRM_ 8 SRM_ 9 SRM_ 0 SRM_ SRM_ SRM_6 SRM_7 6 SRM_NWE 7 SRM_ 8 SRM_6 9 SRM_7 0 SRM_8 SRM_9 0 S 0 V 6 7 WE OE HE LE V N SRM_7 SRM_6 SRM_ SRM_NOE SRM_NHE SRM_NLE SRM_ SRM_ SRM_ SRM_ SRM_ SRM_0 SRM_9 SRM_8 SRM_8 SRM_ SRM_ SRM_ SRM_ SRM_0 GN V 8 is connected so that Kx6 device can be fitted V V V V _SM 0.uF 6V _SM 0nF 6V _SM 0.uF 6V _SM 0nF 6V GN GN GN GN ate: 6K x 6-it SRM 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM SRM_6Kx6_TSOP.Schoc Sheet 0 of ltium Limited L, Rodborough Road NSW 086 ustralia

21 6 7 8 V FPG_TK TK ONE_WIRE P FPG_TI ONE_WIRE P TI HR FPG_TO ONE_WIRE_P NT TO ONE_WIRE_P FPG_TMS TMS ONE_WIRE_I ONE_WIRE_I JTG NEXUS_TK TK UZZER NEXUS_TI UZZER TI SOFT NEXUS_TO U_RESET_SW TO U_RESET_SW NEXUS_TMS TMS V GN SLEEP_N SLEEP_N GN LE8 V0 GN WS VX (NOW PHSE OUT) HR_ MOLEX EXTEN_0 EXTEN_0 USER_LE L[7..0] USER_LE[7..0] EXTEN_ EXTEN_ EXTEN_ 6 EXTEN_ EXTEN_ 7 8 EXTEN_ P EXTEN_ 9 0 EXTEN_ EXT_ [9..0] EXTEN_[9..0] EXTEN_ EXTEN_ GN EXTEN_6 EXTEN_6 EXTEN_7 6 EXTEN_7 P EXTEN_8 7 8 EXTEN_8 EXTEN_[9..0] EXT_ [9..0] EXTEN_9 9 0 EXTEN_9 EXTEN_0 EXTEN_0 P EXTEN_ EXTEN_ EXT_ [9..0] EXTEN_[9..0] EXTEN_ 6 EXTEN_ EXTEN_ 7 8 EXTEN_ EXTEN_ 9 0 EXTEN_ EXTEN_ EXTEN_ Note that the signal ONE_WIRE_I was SPI_LK LK EXTEN_6 EXTEN_6 previously called FPG_LK. SPI_IN IN EXTEN_7 6 EXTEN_7 SPI_OUT SPI OUT EXTEN_8 7 8 EXTEN_8 SPI_MOE This signal was included in N design, but MOE EXTEN_9 9 0 EXTEN_9 SPI_SEL never used. Hence it has now been reallocated. SEL EXTEN_0 EXTEN_0 EXTEN_ EXTEN_ TFT EXTEN_ 6 EXTEN_ U_TFT_RE[..0] RE[..0] EXTEN_ 7 8 EXTEN_ U_TFT_GREEN[..0] GREEN[..0] EXTEN_ 9 0 EXTEN_ U_TFT_LUE[..0] LUE[..0] EXTEN_ EXTEN_ U_TFT_M M EXTEN_6 EXTEN_6 U_TFT_POL POL EXTEN_7 6 EXTEN_7 U_TFT_L[..] L[..] EXTEN_8 7 8 EXTEN_8 U_TFT_STV STV EXTEN_ EXTEN_9 U_TFT_STH STH EXTEN_0 6 6 EXTEN_0 U_TFT_ISP_ON ISP_ON EXTEN_ 6 6 EXTEN_ U_TFT_LIGHT LIGHT EXTEN_ 6 66 EXTEN_ U_TFT_IRQ IRQ EXTEN_ EXTEN_ U_TFT_MUX MUX EXTEN_ EXTEN_ EXTEN_ 7 7 EXTEN_ EXTEN_6 7 7 EXTEN_6 INSTLLE FPG_LK EXTEN_ EXTEN_7 LK FPG_IN EXTEN_ EXTEN_8 IN FPG_ONE EXTEN_ EXTEN_9 ONE FPG_I[..0] EXTEN_0 8 8 EXTEN_0 I[..0] PROGRM FPG_INIT EXTEN_ 8 8 EXTEN_ INIT FPG_M[..0] EXTEN_ 8 86 EXTEN_ M[..0] FPG_PROG_LK EXTEN_ EXTEN_ PROG_LK FPG_PROG_PWR_ON EXTEN_ EXTEN_ V GN PROG_PWR_ON FPG_PROGRM EXTEN_ 9 9 EXTEN_ PROGRM EXTEN_6 9 9 EXTEN_6 GN LOKS FPG_LK EXTEN_ EXTEN_7 FPG_LK REF_LK EXTEN_ EXTEN_8 REF_LK FPG_LK EXTEN_ EXTEN_9 FPG_LK N MH MH N_TX GN GN TX N_RX RX MOLEX KEYOR Green connections are I/O pins connected to N compatible P resources on the mother board. These can be changed. 6 N to aughter oard onnectors 0 - aughter oard Spartan ssy: Revision: 07 ate: //008 Time: :0:7 PM _Motheroardonnectors.Schoc Sheet of 7 ltium Limited L, Rodborough Road NSW 086 ustralia 8 SL S ONE_WIRE P U_TFT_IRQ U_TFT_POL U_TFT_MUX U_TFT_M U_TFT_ISP_ON U_TFT_LIGHT MH MH MH MH FPG_LK REF_LK USER_LE0 USER_LE USER_LE USER_LE USER_LE USER_LE USER_LE6 USER_LE7 IP0 IP IP IP IP IP IP6 IP7 U_RESET_SW UZZER SW0 SW SW SW SW U_TFT_RE0 U_TFT_RE U_TFT_RE U_TFT_RE U_TFT_RE U_TFT_LUE0 U_TFT_LUE U_TFT_LUE U_TFT_LUE U_TFT_LUE U_TFT_GREEN0 U_TFT_GREEN U_TFT_GREEN U_TFT_GREEN U_TFT_GREEN U_TFT_GREEN U_TFT_STV U_TFT_STH U_TFT_L U_TFT_L U_TFT_L MH MH EXTEN_9 EXTEN_7 EXTEN_8 EXTEN_ 6 EXTEN_6 EXTEN_ 7 8 EXTEN_ EXTEN_ 9 0 EXTEN_ EXTEN_9 EXTEN_0 EXTEN_8 N_RX EXTEN_7 6 N_TX EXTEN_6 7 8 RS_RTS EXTEN_ 9 0 RS_TX EXTEN_ RS_TS EXTEN_ RS_RX EXTEN_ 6 EXTEN_ 7 8 EXTEN_0 9 0 EXTEN_9 EXTEN_8 EXTEN_7 6 EXTEN_6 7 8 EXTEN_ 9 0 EXTEN_ EXTEN_ EXTEN_ EXTEN_ 7 8 EXTEN_0 9 0 EXTEN_9 EXTEN_8 EXTEN_7 6 EXTEN_6 7 8 EXTEN_ 9 60 EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_0 EXTEN_9 EXTEN_8 EXTEN_7 EXTEN_6 EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_0 ONE_WIRE_P MH MH KLOK KT MOUSELOK MOUSET FPG_INSTLLE FPG_I FPG_I FPG_I FPG_I0 SPI_IN SPI_LK SPI_SEL SPI_OUT SPI_MOE FPG_TO FPG_M FPG_M FPG_M0 FPG_PROGRM FPG_IN FPG_LK FPG_INIT FPG_TMS FPG_TK FPG_ONE NEXUS_TO FPG_TI NEXUS_TMS NEXUS_TK NEXUS_TI FPG_PROG_PWR_ON FPG_PROG_LK FPG_LK ONE_WIRE_I SW IP USER I RS MOUSE SW SW8 6 [..0] [7..0] [..0] SL S TX RTS RX TS T LOK T LOK SW[..0] IP[7..0] [..0] SL S RS_TX RS_RTS RS_RX RS_TS KT KLOK MOUSET MOUSELOK GN HR_L MH MH GN HR_T MOLEX SLEEP_N Red onnections are locked for N compatibility. They are hardwired on the N and therefore can NOT be changed. lue connections are connected to the New N compatible resources on the motherboard. These can be changed. GN V0 GN WS VX (NOW PHSE OUT)

22 U_MOUNTS _MOUNTS P 0 lank P Printed ircuit oard (are) ate: 0 Hardware Kit 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM 0_Hardware_Kit.Schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia

23 MH MOUNTING HOLE MM ltium Logo Top MH MOUNTING HOLE MM MH MOUNTING HOLE MM ltium Logo ot ate: Mounts, Logo & Label 0 - aughter oard Spartan ssy: Revision: 07 //008 Time: :0:7 PM _MOUNTS.Schoc Sheet of ltium Limited L, Rodborough Road NSW 086 ustralia