PCB NO. DM205A SOM-128-EX VER:0.6
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- Baldwin Evans
- 5 years ago
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1 V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V Q V Q V M W QSN S0 V QSP S S RS WE KE0 SRMLK0P SRMLK0N VoetexEX ZQ0 TEST_OT TEST_OT0 RST VREF L N U U N T L R M T T P P P N L N N V R T V P U W W T R W L R M0 M M M M M M M M M M0 M M M M M M0 M M MS0 MS MRS MWE MKE0 MK0P MK0N MZQ R 0 % MOT0 MR_RST VREF_R_HIP V. 0 R % R % IFF-00 IFF-00 M M M0 M M M M M MQS0N MQS0P MQM0 M M M M0 M M M M MQSN MQSP MQM RP 0x RM RM RM0 RM RP 0x RM RM RM RM RP RP R 0 R 0 R 0 0x R 0 R 0 R 0 0x RMQS0N RMQS0P RMQM0 RM RM RM RM0 RM RM RM RM RMQSN RMQSP RMQM Total Trace length under 000mils with space W and line to line variance under 0mils High byte to Low byte misnatch under 00mil M0 M M M M M M M M M M0 M M M M M M0 M M RMS RMRS RMWE RMS0 MKE0 MOT0 MR_RST RMK0P RMK0N N P P N P P R R T R L R N T T M M N M K J L L K K T J K U 0 E F H H R R N N K K 0/P /# 0 S RS WE S KE OT RESET K K VQ VQ VQ VQ VQ VQ VQ VQ VQ V V V V V G V V V V E E F G G T T P M M J J G E QL0 UL QL QL QL QL QL QL ML QSL QSL QU0 QU QU QU QU QU QU QU MU QSU QSU ZQ N N N N VREF VREFQ Q Q Q Q Q Q Q Q Q E F F F H H G H E F G L J J L L M H RM0 RM RM RM RM RM RM RM RMQM0 RMQS0P RMQS0N RM RM RM0 RM RM RM RM RM RMQM RMQSP RMQSN VREF_R RIII MX R 0 % V. R % 0 R % MRS MS MS0 MWE RP 0x RMRS RMS RMS0 RMWE dd IFF-00 MK0N MK0P R 0 R 0 RMK0N R0 00 RMK0P dd 00R 0/0/ SOMEX-KIT P NO. M0 SOM--EX VER:0. MP ELETRONIS IN. VotexEX R-III Memory Size ocument Number Rev M0 0. ate: Wednesday, ugust, 0 Sheet of
2 UF JTG VTT V R 0 T PWRG PIRST- PWRG POWER_GOO PIRST# PIRST- RSTRV IS_RST RSTRV VT 0 Y.KHz/SM.x. R pf 0M R pf XY XY K H H J H H RT RT_XO RT_LK RT_NMR RT_VE RT_ JTG TMS_0 TO_0 TI_0 TK_0 G E E E TMS TO TI TK 0 pf RN 0Kx TK TO TI TMS V V J WWR LOK SPI SPI FLSH pf pf Y MHz/SM.x. X N X N MHz SM TYPE XX XX W V XIN XOUT SPI_S SPI_K SPI_I SPI_O F E H G SPIS SPILK SPII SPIO V. R K HOL# V. SPIS SPII U HOL# SLK V SI/SIO0 N N N N N N N N S# GN 0 SO/SIO WP#/ M SPI ROM SPILK SPIO WP# R K V. E V 0 GN V. E L L _V 0 GN._TEMP J J M K V V_TEMP _TEMP _IN0 _IN _IN _IN _IN _IN _IN _IN F E F G E F G G _0 0 _ SPIO SPIS SPII WP# oot Flash select (High) Hardware default U S# V SO HOL# WP#/ SLK GN SI M SPI ROM_SOI strap pin SPIS V. HOL# SPILK SPIO oot Mode Select (High) Normal boot (default) 0 0 TEST_MOE E 0 (Low) * (default) from FLSH * 0 (Low) Fast boot GN GN GN R 0 VoetexEX MP ELETRONIS IN. GN PWGOO,RT,ST,LOK,SPI, Size ocument Number Rev M0 0. ate: Wednesday, ugust, 0 Sheet of
3 V. L E V. L E V_NPLL 0 V_. U T T T U U W V U V_NPLL _SPLL V_SPLL _NPLL IF_V IF_ IF_V IF_ LOK PLLK00_0_P PLLK00_0_N PLLK00 P PLLK00 N ST_PHY_LK_P ST_PHY_LK_N W V W V W V IFF-00 IF0_P IF0_N IF_P IF_N IF_P IF_N R 0 R0 0 R 0 R 0 R 0 R 0 PE0_LK+ PE0_LK- PIE_LK+ PIE_LK- ST_LK+ ST_LK- PIE-0 PE0_LK- PE0_LK+ PE0_LK- PE0_LK+ 0 0 V L E 0 V. L E 0 0 V L E V_PE 0 V_PERX 0 0 V_ST 0 N T T M N M N L M M V_PE V_PE _PE V_PEPLL _PEPLL V_PERX _PERX V_ST V_ST _ST PI-E Host/Target ST PIE_REFLKP PIE_REFLKN PIE_RXIP PIE_RXIN PIE_TXOP PIE_TXON PIE_MSEL ST_RXIP ST_RXIN N N P P R R PETXP PETXN IFF-00 PIE_MSEL R K K 0 IFF R 0K PIE_LK+ PIE_LK- PE0_RX+ PE0_RX- PE0_TX+ PE0_TX- V. ST_RX+ ST_RX- PIE_MSEL (High) (default) PIe select PIe Host 0 (Low) PIe Target PI Host / Target PE0_RX- PE0_RX+ PE0_TX- PE0_TX+ ST PE0_RX- PE0_RX+ PE0_TX- PE0_TX+ V. L E V_ST K L V_STPLL _STPLL ST_TXOP ST_TXON ST_REFLKP ST_REFLKN L L J J STXP STXN 0 0 ST_TX+ ST_TX- ST_LK+ ST_LK- IFF-00 IFF-00 ST_TX+ ST_TX- ST_RX- ST_RX+ ST_TX+ ST_TX- ST_RX- ST_RX+ K L V_STRX _STRX VoetexEX MP ELETRONIS IN. LOK, PI-e, ST Size ocument Number Rev M0 0. ate: Wednesday, ugust, 0 Sheet of
4 U V L0 E 0 V_US 0 0 V_US _US V_USS US US_P US_M US_EXTK US+ US- US_EXT R K % IFF-0 US- US+ US- US+ V. L E 0 V_US 0 0 _USS V_US US_P US_M US_EXTK US+ US- US_EXT R K % IFF-0 US- US+ US- US+ V_USPLL _USPLL V. L 0 E 0 V_YG T W V_EPHYG V_EPHYPLL LN EPHY_TXP EPHY_TXN EPHY_RXP EPHY_RXN V W V W TX+ TX- RXIN+ RXIN- IFF-0 LNRX+ LNRX- LNTX- RXIN+ IFF-0 RXIN- TX- IFF-0 LNRX+ LNRX- LNTX- U P V _EPHYTX _EPHYG _EPHYPLL EPHY_ISET R ISET R0.0K % TX+ LNTX+ LNTX+ VoetexEX MP ELETRONIS IN. US, LN Size ocument Number Rev M0 0. ate: Wednesday, ugust, 0 Sheet of
5 P0 P P P P GP00 GP0 GP0 GP0 GP0 GP0 GP0 GP0 GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 GP0 GP0 GP0 GP0 GP0 GP0 GP0 GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP E E H H H G G G H G F E F E F E E F E UE GPIO-P0/0-P0/RIH IO-P0/OM GP00/P00/RP00/# GP0/P0/RP0/SOUT GP0/P0/RP0/RTS# GP0/P0/RP0/RI GP0/P0/RP0/SIN GP0/P0/RP0/TR# GP0/P0/RP0/SR# GP0/P0/RP0/TS# GPIO-P/0-P/RIH IO-P/OM GP0/P0/RP0/# GP/P/RP/SOUT GP/P/RP/RTS# GP/P/RP/RI# GP/P/RP/SIN GP/P/RP/TR# GP/P/RP/SR# GP/P/RP/TS# GPIO-P/0-P/RIH IO-P/OM GP0/P0/RP0/# GP/GP/RP/SOUT# GP/P/RP/RTS# GP/P/RP/RI# GP/P/RP/SIN GP/P/RP/TR# GP/P/RP/SR# GP/P/RP/TS# GPIO-P/0-P/RIH IO-P/OM GP0/P0/RP0/# GP/P/RP/SOUT# GP/P/RP/RTS# GP/P/RP/RI# GP/P/RP/SIN GP/P/RP/TR# GP/P/RP/SR# GP/P/RP/TS# GPIO-P/0-P/RIH IO-P/OM GP0/P0/RP0/# GP/P/RP/SOUT GP/P/RP/RTS# GP/P/RP/RI# GP/P/RP/SIN GP/P/RP/TR# GP/P/RP/SR# GP/P/RP/TS# Port 0 ~ Part OM/RIH IO-P/0-P/GPIO-P #/RP0/P0/GP0 SOUT#/RP/P/GP RTS#/RP/P/GP RI#/RP/P/GP SIN/RP/P/GP TR#/RP/P/GP SR#/RP/P/GP /TS#/RP/PGP OM/RIH IO-P/0-P/GPIO-P #RP0/P0/GP0 SOUT#/RP/P/GP RTS#/RP/P/GP RI#/RP/P/GP SIN/RP/P/GP TR#/RP/P/GP SR#/RP/P/GP TS#/RP/P/GP OM/RIH IO-P/0-P/GPIO-P #/RP0/P0/GP0 SOUT#/RP/P/GP RTS#/RP/P/GP RI#/RP/P/GP SIN/RP/P/GP TR#/RP/P/GP SR#/RP/P/GP TS#/RP/P/GP OM/RIH IO-P/0-P/GPIO-P #/RP0/P0/GP0 SOUT#/RP/P/GP RTS#/RP/P/GP RI#/RP/P/GP SIN/RP/P/GP TR#/RP/P/GP SR#/RP/P/GP TS#/RP/P/GP OM0/RIH IO-/0-/GPIO- 0#/R0/0/G0 SOUT0#/R//G RTS0#/R//G RI0#/R//G SIN0/R//G TR0#/R//G SR0#/R//G TS0#/R//G E E L K K J J J J J GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP G0 G G G G G G G GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP G0 G G G G G G G P P P P VoetexEX MP ELETRONIS IN. GPIO,RIH IO, OM Size ocument Number Rev M0 0. ate: Wednesday, ugust, 0 Sheet of
6 VOUT=0.*(+RF/RF) 00m VOUT=0.*(+RF/RF) 00m K K R R F M U M T0 V V W R K V E T R E0 V G F K U U IO Power R Power PU ore power V V V V V V V_ V V_ V V V V V V V V V V V V V V V V 0 K H E R T M M R U W W R R R J P J0 L L L0 J V V. V. V. V + uf U VIN RUN IP00 TSOT- GN SW VF RF * L.uH/0x0 RF R 00K % (VORE) RF * L.uH/0x0 RF R 00K % VOUT=0.*(+RF/RF) 00m VOUT=0.*(+RF/RF) 00m V U IP00 TSOT- V. V U IP00 TSOT- V +0 uf R 00K % pf R 00K % pf VIN RUN GN SW VF RF 0pF R 00K % L.uH/0x0 RF R 00K % 0pF R 00K % V. + uf + uf V.V V.V V + uf + uf R0 00K % 0pF R 00K % pf U VIN RUN VIN RUN IP00 TSOT- GN GN SW VF SW VF RF 0pF R K % L.uH/0x0 RF R K % 0pF R 00K % V. + uf + uf V.V V.V TP TP EL T P U REG_F REG_VTRL REG_VTRL VoetexEX REG_V REG_ REG_F U U R V EL POWER LE LE R0 K V RESET- RESET- V R K 0 Q RST V GN V R K R.K % FP0-NSGTR R K 0 PWRG RESET PWRG S-LE-00-R S0 E V. V._OUT V_IN V R 0 FM0-M MP ELETRONIS IN. Power Sequence: +V=>+.V/+.V=>.V=>.V TO Size ocument Number Rev M0 0. ate: Wednesday, ugust, 0 Sheet of
7 J () V_IN J () V_IN P0 US / ST PI-E0 LN P GN RSTRV GP00 GP0 GP0 GP0 G0 G G G LNRX- LNRX+ LNTX- LNTX+ GP0 GP GP GP GP0 GP0 GP0 GP0 G G G G _0 _ GN _0 _ 0 RSTRV GP00 GP0 GP0 GP0 G0 G G G LNTX- LNTX+ VTT GP0 GP GP GP US- US+ P0 US / ST PI-E0 PIRST- PWRG LN P US- US+ GP GP GP GP GP0 GP0 GP0 GP0 G G G G US- US+ US- US+ ST_TX- ST_RX- ST_TX- ST_TX+ ST_RX- ST_RX+ ST_TX+ ST_RX+ PE0_TX- 0 0 PE0_RX- PE0_TX- PE0_RX- PE0_TX+ PE0_RX+ PE0_TX+ PE0_RX+ PE0_LK- PIRST- PE0_LK- PIRST- PE0_LK+ RESET- PE0_LK+ RESET HEER x-.mm/ox LNRX- LNRX+ V._OUT GP GP GP GP P P P P P P P GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP GP0 GP GP GP HEER x-.mm/ox GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP P P P P P P P mm () () GN V P0 P US US VortexEX P P / ST TOP VIEW P mm PI-E LN R RM P P P P MP ELETRONIS IN. SOM--EX SOM--EX Size ocument Number Rev M0 0. ate: Wednesday, ugust, 0 Sheet of
8 YPSS V. V. V. V. V. V. V. V. V. R uF/.V.uF/.V V. V. V V.V V V V V V V. V. V. V R V V. V. + + R0 uf.v uf 0.V V V V V V 0 R V FM FM0S FM FM0S FM FM0S FM FM0S FM FM0S FM FM0S MP ELETRONIS IN. Y PSS Size ocument Number Rev M0 0. ate: Wednesday, ugust, 0 Sheet of
J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET
GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP
SVS 5V & 3V. isplsi_2032lv
PU 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF FLSH.0uF.0uF.0uF 0.0uF ata uffer.0uf.0uf.0uf.0uf SVS V & V.0uF.0uF.0uF isplsi_0lv.0uf.0uf
Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz
V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion
Generated by Foxit PDF Creator Foxit Software For evaluation only.
I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software
CONTENTS: REVISION HISTORY: NOTES:
ONTENTS: PGE - ONTENTS PGE - POWER, XOS PGE - SI, SI, JTG PGE - S/eMM, US, HMI, GPIO, OMPOSITE PGE - SOIMM REVISION HISTORY: V.0 - /0/0 NOTES: These reduced schematics omit core SMPS and LPR circuitry
DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.
R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H
RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7
Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM
Power. I/O Extensions. CPU Extensions. JADE-D Subsystem
XXSvideo- Revision: P. Power WI V_ORE_PG WI V_ORE_PG Reference I: 00 # WI PU Extensions HOST_SPI[..0] SPI_0[..0] PU_[..] PU_[..0] MEM_TRL[..0] MEM_RY VIN0_[..0] HOST_SPI[..0] S PI_0[..0] PU_[..] PU_[..0]
core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103
core Tiny0.sch M000 M000-etc.sch -etc.sch US HU US-HU.sch Tiny0SK 0 M_ VV V V V V V V V V V VN VSYN VLK VUS OTGI OTGM OTGP IN0 S_LK S_n S_T0 S_T OUT0 INT INT INT RST ( 红色 ) Tiny0 Tiny0 P Power Supply S
C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.
Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P
AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
All use SMD component if possible
R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off
Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page
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PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.
R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument
LED POWER STAGE1 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE2 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE3 NOT_EN LED+ PWM
MU LE POWER STGE MU MX LI LI_TX LI_RX THERMISTOR- MX_RX MX_TX MX_E MX_/RE EN_ EN_ EN_ EN _ V LE Power Stage LE POWER STGE LE+ LE- LE+ LE- R R 0 J 0 Way 0 LI_TX LI_RX MX_RX MX_TX MX_E MX_/RE V LE Power
NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP.
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Quickfilter Development Board, QF4A512 - DK
Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U
D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF.
POWER_KEY POWER_OFF US_IN WKEUP H_ET HG_STTUS PLYKEY +VRT VT VUS +VRT LI_.V LI_.V VUS VT VTT VTT VTT +V +V +V +V VTT V +V T uf uf R k R k uf uf R k R k VIN VOUT U XPM U XPM Vbat ON ON ON ON KW ON/OFF KW
Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header
esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use
Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.
Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT
XIO2213ZAY REFERENCE DESIGN
XIOZY REFERENE ESIGN XIOZY Reference Size ocument Number Rev ate: Wednesday, September, 00 Sheet of TP+ TP- TP+ TP- TPIS TP+ TP- TP+ TP- TPIS TP0+ TP0- TP0+ TP0- TPIS0 REFLK+ REFLK- V_ V_ V_ORE PLLV_ORE
AML7266-H. Feature table. Block Thursday, February 12, 2009 AMLOGIC AML7266-H. Main Chip: Internal: Video: Audio: Interfaces: UART USB HOST RJ45
ON Y Pb Pr is(smk,sk,slrk,s) MP U V V pin con to Mainboard IR MI MI U WM SMK,SK,SLRK MII_(ST) URT JTG con U ML-H SPI FLSH U MXL-G U NN FLSH KFGU Gb SL +.V/. POR LO U +.V RJ RMII Eth PHY U LN US HOST RMII
COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT
LTER YLONE III EP evelopment & Education OR SHEMTI ONTENT PGE TOP MEMORY OVER PGE, TOP SRM,FLSH 0 ~ 0 0 ~ 0 ISPLY VG, LE, SEGMENT 0 ~ 0 IN/OUT LOK, PS, RS, UTTON, SWITH, ONNETOR,S R 0 ~ FPG yclone II EP
nrf52840-mdk V1.0 An Open-Source, Micro Development Kit for IoT Applications using the nrf52840 SoC Revision History Function Description Page Rev.
nrf0-mk V.0 n Open-Source, Micro evelopment Kit for IoT pplications using the nrf0 So Revision History Function escription Page Rev. escription Title Sheet V.0 The First Release Power Supply US.0 Hub PLink
Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0
Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP
B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History
0-SH-0 R-0 VEG STP0 (VI to PTx) Reference esign P# 00- Revision History SHEMTI SHEET ate uthor Version omments 0. ontents, Revision History Sept., 00 Tony W. Rev. Initial schematic. 0. Overview Oct., 00
NOTE: please place R8 close to J1
Sheets, & /M_RESET PST T T0 +.V_MU R 0K /M_RESET PST T T0 +.V_MU 0.uF NOTE: please place J close to the edge of the P so that the debug cable is clear of the P when attached to the board J 0 0 M Header
KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power
KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO
L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE
LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE
Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode
Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
PTN3356 Evaluation and Applicaiton Board Rev. 0.10
E PTN Evaluation and pplicaiton oard Rev. 0.0 REVISION STORY : ------------------------------------- 0. June 0, 0 - ase on PTN_ONLY_REV.SN 0. July, 0 - OM changes due to long lead time items, LEs 0. July,
AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115
PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.
PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]
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V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH
LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND
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1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766
OMMON_H_V MT (LQFP) V emo oard for Sanyo Slim H PUH INX & PO, ST F, SVO & MPG - MT MMOY - SM, FLSH/POM VIO OUT UIO WM NM TYP VI igital V SUPPLY V igital.v MT FV Servo.V MT LO_V Laser iode.v F V PIKUP H
05 - Adaptacion Puerto Serie RXD_UC R35 0 DTR_UC R36 0 RI_UC Adaptacion Puerto Serie Señalizacion GSM R37 0 INFO_NETLIGHT R38 0
0 - limentacion 0 - onector Externo 0 - daptacion Puerto Serie 0 - Modem SIM00 TT_VOLTGE VN_ TX TX_U RX_GSM RX_GSM HRGE_STTUS P. RX RX_U TX_GSM TX_GSM ST_ ST_ P. P. P. P. R 0 R 0 TR_U RI_U TR_GSM TR_GSM
8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1
isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty
FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13
Table of ontents Title lock iagram KEZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Initial raft Revisions. Remove Motor ontrol onnector J. Remap J, J, J, J pinout. dd one series resister
0603/15p/10v L R/100MHz. 100nF/50V. 100nF/16V. 100nF/50V C105 C106 C108 C107 GND GND GND GND
+V +V 00nF/0V 00nF/0V 00nF/0V 00R/00MHz.µF/0V 00nF/V 00nF/V 0K K n.b. 0k 0k 00/p/0v 00/p/0v MHZ-.X. 00nF/V 0R 0R µ/v MK0XVLK MK0XVLK 00nF/0V 00nF/0V µ/v 00R/00MHz 0R 0 0 0 L0 0 0 R0 R0 R0 R0 L0 L0 Y0 0
Revision History. EFR32 Mighty Gecko Dual PHY Radio Board. 2.4 GHz 13dBm / MHz 14 dbm, DCDC to PAVDD. Board Function Page. Rev.
EFR Mighty Gecko ual PHY Radio oard. GHz dm / 868-9 MHz dm, to PV oard Function Page Title Page History Rev. escription. GHz RF, ntenna & Power 00 Prototype version. SubGHz RF, ntenna & Power EFR, PRO
CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2
VUS R V_IN V TO.V SETION.V SI_RX SI_TX 0E R PINOUT HEK MINISM00F- Resettable Fuse F 00m WHITE 00nF U GN EN IN IN TPS PG nc OUT OUT 0k R 0.V 00nF Power_Good MIRO US IS INITE S ON TX RX 0.uF VUS TR RI GN
Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.
PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional)
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MU THERMISTOR- MU LI_RX LI_TX LI_RX LI_TX MX_TX MX_RX MX_/RE MX_E MX_TX MX_RX MX_/RE MX_E MX_LI +.V_MU R 0K R 0K R R R R LE_POWER_STGE - Out GN J LE- -V LE Power Stage LE_POWER_STGE - Out GN J LE- -V LE
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Table of ontents Notes lock iagram FXL000L / MU ircuit Power and attery harger ircuit Rev escription Revisions Original Release Remove signal line U- pin and add additional signal line between J-pin0 and
+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:
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REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK
REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown
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Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09
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MT9V128(SOC356) 63IBGA HB DEMO3 Card
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HF SuperPacker Pro 100W Amp Version 3
HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project
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THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia
MicroL MicroLon.Sch Timers_nalog Timers_nalog.Sch IO ufferingsch IO uffering.sch Power Supply Power Supply.Sch Mitsubishi ackplane oard ate: THE UNIVERSITY OF NEWSTLE University rive allaghan NSW 0 ustralia
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Power. Video out. LGDC Subsystem
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AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index
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FUNCTION. Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers Digital Audio Interface - Test pin header. Regulator 1.2V.
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USBF USBF.prj. Title: Section: USBF-01. B Designer: Brian Ashelin Date: COMMUNICATIONS COMMUNICATIONS ADC ADC INPUT VCA 4 PAGE 7 PAGE 1 PAGE 5 PAGE 2
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Reference Schematic for LAN9252-HBI-Multiplexed Mode
Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate
2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM
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Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.
lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January,
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Renesas Starter Kit for RL78/G13 CPU Board Schematics
Renesas Starter Kit for RL/G PU oard Schematics REV REF TE RWN Y 0.0 raft.0.0 TES.00 Release.0.0 YOI.0 Release 0.0.0 YOI PGE ESRIPTION INEX RL/G Microcontroller Switches, LEs, RESET, PSU E, Serial Port
3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)
NXP VKIT-SZV Table of ontents 0 LOK IGRM N NOTS 0 I/O Headers 0 Power/MU 0 Peripherals 0 US/OSM Revisions Rev escription esigner ate X Initial raft 00 Release 0/0/ X hanged MU to SZV 0// U T I O N : This
5V_EXT J3-1 J3-1 5CSX_4A_IO39 5CSX_4A_IO37 5CSX_4A_IO40 UART0_CTS 5CSX_4A_IO32 UART0_RTS 5CSX_4A_IO29. 5CSX_IOp0 5CSX_IOn0. 5CSX_IOp1 5CSX_IOn1
JTG hain US to URT L RJ Socket PHY Micro S ard Socket HPS IO 空置 00-00 Soaseoard.(Final) PHY connect_.v V_EXT JTG_FPG_TO S_LK connect_.v SX IO N_RX connect_.v URT_TS URT_RTS RT_T S_ S_M S_T S_T S_T S_T0
Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA
Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive
+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:
+V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V SHN 0
CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H
V N N V N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H N_L N_L J ON N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H
Am186CC and Am186CH POTS Line Card
RVISION HISTORY RV. T INITILS.0 // JSK m and mh POTS Line ard Reference esign NOT: The purpose of this design is to illustrate how to connect some of the M digital blocks together. It is not intended to
INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST
N Updata /N P. R.K R 00 R 00 R.K P_SL P_S V R K SF_E U PMVF00 E SO WP VSS V HOL SK SI SF_LK V 0.UF/V SF_E SF_LK P_SL P_S SL S V SL' S' SF_E SF_LK P_SL P_S SL S V SL' S' U T 0 V WP SL S SL' S' 0.UF/V R
01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES
Table of ontents 0 TITLE PGE 0 MU 0 EUG INTERFE 0 SUPPLY 0 POWER RIGE 0 MOSFET RIVERS / VI SENSING utomotive Product Group 0 William annon rive West ustin, T 9 esigner:. ZUZEK rawn by:. ZUZEK pproved:
RETICLE 2 NORTH SW2 DPDT SOUTH. LM339A TxD1 Out 11 U2D DEC PULSE 1 FOCUSER-2 3.0V 17 CCD EAST U2A AUX -6 FOCUSER-2 FOCUSER SW1 DPDT
J KYP PWR J TX0\ RTIL RX0\ U V V NORTH V- NORTH/SH LM J RS V MIS XMIT LX00 XMIT LX00 RV MIS RV U SH V LM RN V V 0K J U LN 0 RX0\ 0 V TTRY LM Tx Out TX0\ Rx In Tx Out RTIL 0 Rx In U 0 V LM 0 PULS FOUSR-
Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI
Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector.
PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE - Power us and Switches
Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11
Table of ontents Notes lock iagram isplay and Tower onnectors MU & apacitive Touch kt Rev X X escription Revisions Initial Release ate -JUL- pproved hanged Power L colours-jul- Removed J and J dded J &