A[0..14] A[0..15] D[0..7] A[0..15] D[0..7] D[0..7] R/W I/O Phi0 MAP R/W R/W. I/O Phi0 MAP. Phi0 MAP. ROMDIS Phi2. ROMDIS Phi2. Id: 1/
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1 Power power.sch udio SOUN_OUT audio.sch Phi P[0..] P[0..] Phi P[0..] P[0..] PU Phi P[0..] P[0..] [0..] [0..] I/O MP ROMIS Phi [0..] [0..] I/O MP ROMIS Phi UL [0..] [0..] VI_S MP ula.sch LUE RE SYN M[0..] RS S _RM SROM LUE RE SYN M[0..] RS S _RM SROM VideoGenerator LUE RE SYN video.sch Memory M[0..] RS S SROM ROMIS Phi SOUN_OUT SYN_IN [0..] [0..] Tape SOUN_OUT P[0..] SYN_IN cpu.sch memory.sch tape.sch Revision Log: Issue : Last official Oric version Issue : Include all official rework from Oric Product Inc Issue : Include changes from Oric International (dd TR, R, LK,, ), Issue.: dd official support for the VSYN "hack". RL changed to a Two Pole, SK changed to a IN to add on the same place as OI does. (pin and will provide SYN IN and UIO OUT.) dded LK to allow use of a single pole relay Issue : Make the hardware VSYN working dd pins for a reset button Remove unusefull I0 and change to make /ROMIS working on all type of ROM chips. dd the possibility to use a x storing to ROM banks Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: / File: Oric.sch Title: Oric- / tmos Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
2 V SK RREL_JK + 00uF 0V I nf nf 0 nf nf nf nf nf nf nf nf nf nf nf nf 0 nf GN VI VO 0 Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /Power/ File: power.sch Title: Power supply Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
3 P[0..] GN R K 0uF + - Pwr Gnd LM I Gain Gain 0uF 0V SP P 0 R n SPEKER K R KEYOR_ONN PL 0 K_V K_INT K_OL K_OL K_GN K_OL K_ROW0 K_ROW K_ROW K_OL K_OL K_OL K_OL K_OL0 P0 P P R K P[0..] S TO TR P[0..] E SOUN_OUT n GN GN 0n 0 R R K K R K_OL K_OL K_OL K_OL K_OL K_OL K_OL K_OL0 0 H_ 0 Test V H_ H_ Y-- IO_ IO_ I IO_ IO_ IO_ ir IO_ IO_ IO_0 LK 0 P0 P P P P P P P P[0..] Phi P[0..] K_OL[0..] SHUNT 0 GN Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /udio/ File: audio.sch Title: PSG Keyboard Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
4 M[0..] M[0..] M0 M M M M M M M 0 0 I O I 0 M0 M M M M M M M 0 0 I O I I I M0 0 O M0 0 O M M M I M I M M M M M 0 M 0 M M M M RS S RS S RS S RS S S RS M0 M M M M M M M 0 0 I O I I I I M0 0 O M0 0 O M0 0 O M M M M I M I M I M M M M M M M 0 M 0 M 0 M M M M M M RS S RS S RS S RS S GN 0 I LS00 I LS00 [0..] ROMIS ROMIS SROM K RP [0..] If I is x or Original ROM, shunt pin and pin If I is x PL can be connected to a switch to select between two rom bank ONN_0X0 I PL 0K R0 GN LS00 Phi 0K R0 I LS00 I LS0 0 0 [0..] 0 0 I 0 0 VPP E OE Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /Memory/ File: memory.sch Title: RM & ROM Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: / 0 0 [0..]
5 SOUN_OUT RP 0K R 00K K R SYN_IN TPE_OUT SK IN TPE_IN n TPE_MP R 0K IOE IOE 0K RP If you don't want to use VSYN, or use relay shunt LK - + V- V+ LM I GN R K 0K RP 00n + - V+ V- GN I LM TPE_MP K R LK JUMPER Shunt LK only you want to support VSYN TPE_MP K RELY_RT IOE JUMPER LK RP 0K S TO S TO TR P GN E n E TR GN SHUNT 0 n K R GN R K P P[0..] Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /Tape/ File: tape.sch Title: Oric Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: / P[0..] GN
6 LUE RE SYN LUE RE SYN 0 R SYN_IN 00n 0 I I I I I I E E I LS O O O O O O RP RP RP RP OUT_LUE SYN_IN OUT_RE OUT_ OUT_SYN SYN_IN M R IN_ SK GN p 0 Sd d I I LS0 LS LS0 I SYN p d Sd I LS PL_LK PL_LK PL_LK I 0 O O O O E E S0 00pF 0 R 0K R R R R K K K K R K 0 RV R GN PL_OMPOSITE 00pF PL ONN_0X0 SOUN_OUT Rext ext 0 Rext ext PL_LK I LS0 R K V.pF 0pF XT.MHz R0 K IE 0 LS0 IF LS0 I LS0 p Sd d I LS p 0 Sd d I LS Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /VideoGenerator/ File: video.sch Title: PL Generation Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: / PL_LK PL_LK I LS lr I LS lr SHUNT 0 GN
7 Shunt LK if TR and R not fitted PU SW ONN_0X0 0K R SW_PUSH PL NMI K RPE Phi NMI IR RY Phi IR N NMI SYN V 0 0 Phi SO N N 0 MOS0 I 0 0 Phi 0 [0..] LK TR JUMPER NPN [0..] E R Phi MP K RP Phi I/O 0 0 PL HE I/O_ontrol IR 0 ROMIS Expansion Port [0..] [0..] K RP K RP [0..] uf 0V 0 0 Phi I/O_ontrol IR I/O 0 0 PI RS0 RS RS RS 0 MOS I Phi S S IR GN P0 P P P P P P P P0 P P P P P P P V 0 0 P0 P P P P P P P P0 P P P P P P P P[0..] P[0..] P[0..] P[0..] STR P0 P P P P P P P K Printer Port PL 0 0 HE Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /PU/ File: cpu.sch Title: PU & VI Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
8 R K IF LS0 lock Generation XT MHz [0..] 0pF [0..] [0..] I R0 K LS0 0 R0 0 R LK 0 0 V M0 M M M M M M M MPX HS00 S RS I _RM MP VI_S SROM SYN RE LUE UL_0 UL_ UL_ UL_ UL_ UL_ 0 UL_ UL_ MPX 0 0 [0..] MP VI_S SROM SYN RE LUE UL_[0..] [0..] I LS0 IE 0 LS0 I LS0 UL_ I0a Za Ia UL_0 I0b 0 Zb Ib I UL_ I0c Zc Ic UL_ LS I0d 0 Zd Id MPX S OE UL_ UL_ UL_ UL_ S RS _RM I0a Za Ia I0b Zb Ib I0 I0c Zc Ic LS I0d 0 Zd Id MPX S OE M M0 M M M M M M M[0..] M[0..] Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /UL/ File: ula.sch Title: UL & Memory decoding Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
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console cpu ide iot console.sch cpu.sch ide.sch iot.sch memory memory.sch ONN_0X0 TP TP TEST POTS & ONN_0X0 0K R0 ONN_0X0 J +V PWR_FLG F PWR_FLG N uf 0 0-0.uF p 0 Sd d U H SPRE; UNUSE PUTS MUST E HEL HGH
Note Division P1 P2 P3 P4 P5 P6 P7 P8 P1 P2 P3 P4 P5 P6 P7 P8 NOTEDIV1 NOTEDIV2 KEYBOARD_VOLTAGE VCF_IN LFO_IN FILTER_ENVELOPE. Filter.
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CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-
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Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz
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SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:
R 0K0 RST U S_ PF/0V PF/0V 0FS FS T T 0SLK N SOT N SOT Y mhz U LS0 debug port 0 do not stuff R WR S PS X/Y IN/IN IR 0IR MO J R M R 0K0 R0 K00 R 0K0 dsck dr dsi dso / G 0 U LS0 R 0K0 SI_RX SI_TX SI_LK TFS
1K21 LED GR N +33V 604R VR? 1K0 -33V -33V 0R0 MUTE SWTH? JA? T1 T2 RL? +33V 100R A17 CB? 1N N RB? 2K0 QBI? OU T JE182 4K75 RB? 1N914 D?
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RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7
Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM
Sheet_Symbol_Overspeed. HA_Vel_Feedback Dec_Vel_Feedback. HA_Overspeed_N Dec_Overspeed_N
NOTES: ISION LOK. Unless otherwise stated: Resistors are mw, % tolerance. apacitors are V, % tolerance.... J Port and Net Name scopes for this project are: Port NOT Global (connected via Sheet Symbols)
Channel V/F Converter
00 Wesbrook Mall Vancouver,.., anada VT - 0 -Nov-000 :: H:\0\sheet_.SH wg. No.: ate: File: Revision: Sheet of Time: 0 hannel V/F onverter wg List: rawn y: P. ennett isk: 0 0 0 J IN+ IN- IN+ IN- IN+ IN-
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PU 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF FLSH.0uF.0uF.0uF 0.0uF ata uffer.0uf.0uf.0uf.0uf SVS V & V.0uF.0uF.0uF isplsi_0lv.0uf.0uf
DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2
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opyright ERN. This documentation describes Open Hardware and is licensed under the ERN OHL v... You may redistribute and modify this under the terms of the ERN OHL v... (http://ohwr.org/ernohl). This documentation
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THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia
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