FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
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1 Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate R, R, R, R for production version Sep, hange all -Pin Jumpers to mm pitch dd one Jumper between R, R, R, R, R, R, RG LE Power and PV for power disconnection in low power test dd one Jumper between R, R and PV for power disconnection in low power test hange R, R to Jumper J, J hange R, R to Jumper J, J hange R, R to Jumper J, J Remove SPI Flash U ec, Remove R Pouplate J, J and J Remove cut-short of J and J ec, FRM-KLZ utomotive, Industrial & Multi- market Solutions Group William annon rive West ustin, TX - This document contains information proprietary to Freescale and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale. esigner: rawn by: pproved: IP lassification: FP: FIUO: PUI: X rawing Title: FRM-KLZ TITLE PGE Size ocument Number Rev SH- PF: SPF- Monday, ecember, ate: Sheet o f
2 IP lassification: FP: FIUO: PUI: X rawing Title: FRM-KLZ LOK IGRM Size ocument Number Rev SH- PF: SPF- Monday, ecember, ate: Sheet o f
3 G PV_KLZ J HR X J HR X U Push uttons PV_JMP PV_JMP R R K K SW NMI_UTTON LLWU_UTTON TLFQG PT PT.UF.UF SW TLFQG (pg) URT_RX_TGTMU (pg) URT_TX_TGTMU -URT_RX PT -URT_TX PT J- PT NMI_UTTON J HR X INT_EL INT_EL (pg) SW_IO_TGTMU PT R PT (pg,) PT PV_JMP J HR X PT PT PT PT PT PT (pg,) PT (pg,) PT R KL_SW_LK -TPM_H -TPM_H -LE_LUE/TPM_H EXTL_KHZ XTL_KHZ RST_K_ R K R K -I_SL/_SE -I_S/_SE J- J- J- J- LE_RE/J- LE_GREEN/J- LLWU_UTTON PT/SW_LK/TPM_H PT/URT_RX/TPM_H PT/URT_TX/TPM_H PT/SW_IO/I_SL/TPM_H PT/NMI/I_S/TPM_H PT/US_LKIN/TPM_H PT/TPM_H PT/TPM_H PT/EXTL/URT_RX/TPM_LKIN PT/XTL/URT_TX/TPM_LKIN/LPTMR_LT PT/RESET PT/LLWU_P/_SE/I_SL/TPM_H/SPI_MOSI/SPI_MISO PT/_SE/I_S/TPM_H/SPI_MISO/SPI_MOSI PT/_SE/I_SL/TPM_H PT/_SE/I_S/TPM_H PT/SPI_MOSI/URT_RX/TPM_LKIN/SPI_MISO PT/SPI_MISO/URT_TX/TPM_LKIN/SPI_MOSI PT/TPM_H PT/TPM_H V V V V VREFH VREFL VREFH PV_KLZ.UF.UF.UF.UF.UF.UF NOTE: Place these capacitors near their respective PU pin (VREFH to VREFL and V to VSS).UF.V.UF R REF PV_KLZ R E PV_JMP R K R K TOUH_ TOUH_ PTE PTE PT PT PT J- J- J- J HR X J HR X PT PT PT PT PT PT PT PT PT -_SE -SPI_S -SPI_SK -SPI_MOSI -SPI_MISO -TPM_H/MP_IN -TPM_H/MP_IN J- J- PT/_SE/EXTRG_IN/UIOUS_SOF_OUT/MP_OUT PT/LLWU_P/RT_LKIN/_SE/I_SL/TPM_H PT/_SE/I_S/TPM_H PT/LLWU_P/SPI_SK/URT_RX/TPM_H/LKOUT PT/LLWU_P/SPI_PS/URT_TX/TPM_H/SPI_PS PT/LLWU_P/SPI_SK/LPTMR_LT/MP_OUT PT/LLWU_P/MP_IN/SPI_MOSI/EXTRG_IN/SPI_MISO PT/MP_IN/SPI_MISO/UIOUS_SOF_OUT/SPI_MOSI PT/MP_IN/I_SL/TPM_H PT/MP_IN/I_S/TPM_H PT/I_SL PT/I_S SW ONNETOR PV_KLZ J Slider_ HR X Touch Interface on GPIOs SW_IO_TGTMU SHORTING HEER ON OTTOM LYER Jumper is shorted by a cut-trace on bottom layer. utting the trace will effectively isolate the on-board MU from the OpenS debug interface. HR X J KL_SW_LK SW_LK_TGTMU RST_K_ (pg,) (pg) I_SL I_S EL_RST PV_KLZ J- PT J- PT J- PT J- PT J- PT J- PT -I_S PT -I_SL PT J- PTE J- PTE -_SE PTE -_SE PTE -_SE PTE THER_ THER_ -TPM_H PTE -TPM_H PTE TOUH_ TOUH_ -TPM_H PTE L OHM.UF US_V.UF PT/SPI_PS/TPM_H/FXIO_ PT/_SE/SPI_SK/TPM_H/FXIO_ PT/SPI_MOSI/URT_RX/TPM_H/SPI_MISO/FXIO_ PT/SPI_MISO/URT_TX/TPM_H/SPI_MOSI/FXIO_ PT/LLWU_P/SPI_PS/URT_RX/TPM_H/FXIO_ PT/_SE/SPI_SK/URT_TX/TPM_H/FXIO_ PT/LLWU_P/_SE/SPI_MOSI/URT_RX/I_S/SPI_MISO/FXIO_ PT/SPI_MISO/URT_TX/I_SL/SPI_MOSI/FXIO_ PTE/LKOUTK/SPI_MISO/URT_TX/RT_LKOUT/MP_OUT/I_S PTE/SPI_MOSI/URT_RX/SPI_MISO/I_SL PTE/_P/_SE/SPI_PS/URT_TX/TPM_LKIN/FXIO_ PTE/_P/_SE/TPM_H/URT_TX/FXIO_ PTE/_M/_SE/TPM_H/URT_RX/FXIO_ PTE/_P/_SE/TPM_H/URT_TX/FXIO_ PTE/_M/_SE/TPM_H/URT_RX/FXIO_ PTE/TPM_H/I_SL PTE/TPM_H/I_S PTE/MP_IN/_SEb/TPM_H/TPM_LKIN PTE/_SE/MP_IN/TPM_H/TPM_LKIN/URT_TX/LPTMR_LT PTE/TPM_H US_V US_P US_M VSS VSS VSS VSS PKLZVLH KL_US_SHL KLZ US S I + - VUS S PV_KLZ J TP US MINI- L OHM PV_KL_US KL_US_N R US_M KL_US_P R US_P THERMISTOR PV J HR X J HR X PV_JMP PV_JMP S S L U GSOT-GS EXTL_KHZ KHz LK Y to - Vdiff ~.V to.v (Ta=.V) PV_JMP R.K J, J open in MU low power test OHM RG LE FETURE TP TP R LERG_RE LERG_GREEN R (pg,) PT PT (pg,) PV_JMP R G LERG_LUE R PT (pg,) TP LV-FK-JMFRS XTL_KHZ R M.KHZ PF PF PTE PTE THER_ THER_ R R pf pf THER_P THER_N RT K.UF t R.K IP lassification: FP: FIUO: PUI: X rawing Title: FRM-KLZ KLZ MU Size ocument Number Rev SH- PF: SPF- Monday, ecember, ate: Sheet o f
4 G U PV_S V.UF V PV_S L PV_S TP T_VT_TP VSS VT JTG_TLK/SW_LK/EZP_LK/TSI_H/PT/URT_TS/URT_OL/FTM_H JTG_TI/EZP_I/TSI_H/PT/URT_RX/FTM_H JTG_TO/TRE_SWO/EZP_O/TSI_H/PT/URT_TX/FTM_H JTG_TMS/SW_IO/TSI_H/PT/URT_RTS/FTM_H NMI/EZP_S/TSI_H/PT/FTM_H/LLWU_P S_JTG_TLK S_JTG_TI S_JTG_TO S_JTG_TMS S_SW_EN R K S_SW_EN S S VUS - + I S S J US MINI- PV_S_US_ONN_VUS S_US_ONN_N S_US_ONN_P U GSOT-GS OHM.UF R R PV_S S_US_N S_US_P R.K S_US_VOUT.UF TP TP PV_S T_EXTL_TP T_XTL_TP TP VREGIN VOUT US_M US_P EXTL XTL EXTL/PT/FTM_FLT/FTM_LKIN XTL/PT/FTM_FLT/FTM_LKIN/LPTMR_LT _SE/TSI_H/PT/I_SL/FTM_H/FTM_Q_PH/LLWU_P _SE/TSI_H/PT/I_S/FTM_H/FTM_Q_PH S_EXTL S_XTL PF S_SW_OE_ Y MHZ PF R S_RST_TGTMU K PV_S J HR X TRGET MU INTERFE SIGNLS RST_K_ (pg,) S_USSHIEL L OHM S_RST_ R K PU/P LOGI: SERIL INTERFE IS LWYS RESET WHEN US PORT IS ISONNETE S_RST_ RESET VSS _SE/TSI_H/PT/SPI_PS/URT_RTS/FTM_H/IS_TX/LLWU_P _SE/MP_IN/TSI_H/PT/SPI_PS/URT_TS/FTM_H/IS_TX_FS MP_IN/PT/SPI_PS/URT_RX/FTM_H/IS_TX_LK/LLWU_P PT/SPI_PS/URT_TX/FTM_H/MP_OUT/LLWU_P PT/SPI_SK/LPTMR_LT/IS_RX/MP_OUT/LLWU_P MP_IN/PT/SPI_SOUT/P_EXTRG/IS_RX_LK/IS_MLK/LLWU_P MP_IN/PT/SPI_SIN/US_SOF_OUT/IS_RX_FS URT_TX_TGTMU URT_RX_TGTMU S_SPI_SK S_SPI_SOUT S_SPI_SIN PV_S PV_S V U LV S_IO URT_TX_TGTMU URT_RX_TGTMU J HR X SW_IO_TGTMU EP PT/SPI_PS/URT_RTS/FTM_H/EWM_IN/LLWU_P _SE/PT/SPI_PS/URT_TS/URT_OL/FTM_H/EWM_OUT _SE/PT/SPI_PS/URT_RX/FTM_H/FTM_FLT/LLWU_P PT/MT_IRO/URT_TX/FTM_H/FTM_FLT LE GREEN S_LE R S_LE_R TP S_PT U U LV S_LK J HR X SW_LK_TGTMU LV MKXVFM OpenS INTERFE PV_S R.K S_US_PV_SENSE TP R K SPRE H buffer PV_S TRGET RESET N OOTLOER PUSH UTTON PV_JMP OpenS INTERFE JTG ONNETOR PV_S TP T SPRE_I_TP R U LV TP T SPRE_O_TP SW EVQ-PEK R K RST_K_.UF PV_S J HR X R K S_JTG_TMS S_JTG_TLK S_JTG_TO S_JTG_TI S_RST_ IP lassification: FP: FIUO: PUI: X rawing Title: FRM-KLZ OpenS interface Size ocument Number Rev SH- PF: SPF- Monday, ecember, ate: Sheet o f
5 OPTIONL OIN ELL HOLER TP - T + PV_TT uf FLSL- PV J HR X R PV_KLZ RUINO HEERS -URT_RX PT -URT_TX PT -TPM_H PT -TPM_H PTE -TPM_H PT -TPM_H PTE -TPM_H/MP_IN PT -TPM_H/MP_IN PT -TPM_H PTE -TPM_H PT -SPI_S PT -SPI_MOSI PT -SPI_MISO PT -SPI_SK PT FLSL- PV_S P-V_VIN PV_KLZ FLSL- uf U NPSTTG VIN VOUT T PV_VREG uf TP mohm Resistor in layout FLSL- R R R HR X J PV_S REF PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT -I_S -I_SL J ON X J ON X I ddress X TP R K R K PV R K TP R PV I_SL I_S ** TP R.K PV SNSR_I_S SNSR_I_S SNSR_YP.UF R.K U SL S S YP MMQ.UF VIO PV V INT INT N N N N N uf.uf * RST R K.UF PV I INERTIL SENSOR R K R R INT_EL INT_EL TP PT PT EL_RST PTE PTE PTE V VR SUPPORT J HR_X N connections, to make compatible with FXOSQ sensor * Populate these components, if FXOSQ sensor is used ** I ddress config option for FXOSQ J ON X IN OUT J ON X I MGNETOMETER P-V_VIN (pg) S_PT (pg,) RST_K_ PV uf uf uf.uf PV_KLZ FLSL- PV_US PV_US PV_S FLSL- uf -_SE PTE -_SE PT -_SE PTE -_SE PTE -I_S/_SE PT -I_SL/_SE PT P_ P_R.UF.UF.UF PV P_ P_R N V VIO PV.UF U SL S INT MG I ddress XE I_SL I_S INT_MG R INT_EL These comps are, if FXOSQ (ccelerometer & magnetometer) sensor is used IN IRUIT TEST PROING TP TP TP EUG HOOK TP IP lassification: FP: FIUO: PUI: X rawing Title: FRM-KLZ I/O Headers and Power Supply Size ocument Number Rev SH- PF: SPF- Monday, ecember, ate: Sheet o f
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