MAINS BUS (VEE AND RTN) MASTER BOARD SLAVE BOARD PORTS 1 THRU 24 PORTS 25 THRU 48 PORTS 49 THRU 72 PORTS 73 THRU 96 BOARD BLOCK DIAGRAM

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1 ustomer Notice:Linear Technology has made a best effort to and reliable operation in the actual application, omponent affect circuit performance or reliability. ontact Linear pplications Engineering for assistance. OPTIONL EUG ERFE (NOTES,, N ) ISOLTE.V OPTIONL HOST OMPUTER (NOTE ) MSTER OR MINS US ( N RTN) SLVE OR SLVE OR SLVE OR PORTS THRU PORTS THRU PORTS THRU PORTS THRU EXPNSION US INLUES:. N. TWO I USES ISOLTE MIN POWER SYSTEM LOK IGRM UP TO FOUR ORS N E ONNETE IN HIN TO PROVIE PORTS. THE FIRST OR IN THE HIN MUST E MSTER (MIRO IS STUFFE). THE OTHER ORS N E EITHER MSTERS OR SLVES; IF THEY RE MSTERS, THEIR MIROS WILL MTILLY E ISLE N THEY WILL EHVE S SLVES. THE MIN PS MUST E ONNETE TO EH OR. THE PS (.V NOM) MUST E ONNETE TO T LEST ONE OR IN THE HIN..,,, MI. SIGNLS FOR MTI SSIGNMENT OF I RESSS. SEE OTTOM RIGHT. N OPTIONL HOST OMPUTER ERFE N E USE TO:. SET THE SYSTEM POWER UGET. MONITOR STTUS. IMPLEMENT HIGH-LEVEL POWER MNGEMENT FUNTIONS SUH S PRIORITIZTION. OR LOK IGRM ONNETOR FOR HOST OMPUTER ERFE (NOTE ) MSTER ONTROL IRUITRY. (THIS IRUITRY IS NOT STUFFE ON THE SLVE ORS.).V SYS_ HOST_ HOST_S FST SHUT OWN ISOLTION RRIER (NOTE ) (NOTE ) ISO_ SIN MLR S TO LL LT HIPS -IT MIROONTROLLER I MOULE K PROGRM MEM (NOTE ) K SRM I/O PORT (NOTE ) I/O PORT (NOTE ) R0 R R PORTS THRU LT N (R = 00XY00) PORTS THRU LT N (R = 00XY0) PORTS THRU 0 LT N (R = 00XY0) S S S S_ S_ EXPNSION ONNETOR IN FROM PIOUS OR IN HIN (NOTE ) (NOTE ) X Y RESS EOER LOGI M EXPNSION ONNETOUR OUT TO NEXT OR IN HIN OPTIONL EUGGER ERFE NOTES:. TWO S N VOLTGE OMPRTOR RE USE FOR IIRETIONL ISOLTION OF HOST_S N HOST_.. THE LT HIPS RE SEGREGTE ONTO TWO I USSES. THIS LLOWS THE TWO MOST-SIGNIFINT RESS ITS (THE N PINS ON THE LT) TO E USE FOR OR I, WHILE THE LOWER TWO ITS (, 0 PINS) RE HRWIRE.. I/O PORT IS USE TO IT-NG THE TWO I USSES THT TLK TO THE LT HIPS. THIS LLOWS FOR HIGH-SPEE OPERTION SINE TWO HIPS N E RE SIMULTNEOUSLY.. I/O PORT IS USE FOR VRIOUS MIS STTUS N ONTROL SIGNLS: MSTER,, MI,, N.. THE FIRMWRE N E REPROGRMME VI THE HOST OMPUTER ERFE OR THE EUGGER ERFE.. WHEN USING THE MPL I FROM MIROHIP IN., N ISOLTE US HU IS REOMMENE.. URT ERFE IS LSO PROVIE FOR TERMINL PROGRM TO SIMPLIFY EUGGING.. THE HOST ERFE ONNETOR IS OMPTILE WITH THE 0 OR FROM LINER TEH. (NOTES,, N ) POWER FROM LT HIPS N T FROM PHYs S S S LT N (R = 00XY00) PORTS THRU LT N (R = 00XY0) PORTS THRU RJ ONNETORS WITH EGRTE HIGH-POWER POE ETHERNET MGNETIS LT N (R = 00XY0) PORTS THRU T N POWER TO Ps X Y M MSTER OR 0 0 M TELLS THE OR IF IT'S THE MSTER SLVE OR 0 0 X IS ONNETE TO THE PIN ON EH LT. SLVE OR 0 0 Y IS ONNETE TO THE PIN ON EH LT. SLVE OR 0 ONTRT NO. 0 Mcarthy lvd. Milpitas, 0 Phone: (0)-00 PPROVLS TE TEHNOLOGY Fax: (0)-00 RWN Steve R. //0 TITLE LTUHF HEKE -PORT PSE OR ( lock diagram) PPROVE Steve R. //0 SIZE GE OE WG NO ESIGNER ustom Thursday, May, 00 SLE: FILENME: T OF

2 ustomer Notice:Linear Technology has made a best effort to and reliable operation in the actual application, omponent affect circuit performance or reliability. ontact Linear pplications Engineering for assistance. EO ISION HISTORY ESRIPTION TE PPROVE 0.uF 0.uF S_ SIN SOUT 0 S S S S MI U LTUHF S_ SIN SOUT 0 S S S S MI U LTUHF 0 0 SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT 0 0.uF 00V 0.uF 00V + 0uF 00V R0.00 R0.00 R0.00 R0.00 SENSE GTE Q IRFM0 SENSE R0.00 R0.00 R0.00 R0.00 GTE Q IRFM0 SENSE R0.00 R0.00 R0.00 R0.00 GTE Q IRFM0 SENSE R0.00 R0.00 R0.00 R0.00 GTE Q IRFM0 0.uF 00V 0.uF 00V 0.uF 00V 0.uF 00V F Q. F Q. F Q. F Q. OUT TP OUT TP OUT TP OUT TP OUT OUT OUT OUT 0.uF 00V 0 0.uF 00V R0.00 R0.00 R0.00 R0.00 SENSE GTE Q IRFM0 SENSE R0.00 R0.00 R0.00 R0.00 GTE Q IRFM0 SENSE R0.00 R0.00 R0.00 R0.00 GTE Q IRFM0 SENSE R0.00 R0.00 R0.00 R0.00 GTE Q IRFM0 0 0.uF 00V 0.uF 00V 0.uF 00V 0.uF 00V F Q. F Q. F Q. F Q. OUT TP OUT TP OUT TP OUT TP OUT OUT OUT OUT R.M % R.M % R.M % R.M % R.M % R.M % R.M % R.M % Q SiS Q SiS Q SiS Q SiS Q SiS Q0 SiS Q SiS Q SiS R M R0 00 R M R 00 R M R 00 R M R 00 OUT OUT OUT OUT OUT OUT OUT OUT R M OPTIONL LE RIVE R 00 R M R0 00 R M 0 OUT OUT OUT OUT OUT R 00 OUT R M OUT R 00 OUT TP0 ONTRT NO. 0 Mcarthy lvd. Milpitas, 0 Phone: (0)-00 PPROVLS TE TEHNOLOGY Fax: (0)-00 RWN Steve R. //0 TITLE HEKE LTUHF PPROVE -PORT PSE OR ( Ports thru ) Steve R. //0 ESIGNER SIZE GE OE WG NO ustom Thursday, May, 00 SLE: FILENME: T OF

3 ustomer Notice:Linear Technology has made a best effort to and reliable operation in the actual application, omponent affect circuit performance or reliability. ontact Linear pplications Engineering for assistance. EO ISION HISTORY ESRIPTION TE PPROVE 0.uF 0.uF S_ SIN SOUT 0 S S S S MI U LTUHF S_ SIN SOUT 0 S S S S MI U LTUHF SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT uF 00V 0.uF 00V + 0uF 00V R0.00 R0.00 R0.00 R0.00 SENSE GTE Q SENSE0 GTE0 SENSE GTE SENSE GTE 0.uF 00V F0 Q. F Q. OUT TP OUT TP OUT TP OUT OUT OUT 0.uF 00V IRFM0 F IRFM0 Q. 0 OUT0 R0.00 Q0 0 0.uF TP0 R.00 Q R0.00 R.00 R0.00 R.00 R V OUT0 R.00 IRFM0 R.00 R.00 R.00 R.00 Q IRFM0 R.00 R.00 R.00 R.00 Q IRFM0 0.uF 00V 0.uF 00V F Q. 0.uF 00V R.00 R.00 R.00 R.00 SENSE GTE Q SENSE GTE IRFM0 SENSE GTE R.00 Q R.00 R.00 R.00 IRFM0 SENSE GTE R.00 Q R.00 R.00 R.00 IRFM0 0 0.uF 00V 0.uF 00V 0.uF 00V 0.uF 00V OUT TP F Q. OUT TP F Q. OUT TP F Q. OUT TP F Q. OUT OUT OUT OUT R.M % R.M % R.M % R.M % R.M % R0.M % R.M % R.M % Q SiS Q SiS Q SiS Q SiS Q SiS Q SiS Q SiS Q0 SiS R M OUT OUT0 OUT OUT OUT OUT0 OUT OUT R 00 R M R 00 R M R 00 R M R0 00 R M OPTIONL LE RIVE R 00 R M R 00 R M OUT OUT OUT OUT OUT R 00 OUT R M OUT R 00 0 OUT TP ONTRT NO. 0 Mcarthy lvd. Milpitas, 0 Phone: (0)-00 PPROVLS TE TEHNOLOGY Fax: (0)-00 RWN Steve R. //0 TITLE HEKE LTUHF PPROVE -PORT PSE OR ( Ports Thru ) Steve R. //0 ESIGNER SIZE GE OE WG NO ustom Thursday, May, 00 SLE: FILENME: T OF

4 ustomer Notice:Linear Technology has made a best effort to and reliable operation in the actual application, omponent affect circuit performance or reliability. ontact Linear pplications Engineering for assistance. EO ISION HISTORY ESRIPTION TE PPROVE 0 0.uF 0.uF S_ U LTUHF S_ SIN SOUT 0 S S S S MI U LTUHF SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SENSE GTE OUT SIN SOUT 0 SENSE GTE OUT SENSE GTE OUT SENSE GTE S S S S MI OUT SENSE GTE OUT uF 00V 0.uF 00V + 0uF 00V R.00 R.00 R.00 R.00 SENSE GTE Q IRFM0 SENSE GTE R.00 Q R.00 R.00 R.00 IRFM0 SENSE GTE R.00 Q R.00 R.00 R.00 IRFM0 SENSE0 GTE0 R0.00 Q0 R0.00 R0.00 R0.00 IRFM0 0 0.uF 00V 0.uF 00V 0.uF 00V 0 0.uF 00V OUT TP F Q. OUT TP F Q. OUT TP F Q. OUT0 TP0 F0 Q. OUT OUT OUT OUT0 0.uF 00V 0.uF 00V R.00 R.00 R.00 R.00 SENSE GTE Q IRFM0 SENSE GTE R.00 Q R.00 R.00 R.00 IRFM0 SENSE GTE R.00 Q R.00 R.00 R.00 IRFM0 SENSE GTE R.00 Q R.00 R.00 R.00 IRFM0 0 0.uF 00V 0.uF 00V 0.uF 00V 0.uF 00V OUT TP F Q. OUT TP F Q. OUT TP F Q. OUT TP F Q. OUT OUT OUT OUT R.M % R0.M % R.M % R.M % R.M % R.M % R.M % R.M % Q SiS Q SiS Q SiS Q SiS Q SiS Q SiS Q SiS Q SiS R M OUT OUT OUT OUT0 OUT OUT OUT OUT0 R 00 R M R0 00 R M R 00 R M R 00 R M OPTIONL LE RIVE R 00 R M R 00 R M OUT OUT OUT OUT OUT R0 00 OUT R M OUT R 00 OUT TP ONTRT NO. 0 Mcarthy lvd. Milpitas, 0 Phone: (0)-00 PPROVLS TE TEHNOLOGY Fax: (0)-00 RWN Steve R. //0 TITLE HEKE LTUHF PPROVE -PORT PSE OR ( Ports thru ) Steve R. //0 ESIGNER SIZE GE OE WG NO ustom Thursday, May, 00 SLE: FILENME: T OF

5 ustomer Notice:Linear Technology has made a best effort to and reliable operation in the actual application, omponent affect circuit performance or reliability. ontact Linear pplications Engineering for assistance. J 0-XR-W TR- TR+ TR- TR+ TR- TR+ TR- TR+ 0 L0 E V V L0 E OUT G G G G G JG 0-XR-W TR- TR+ TR- TR+ TR- G G TR+ G TR- TR+ G 0G L0 E V G V G L0 E OUT J 0-XR-W TR- TR+ TR- TR+ TR- 0 L E V V L E OUT G G G G G JG 0-XR-W TR+ TR- TR+ TR- TR+ TR- TR+ TR- G G TR+ G TR- TR+ G 0G L E V G V G L E OUT J 0-XR-W TR- TR+ TR- TR+ TR- TR+ TR- TR+ 0 L0 E V V L0 E OUT -0 J H H H H H JH 0-XR-W TR- TR+ TR- TR+ TR- H 0H L0 E V H V H L0 E OUT -0 J OUT OUT0 OUT OUT OUT OUT J 0-XR-W TR- TR+ TR- TR+ TR- TR+ TR- TR+ 0 L0 E V V L0 E OUT OUT0 OUT OUT OUT OUT E E E E E JE 0-XR-W TR- TR+ TR- TR+ TR- E 0E L E V E V E L E OUT K K K K K JK 0-XR-W E E TR+ E TR- TR+ TR- TR+ TR- TR+ TR- K K TR+ K TR- TR+ K 0K L E V K V K L E OUT OUT J OUT OUT J 0-XR-W H H TR+ H TR- TR+ TR- TR+ TR- TR+ TR- TR+ TR- TR+ 0 L E V V L E J H H H H H JH 0-XR-W TR- TR+ TR- TR+ TR- H H TR+ H TR- TR+ H 0H L0 E V H V H L0 E J 0-XR-W TR- TR+ TR- TR+ TR- TR+ TR- TR+ 0 L0 E V V L0 E I I I I I JI TR- TR+ TR- TR+ TR- I I TR+ I TR- TR+ 0-XR-W I 0I L0 E V I V I L0 E J 0-XR-W TR- TR+ TR- TR+ TR- TR+ TR- TR+ 0 L E V V L E I I I I I JI TR- TR+ TR- TR+ TR- I I TR+ I TR- TR+ 0-XR-W I 0I L E V I V I L E -0 J L0 E V J V J L0 E J0 J 0-XR-W TR- TR+ TR- TR+ TR- TR+ TR- TR+ 0 L E V V L E E E E E E JE 0-XR-W K K TR+ K TR- TR+ TR- TR+ TR- TR+ TR- E E TR+ E TR- TR+ E 0E L0 E V E V E L0 E K K K K K JK 0-XR-W TR- TR+ TR- TR+ TR- K 0K L E V K V K L E J J J J J J J JJ 0-XR-W TR- TR+ TR- TR+ TR- J J TR+ J TR- TR+ J 0J L E V J V J L E J F F F F F JF 0-XR-W TR- TR+ TR- TR+ TR- F F TR+ F TR- TR+ F 0F L0 E V F V F L0 E L L L L L JL 0-XR-W TR- TR+ TR- TR+ TR- L L TR+ L TR- TR+ L 0L L E V L V L L E J J J J J J JJ 0-XR-W TR- TR+ TR- TR+ TR- J J TR+ J TR- TR+ J 0J J F F F F F JF 0-XR-W TR- TR+ TR- TR+ TR- F F TR+ F TR- TR+ F 0F L E V F V F L E J L L L L L JL 0-XR-W TR- TR+ TR- TR+ TR- L L TR+ L TR- TR+ L 0L L E V L V L L E OUT S S S S S S S S S S0 S JM SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL0 SHIEL 0-XR-W S S S S S S S S S S0 S JM SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL0 SHIEL 0-XR-W ONTRT NO. 0 Mcarthy lvd. Milpitas, 0 Phone: (0)-00 PPROVLS TE TEHNOLOGY Fax: (0)-00 RWN Steve R. //0 TITLE HEKE LTUHF PPROVE -PORT PSE OR ( Ethernet connectors ) Steve R. //0 ESIGNER SIZE GE OE WG NO ustom Thursday, May, 00 SLE: FILENME: T OF

6 ustomer Notice:Linear Technology has made a best effort to and reliable operation in the actual application, omponent affect circuit performance or reliability. ontact Linear pplications Engineering for assistance. IRUITRY ON THE LEFT SIE OF THIS LINE IS NOT ESSENTIL (EXEPT WHERE NOTE); THESE OMPONENTS N E ELETE IN MOST PPLITIONS. S_ S_ R.0k R.0k S_ S_ No pull up is needed for since the PI will drive it high as well as low. The LT chips don't use clock stretching, so goes in one direction only. EO ISION HISTORY ESRIPTION TE PPROVE LOGI INPUTS. +.V NOMINL +.V E E MIN POWER INPUTS. F Q. F Q. POSITIVE J NEGTIVE uf - R k Q F TP TP 0 SMTV V R 00 TP MMZVT.SM MER NOTE: These components are essential to protect the LT chips from voltage transients on the supply that can exceed the absolute maximum rating and cause permanent damage. O NOT ELETE THESE uF 00V R.k R0 k TP R.k Q0 MMT0/SOT MER ZT V THE OMPONENTS IN THIS RETNGLE RE STUFFE ONLY ON THE MSTER OR. UV MS JP EN IS OPTIONL ERFE TO RS- PORT URT_TX URT_RX GPIO TP Q MMT0/SOT 0 J This circuit causes low-priority ports to shut down quickly if the magnitude of drops below approx. V. S HEER X OPTIONL ERFE FOR PG IN-IRUIT PG EMULTOR/ MLR EUGGER. uf MLR S_ S_ PG PG ISO_S ISO_ URT_TX URT_RX.V.V TP0 TP The +.V supply for this side of the isolation barrier can be supplied via this connector or through the.v and test points. 0.uF U PIFJG00 -IT MIROONTROLLER MLR N0/VREF+/N/R0 VSS N/VREF-/N/R N/RP/N/PMS/R PG/EMU/N/IN-/RP0/N/R0 N0/VREF/RT/RP/N/PMWR/R PG/EMU/N/IN+/RP/N/R N/RP/N/PMR/R N/IN-/RP/S/N/R N/RP/N/PM0/R N/IN+/RP//N/R PG/EMU/TMS/RP/N/PM/R VSS PG/EMU/TI/RP0/N/PM/R0 0 0 OSI/LKI/N0/R VP/ORE OSO/LKO/N/PM0/R ISVREG SOSI/RP/PME/N/R TO/RP/S/N/PM/R SOSO/TK/N0/PM/R TK/RP//N/PM/R RP/0/N/PM/R PG/EMU/PR/S/N/PM/R PG/EMU/RP//N/PM/R HOST TP NOTES ON MIROONTROLLER:. This design uses the internal FR oscillator and x PLL to produce a clock freq of approx MHz.. The internal voltage regulator is used to provide the.v for the core. Therefore the 0uF cap on pin 0 is required.. Port is used to bit-bang the two I interfaces that go to the LT chips.. Port is used for optional status signals such as and MI. HOST_ R 0 R 0 0.uF 0.uF.V ISO.V ISO MO0 MO0 MLR 0.uF The PI must be able to stretch the clock when responding to a read command from the host, so both ISO_S and ISO_ are bidirectional. To avoid positive feedback in the optos, three-level logic is used: the voltage comparators drive the LEs only when the PI is pulling the line low. 0.uF PI I/O SPES: VIL < 0. VOL < HPL-0L SPES: 0. > VOL > 0. MSTER MI GPIO 0uF EXPNSION IN FROM PIOUS OR J 0 0 R 00k R0 00k Q SS/SOT TP TP Q SS/SOT 0 0 J When multiple boards are plugged together, this logic automatically configures the and lines such that all LT chips have a unique I address. EXPNSION OUT TO NEXT OR MLR TP S R 00 RE NW- 00V R.K R.K OPTIONL ERFE TO HOST OMPUTER. J.V 0 HOST_ HOST_S HOST TP HOST S TP.V R 00k.V R 00k The user should provide pull-up resistors on HOST_S and HOST_ external to this board. The 00k resistors are included here so these inputs don't float when no host is connected..v U V NWZ0 0.uF.V ISO R R 0.uF HPL-0L.V ISO HPL-0L R R 0.uF S V+ V- R R R.0k U LTS 0.uF U0 S LTS R.0k V+ V- ISO_ ISO_S R.0k (0.V) R.0k S-0-L--HE SMTE S_ S_ MI SPRE MSTER MSTER is high only on the first board in the chain. The other boards likely won't have the micro stuffed, but if they do, the MSTER signal mutes them so only one micro is the master. TSS-0-0-G--R SMTE R 0 TP TP ONTRT NO. 0 Mcarthy lvd. Milpitas, 0 Phone: (0)-00 PPROVLS TE TEHNOLOGY Fax: (0)-00 RWN Steve R. //0 TITLE HEKE LTUHF PPROVE -PORT PSE OR ( Microcontroller) Steve R. //0 ESIGNER SIZE GE OE WG NO ustom Thursday, May, 00 SLE: FILENME: T OF

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