FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M.
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1 Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Revisions Initial raft ate 0/0/ pproved M. NORMN Release to production 0/0/ M. NORMN X hanges made to KLZ XTL ircuit Fixed J0 orientation. Initial Re-spin Prototype revision Re-spin release 0/0/ 0// 0// 0/0/ M. NORMN M. NORMN M. NORMN M. NORMN FREEOM KLZ utomotive, Industrial & Multi- Market Solutions Group 0 William annon rive West ustin, TX - esigner: RFEL EL REY rawn by: RFEL EL REY pproved: MIHEL NORMN IP lassification: FP: FIUO: PUI: X rawing Title: FRM-KLZ TITLE PGE Size ocument Number Rev SH- PF: SPF- Friday, July, 0 ate: Sheet of
2 . Unless Otherwise Specified: ll resistors are in ohms, %, / Watt ll capacitors are in uf, 0%, 0V ll voltages are ll polarized capacitors are aluminum electrolytic. Interrupted lines coded with the same letter or letter combinations are electrically connected.. evice type number is for reference only. The number varies with the manufacturer.. Special signal usage: _ enotes - ctive-low Signal <> or [] enotes - Vectored Signals. Interpret diagram in accordance with merican National Standards Institute specifications, current revision, with the exception of logic block symbology. IP lassification: FP: FIUO: PUI: rawing Title: FRM-KLZ LOK IGRM Size ocument Number Rev SH- PF: SPF- Thursday, July, 0 ate: Sheet of
3 G V S S L PV_KLZ J ONN US MINI- PV0_US_ONN_VUS 0 OHM.0UF KLZ ecoupling aps SHIEL_K0US I + - S S US_ONN_N US_ONN_P T_US_I_TP TP PV_KLZ R US_N R US_P 0.0UF.0UF.0UF 0.UF 0.UF 0.UF U GSOT0-GS0 L 0 OHM KLZ US ONNETOR PV_KLZ SH SOLER SHORT PV_KLZ 0.UF VREFH R 0 NP REF NOTE: Please place these capacitors near their respective PU pin (VREFH to VREFL and V to VSS) 0.UF V V 0 V V VREFH VREFL 0 VSS U PTE PTE PTE PTE I0_SL I0_S PTE TP US_VOUT.UF PTE0/URT_TX/RT_LKOUT/MP0_OUT/I_S PTE/SPI_MOSI/URT_RX/SPI_MISO/I_SL PTE/SPI_SK PTE/SPI_MISO/SPI_MOSI PTE/SPI_PS0 PTE PTE0 PTE0/0_P0/0_SE0/FTM_H0/URT0_TX PTE PTE/0_M0/0_SE/FTM_H/URT0_RX PTE PTE/0_P/0_SE/FTM_H0/URT_TX PTE PTE/0_M/0_SE/FTM_H/URT_RX PTE/FTM0_H0/I0_SL PTE/FTM0_H/I0_S PTE0 PTE0/0_OUT/0_SE/MP0_IN/FTM0_H/FTM_LKIN PTE/FTM0_H PV_KLZ VREGIN US_N 0 VOUT US_P US0_M US0_P PTE/MP0_IN/0_SE/FTM0_H/FTM_LKIN0 PT0/TSI0_H/FTM0_H/SW_LK PT/TSI0_H/URT0_RX/FTM_H0 PT/TSI0_H/URT0_TX/FTM_H PT/TSI0_H/I_SL/FTM0_H0/SW_IO 0 PT/TSI0_H/I_S/FTM0_H/NMI PT/US_LKIN/FTM0_H PT/FTM_H0 PT/FTM_H PT/SPI0_PS0/URT0_TX PT/SPI0_SK/URT0_RX PT/SPI0_MOSI/SPI0_MISO PT/SPI0_MISO/SPI0_MOSI 0 PT/EXTL0/URT_RX/FTM_LKIN0 PT/XTL0/URT_TX/FTM_LKIN/LPTMR0_LT PT0/RESET PT0/LLWU_P/0_SE/TSI0_H0/I0_SL/FTM_H0 PT/0_SE/TSI0_H/I0_S/FTM_H PT/0_SE/TSI0_H/I0_SL/FTM_H0 PT/0_SE/TSI0_H/I0_S/FTM_H PT/EXTRG_IN PT PT0/SPI_PS0 PT/SPI_SK 0 PT/TSI0_H/SPI_MOSI/URT0_RX/FTM_LKIN0/SPI_MISO PT/TSI0_H0/SPI_MISO/URT0_TX/FTM_LKIN/SPI_MOSI PT/TSI0_H/FTM_H0 PT/TSI0_H/FTM_H KL_SW_LK EXTL XTL PT PT PTE SW_IO_TGTMU RST_TGTMU 0 pg() pg(,,) PT PT PT0 PT TSI0_H TSI0_H0 pg(,) INT_EL INT_EL PT PT PF 0 NP R.0M Y MHZ R R K K PF URT_RX_TGTMU URT_TX_TGTMU pg() pg() TSI PITIVE/TOUH INTERFE E PT0/0_SE/TSI0_H/EXTRG_IN/MP0_OUT PT/LLWU_P/RT_LKIN/0_SE/TSI0_H/I_SL/FTM0_H0 PT/0_SE/TSI0_H/I_S/FTM0_H PT/LLWU_P/URT_RX/FTM0_H/LKOUT PT/LLWU_P/SPI0_PS0/URT_TX/FTM0_H PT/LLWU_P/SPI0_SK/LPTMR0_LT/MP0_OUT PT/LLWU_P0/MP0_IN0/SPI0_MOSI/EXTRG_IN/SPI0_MISO PT/MP0_IN/SPI0_MISO/SPI0_MOSI PT/MP0_IN/I0_SL/FTM0_H PT/MP0_IN/I0_S/FTM0_H PT0/I_SL PT/I_S PT/FTM_LKIN0 0 PT/FTM_LKIN pg(,) PT0 PT PT PT PT PT PT0 PT PT PT Slider_ PT PT PT PT VSS VSS VSS PT0/SPI0_PS0/FTM0_H0 PT/0_SE/SPI0_SK/FTM0_H PT/SPI0_MOSI/URT_RX/FTM0_H/SPI0_MISO PT/SPI0_MISO/URT_TX/FTM0_H/SPI0_MOSI PT/LLWU_P/SPI_PS0/URT_RX/FTM0_H PT/0_SE/SPI_SK/URT_TX/FTM0_H PT/LLWU_P/0_SE/SPI_MOSI/URT0_RX/SPI_MISO 0 PT/SPI_MISO/URT0_TX/SPI_MOSI 0 pg(,) PT PT PKLZVLK KINETIS KLZ MU RG LE FETURE PT R 0 TP TP LERG_RE LERG_GREEN R PV R G 0 LERG_LUE R 0 TP LV-FK-JMFRS PT pg(,) SW ONNETOR pg(,) SW_IO_TGTMU J PV_KLZ 0 J NP HR X TH RST_TGTMU SHORTING HEER ON OTTOM LYER Jumper is shorted by a cut-trace on bottom layer. utting the trace will effectively isolate the on-board MU from the OpenS debug interface. pg(,,) KL_SW_LK SW_LK_TGTMU pg() pg() IP lassification: FP: FIUO: PUI: rawing Title: FRM-KLZ KLZ MU HR X Size ocument Number Rev SH- PF: SPF- Thursday, July, 0 ate: Sheet of
4 G PV_S U V.0UF V L PV_S TP VSS JTG_TLK/SW_LK/EZP_LK/TSI0_H/PT0/URT0_TS/URT0_OL/FTM0_H JTG_TI/EZP_I/TSI0_H/PT/URT0_RX/FTM0_H JTG_TO/TRE_SWO/EZP_O/TSI0_H/PT/URT0_TX/FTM0_H JTG_TMS/SW_IO/TSI0_H/PT/URT0_RTS/FTM0_H0 NMI/EZP_S/TSI0_H/PT/FTM0_H S_JTG_TLK S_JTG_TI S_JTG_TO S_JTG_TMS S_SW_EN PV_S R 0K T_VT_TP VT S_SW_EN S_USSHIEL I + - V S S S S J 0 OHM ONN US MINI- PV0_S_US_ONN_VUS S_US_ONN_N S_US_ONN_P T_S_US_I_TP TP U GSOT0-GS0 L.0UF PV_S S_EXTL EXTL/PT/FTM0_FLT/FTM_LKIN0 S_XTL Y XTL/PT/FTM_FLT0/FTM_LKIN/LPTMR0_LT S_US_VOUT VREGIN R S_US_N VOUT R S_US_P US0_M US0_P MHZ PF PF NP NP 0_SE/TSI0_H0/PT0/I0_SL/FTM_H0/FTM_Q_PH 0.UF 0_SE/TSI0_H/PT/I0_S/FTM_H/FTM_Q_PH 0 EXTL XTL TP TP T_EXTL_TP T_XTL_TP RESET S_SW_OE_ R PV_S 0K TRGET MU INTERFE SIGNLS RST_TGTMU URT_RX_TGTMU pg(,,) URT_TX_TGTMU pg() pg() 0 OHM PV_S R.K S_RST R 0K PU/P LOGI: SERIL INTERFE IS LWYS RESET WHEN US PORT IS ISONNETE TP S_RST VSS EP S_SPI0_RST_ 0_SE/TSI0_H/PT/SPI0_PS/URT_RTS/FTM0_H0/IS0_TX0 S_SPI0_S 0_SE/MP_IN0/TSI0_H/PT/SPI0_PS/URT_TS/FTM0_H/IS0_TX_FS URT_TX_TGTMU MP_IN/PT/SPI0_PS/URT_RX/FTM0_H/LKOUT/IS0_TX_LK URT_RX_TGTMU PT/SPI0_PS0/URT_TX/FTM0_H/MP_OUT S_SPI0_SK PT/SPI0_SK/LPTMR0_LT/IS0_RX0/MP0_OUT S_SPI0_SOUT MP0_IN0/PT/SPI0_SOUT/P0_EXTRG/IS0_RX_LK/IS0_MLK S_SPI0_SIN MP0_IN/PT/SPI0_SIN/US_SOF_OUT/IS0_RX_FS PV_S R 0 PT/SPI0_PS/URT0_RTS/FTM0_H/EWM_IN 0 0_SE/PT/SPI0_PS/URT0_TS/URT0_OL/FTM0_H/EWM_OUT 0_SEb/PT/SPI0_PS/URT0_RX/FTM0_H/FTM0_FLT0 PT/MT_IRO/URT0_TX/FTM0_H/FTM0_FLT LE GREEN S_LE S_LE_R TP0 S_PT S_SPI0_SOUT S_SPI0_SIN PV_S U V LV U 0 LV U SW_IO_TGTMU pg() SW_LK_TGTMU pg() S_SPI0_SK TRGET RESET N OOTLOER PUSH UTTON PV PK0XVFM OpenS INTERFE S_PT R 0 PV_S R0.K pg(,) KLZ Pin PT/LLWU_P/RT_LKIN LV pg(,,) RST_TGTMU R 0K SW S_US_PV_SENSE TP R 0K.0UF EVQ-PE0K SPRE H buffer PV_S TP U T SPRE_I_TP LV TP T SPRE_O_TP SPI FLSH MEMORY TP S_SPI0_SOUT TP S_SPI0_SK TP S_SPI0_RST_ TP S_SPI0_S SI SK U RSET_ S_ V SO WP_ SUSSEMLY_S0 T-S OR TE-SSH PV_S S_SPI0_SIN PV_S TP0 OpenS INTERFE JTG ONNETOR PV_S R 0K J PV_S S_JTG_TMS S_JTG_TLK S_JTG_TO S_JTG_TI 0 S_RST HR X IP lassification: FP: FIUO: PUI: rawing Title: FRM-KLZ OpenS interface Size ocument Number Rev SH- PF: SPF- Thursday, July, 0 ate: Sheet of
5 OPTIONL OIN ELL HOLER T TP P-V_VIN PV_S PV_KLZ T U PV_TT 0uF TP PV SHORTING HEER ON OTTOM LYER J HR X TH PV_KLZ 0uF NPSTTG VIN VOUT T PV_VREG 0uF T 0mOhm Resistor in layout NP SHORTING HEER ON OTTOM LYER J HR X TH PV_S NP pg() 0 pg() pg() pg() pg() pg() pg() pg() pg() pg() pg() 0 pg() pg() pg() EUG GROUN HOOK TP pg() pg() pg() REF I INERTIL SENSOR PV 0 0.UF PV PV 0uF pg() pg() PT PT J ON_X ON X J IN IRUIT TEST PROING TP TP TP R R.K.K PV U pg() I0_SL R0 SL pg() I0_S 0K S TP MM_SERIL_R0 S0 TP MM_YP R YP 0K NP 0.UF MMQ VIO 0 V INT INT N N N N N INT_EL INT_EL pg() pg() pg() PTE pg() PT pg() PT pg() PT pg() PT pg() PT pg() PT pg() PT pg() PT0 pg() PT pg() PT pg() PT pg() PT pg() PT0 pg() PT pg() PTE0 pg() PTE pg() PTE pg() PTE pg() PTE pg() PTE0 pg() PTE pg() PTE pg() PTE pg() PTE pg() PT pg() PT0 pg() PT pg() PT PV_S PV_KLZ ON X PV J 0 ON X SKT J0 T pg(,) RST_TGTMU.UF 0 PV_US PV P-V_VIN pg() S_PT pg() pg() pg() pg() pg() pg(,) 0 IP lassification: FP: FIUO: PUI: rawing Title: FRM-KLZ RUINO SHIELS & PWR SUPPLY Size ocument Number Rev SH- PF: SPF- Thursday, July, 0 ate: Sheet of
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