3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)
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1 NXP VKIT-SZV Table of ontents 0 LOK IGRM N NOTS 0 I/O Headers 0 Power/MU 0 Peripherals 0 US/OSM Revisions Rev escription esigner ate X Initial raft 00 Release 0/0/ X hanged MU to SZV 0// U T I O N : This schematic is provided for reference purposes only. s such, Freescale does not make any warranty, implied or otherwise, as to the suitability of circuit design or component selection (type or value) used in these schematics for hardware design using the NXP S family of Microprocessors. ustomers using any part of these schematics as a basis for hardware design, do so at their own risk and Freescale does not assume any liability for such a hardware design. ifferent test points used in design: TPx - Test point pad TPHx - Through Hole Pad Large (for standard 0." header). lso used on IO Matrix (IOMx) TSx - Surface Mount Wire Loop User notes are given throughout the schematics. Specific P LYOUT notes are detailed in ITLIS Notes: - ll components and board processes are to be ROHS compliant - ll connectors and headers are denoted Jx/Px and are.mm pitch unless otherwise stated - ll jumpers are denoted Jx. - Jumper default positions are shown in the schematics. For way jumpers, default is always position -. Pin jumpers generally have the "source" on pin. - ll switches are denoted SWx - ll test points (SMT wire loop style) are denoted TPx - Test point Vias (just through hole pads) are denoted TPVx esigner: rawn by: pproved: IP lassification: P: PUI: rawing Title: utomotive Product Group 0 William annon rive West ustin, TX - VKIT-SZV TITL N NOTS Size ocument Number Rev SH- PF: SPF- ate: Monday, January, 0 Sheet of
2 esigner: rawn by: pproved: IP lassification: P: PUI: rawing Title: utomotive Product Group 0 William annon rive West ustin, TX - VKIT-SZV LOK IGRM Size ocument Number Rev SH- PF: SPF- ate: Monday, January, 0 Sheet of
3 pag() PT pag() PT pag() PT pag() PT pag() PT R.K R.K J ON_X0 0 J ON X pag(,) N0 R 0 0.uF RF pag(,) PJ0 pag(,) PJ SL S 0 GN pag() PS pag() PS0 pag() PS pag() PS pag(,) PP pag() PP pag() PT pag(,) PP pag(,) PP pag() PP pag() PP pag() PP pag() PP0 pag() PS pag() PS /SK /MISO /MOSI /SS TX RX R 0 R 0 NOT: J,J,J and J: rduino UNO compatible headers. PV0 PV_LR pag(,) N0 pag(,) N pag(,) PJ0 pag(,) PJ pag() N pag() N pag() N pag() N pag() N pag() N SL S R 0 R 0 R 0 R 0 R.K R.K 0.uF 0 0.uF 0.uF pag(,) RST_ SRU0PQ 0 0.uF VIN J VIN 0.uF J 0 0 SMT SQ-0--T- pag(,) P0 pag(,) P pag() P pag() P pag() P pag() P / / / / / / pag() PL pag() PL0 pag() N pag() N HVIO HVIO TP R0 0K TP pag() PS pag() PS esigner: rawn by: pproved: IP lassification: P: PUI: rawing Title: utomotive Product Group 0 William annon rive West ustin, TX - VKIT-SZV I/O HRS Size ocument Number Rev SH- PF: SPF- ate: Monday, January, 0 Sheet of
4 M Interface J0 SH SH ON PWR TP VT VT TP 0.uF 0.uF J HR X TH SRU0PQ TP + uf TS 0.uF 0.uF GN GN GN GN GN pag(,) KG R.K TP J R 0 RSTR ORNG TP R.K RST RST_ pag(,,) 0pF HR_X 0.uF 0pF SW VQ-P0W RST TP pag() N0 pag(,) N pag() N pag() N pag() N pag() N pag() N pag() N pag() N pag() N 00pF 0 00pF 00pF 00pF PF PF 00pF 00pF Y MHZ 00pF 00pF 00pF 00pF pag(,,) XTL XTL pag(,) N0 N N N N N N N N N pag() pag() pag() pag() pag() pag() pag() pag() RST_ KG PS0 PS PS PS PS PS pag(,) pag(,) pag() pag() pag() pag() PJ0 PJ pag() pag() MISO0 MOSI0 SK0 SS0_ P0 P P P P P PS PS I_SL0 I_S0 RST_ KG TL TL PS0 PS PS PS FRM-RX FRM-TX PJ0 PJ 0 0 U PS0/KWS0/MISO0/S0/RX0/PRX0 PS/KWS/MOSI0/SL0/TX0/PTX0 PS/KWS/SK0/RXN0/IRQ PS/KWS/SS0/TXN0/PR/XIRQ PS/KWS/MISO/RX/IO0_ PS/KWS/MOSI/TX/IO0_ PS/KWS/SK/IO0_ PS/KWS/SS/SNT_TX/IO0_0 P0/KW0/N0/MP0_0 P/KW/N/RTIG0/MP0_ P/KW/N/MPO0 P/KW/N/VRH_0/MP_0 P/KW/N/VRL_0/MP_ P/KW/N/MPO P/KW/N/U P/KW/N/MPP P/KW/N/MPM P/KW/N/MP P0/KW0/N0 P/KW/N P/KW/N P/KW/N P/KW/N P/KW/TRIG0/N PJ0/S0/RX0 PJ/SL0/TX0 P0/XTL P/XTL RST KG/MO TL TL TST MSZV -pin LQFP V V VSS VSS VSS 0 0 VSSX VSSX P PP0/KWP0/0_ PP/KWP/0_ PP/KWP/0_ PP/KWP/0_ PP/KWP/_/TRIG0 PP/KWP/_ PP/KWP/_ PP/KWP/_ 0 PT0/IO_0/S0/RX 0 PT/IO_/SL0/TX PT/IO_/0_ PT/IO_/0_ PT/IO0_/MISO0/GV PT/IO0_/MOSI0 PT/IO0_/SK0 PT/IO0_/SS0/LK PL0/HVI0/KWL0 PL/HVI/KWL NH NL SPLIT NH NL SPLIT TP PP0 pag() PP pag() PP pag() PP pag() PP pag(,) PP pag(,) PP pag(,) PP pag() PT0 pag() PT pag() PT pag() PT pag() PT pag() PT pag() PT pag() PT pag() PL0 pag() PL pag() TS 0UF V 0.uF xternal PNP allast Transistors - / and V 0 000pF TL R0 K TS 0.uF Q P-0 TP 0.uF 0.uF 0.uF uf 0UF TL R0 K R 0 ORNG Q P-0 V MSZVF0WLHR N connector LO Voltage Regulator 0m / SOT- NH NL TP TP TP TP0 TP TP SPLIT 0.0uF R 0. R 0. VT R 0 HR X R J PV_SWUS HR TH X PV0 SRU0PQ TP 0uF 0.uF R 0 R 0 TP U0 VIN VOUT GN 0.0UF N YP SPXM-L-- TS PV_LR 0uF 0.uF J utomotive Product Group 0 William annon rive West ustin, TX - esigner: rawn by: pproved: X IP lassification: P: IUO: PUI: rawing Title: VKIT-SZV PWR N MU Size ocument Number Rev SH- PF: SPF- Monday, January, 0 ate: Sheet of
5 L R/GRN/L TP TP TP RG L SW VQ-P0W TP User buttons P0 pag(,) LRG_R R 0 LRG_GRN R0 0 SH 0 SH 0 SH 0 PP pag(,) PP pag(,) PP pag(,) SW VQ-P0W TP P pag(,) LRG_LU R 0 0.uF 0.uF R 0.0K R 0.0K Potentiometer TP0 TP R K 0.uF R 0 0.0UF SH0 0 N pag(,) esigner: rawn by: pproved: IP lassification: P: PUI: rawing Title: utomotive Product Group 0 William annon rive West ustin, TX - VKIT-SZV USR PRIPHRLS Size ocument Number Rev SH- PF: SPF- ate: Monday, January, 0 Sheet of
6 # Pull-Up Pull-own 0 OR I RSISTN SLTION TL 0K 0K 0K 0K 0K 0K 0K 0K 0K 0.K.K.K 0K K 0K K (N) oard Rev OSM_RV 00 R0 0.0K RV R 0.0K R 0.0K RV R 0.0K R 0.0K RV0 R 0.0K +VU oard I I0 I 0 R 0.0K I0 R 0.0K R 0.0K I R 0K R 0.0K 0.uF R 0.0K on't populate R. Provision for future use. R_I0 R_I P_ R_RV0 R_RV R_RV US - Power Section +VU U +VSW_N N FLG +VTRG_N N FLG IN OUT R R 0.0K 0UF 0.uF OUT 0.0K GN MI0-YM +VU POWR L L_PWR R K TPWR STTUS L L_STTUS R K TSTTUS TP R0 0.0K +VU R 0.0K +VSW_FULT +VTRG_FULT U_TX R 0.0K R 0.0K 0UF MU-OSM VOLTG TRNSLTORS +V_SW TP 0.uF +V_SW +V_SW to U > LVHTGF IR TP 0UF V V 0 0.uF PV_SWUS OSM_RX 0.uF SH 0 SH 0 TX / RX [R and R] POK-YOK: Place both jumpers with the same orientation and provide same airgap between their terminals in a square fashion. PT0 pag() PT pag() GN R 0 TP R.0 U TZU--F R +V_SW R R U TP0 TZU--F +VSW_N +VTRG_N R_I0 R_I P_ R_RV0 R_RV R_RV TRST_OUT TPWR TSTTUS TRST_IN +VU R 0.0K OSM Interface R.K Place one 0.uF cap near Pin(V) & another 0.uF cap near Pin(V/VRFH) U_IRQ* U_RST_ U_KG +VTRG_N 0 0 U PT0/MISO/P0 PT/MOSI/P PT/SPSK/P PT/SS/P PT/KIP/P PT/KIP/P PT0/SL PT/S PT PT/Tx PT PT/Rx PT0/P/MP+ PT/P/MP- PT/KIP/MPO PT IRQ/TPMLK RST KG/MS PT0 PT V/VRFH V VSS/VRFL VSS VSSOS GN TP +VU 0.uF 0.uF 0UF PT0/Tx 0 PT/Rx PT/TPMH0 PT/TPMH PT/MISO PT/MOSI PT/SPSK PT/SS PTF0/TPMH PTF/TPMH PTF/TPMH0 PTF/TPMH PTF PTG0/KIP0 PTG/KIP PTG/KIP PTG/KIP PTG/XTL PTG/XTL VUS USN USP 0 SH 0 SH 0 TGN_IN TGN_OUT TGN_N +VSW_FULT +VTRG_FULT XTL_PU XTL_PU 0UF TP U_RX TP R.K R 0M 0.uF Y MHz PF PF +V_SW to < U LVHTGF V IR V R 0 U LVHTGF IR GN +V_SW OSM_TX V V TGN GN Place the componenets as close as possible to the OSM MU pins. 0.uF 0.uF SH 0 KG KG pag() R R 0.0K J MS0JM0GT pag(,) RST_ SH 0 U TZU--F R R TP TRST_IN efault: No shunt ootloader nable TP +VU R 0.0K OS_UG J HR X +VU R 0.0K TP 000PF +VU L 0OHM U OSM_US_N R OSM_US_P R J MIRO US US_VUS US_N US_P 0 0.uF S S V - + I G L S S 0OHM utomotive Product Group 0 William annon rive West ustin, TX - esigner: rawn by: pproved: X IP lassification: P: IUO: PUI: rawing Title: VKIT-SZV US/OSM Size ocument Number Rev SH- PF: SPF- Monday, January, 0 ate: Sheet of
NXP Automotive S12ZVMBEVB C U S T O M E R E V B
NXP utomotive SZVMEV U S T O M E R E V Table of ontents 0 PWR SUPPLY / LIN INTERFE 0 ZZVM MU 0 MOTOR ONTROL 0 NLOG SENSE 0 USER PERIPHERLS 0 OSM Revisions Rev escription X Initial raft 00 Release Prototype
S08P-LITE. 1 Title Page 2 Block Diagram 3 MCU & Arduino Headers 4 OSBDM & Power Supply 5 On-board Peripherials S08P-LITE. 23-Jun-17. V3.
Title Page lock iagram MU & rduino Headers OSM & Power Supply On-board Peripherials Revisions Rev escription ate -Jun- V.0 -Feb- pproved Microcontroller Product Group 0 William annon rive West ustin, T
2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM
Table of ontents Notes MS0LGLK Touch Sensors Touch Sensors Power OSM US OM L Revisions Rev escription X First raft X Replaced, M RN with sigle resistors Updated Power section Swapped LE_ER, with ER, to
FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13
Table of ontents Title lock iagram KEZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Initial raft Revisions. Remove Motor ontrol onnector J. Remap J, J, J, J pinout. dd one series resister
Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA
Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive
Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:
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AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
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AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate
Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11
Table of ontents Notes lock iagram isplay and Tower onnectors MU & apacitive Touch kt Rev X X escription Revisions Initial Release ate -JUL- pproved hanged Power L colours-jul- Removed J and J dded J &
Revisions Rev Description X1 A. Designer J.Sanchez J.Sanchez B Initial Release J.Sanchez. Prototype C A U T I O N :
SKEV-Q U S T O M E R E V Table of ontents TITLE N NOTES Notes and lock iagram SK MU OPEN S Power Supply/SW I/Os HEERS Revisions Rev escription X Prototype esigner J.Sanchez J.Sanchez Initial Release J.Sanchez
01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES
Table of ontents 0 TITLE PGE 0 MU 0 EUG INTERFE 0 SUPPLY 0 POWER RIGE 0 MOSFET RIVERS / VI SENSING utomotive Product Group 0 William annon rive West ustin, T 9 esigner:. ZUZEK rawn by:. ZUZEK pproved:
FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M.
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Revisions Initial raft ate 0/0/ pproved M. NORMN Release to production 0/0/ M. NORMN X hanges made
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Table of Contents 1 TITLE PAGE
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PA50 Amplifier Operation and Maintenance Manual
Eclipse Series RF Technology rfinfo@rftechnology.com.au October 00 Revision PA0 Amplifier Operation and Maintenance Manual This manual is produced by RF Technology Pty Ltd 0/ Leighton Place, Hornsby NSW
[1] [1] C7 10nF. C4 10nF SCL [2] SDA [2] CS_SD PWR_PRSNT [4] INT_BTN0 [2] INT_BTN1 [2] LOADER_EN [4] [1] TXLED [1] J11 [1] RST +3V3 RST
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Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.
lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January,
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Revision History. EFM32 Wonder Gecko MCU Plugin. Rev. Description. Board Function. Page. EFM32 Wonder Gecko MCU Plugin Board
EFM Wonder Gecko MU Plugin oard Function Page History Rev. escription Front Page EFM Microcontroller Initial Version. Imported from GG MU Plugin oard. EFM Power EFM onnectors Signal ssignments # Signal
For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used!
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Reference Schematic for LAN9252-HBI-Multiplexed Mode
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PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.
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SM XBEE MODULE XBEE SMT MODULE NC GND GND RF_SELECT VCC COMM/AD0/DIO0 AD1/DIO1 DOUT/DIO13 AD2/DIO2 DIN/CONFIG/DIO14 DIO12 AD3/DIO3 RESET RTS/DIO6
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Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI
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Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0
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DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.
R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H
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KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power
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ADC_1_AN[5]/SIUL_GPIO[64]/E[0] 49 ADC_0_AN[5]/SIUL_GPIO[66]/E[2] ADC_0_AN[7]/SIUL_GPIO[68]/E[4] ADC_0_AN[8]/SIUL_GPIO[69]/E[5]
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U V_SYS ETIMER0_ET0 ETIMER0_ET SPI_S0* SPI_SK SPI_SOUT SPI_SIN FLEXPWM0_FULT0 SPI_S0* SPI_SK FLEXN_TX FLEXN_RX FLEXN0_TX FLEXN0_RX LIN0_TX LIN0_RX LK_OUT0 0_N0 0_N GPIO GPIO GPIO GPIO, _N0, _N, _N, _N
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SHI KSI [K4554] K4554- valuation boar Rev.0 for K4554 GNRL SRIPTION K4554- is an evaluation boar for the portable igital auio 6bit / an / converter, K4554. The K4554- can evaluate / converter an / converter
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FUNCTION. Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers Digital Audio Interface - Test pin header. Regulator 1.2V.
[K-] K- K Evaluation oard Rev.0 GENERL ESRIPTION The K- is an evaluation kit for the K; a digital signal processor (SP) with channels digital data interface. It realizes an easy evaluation of the audio
PCLKS SYNCHS PDATS[3:0] PCODES[3:0] STATCLKS CMDCLKS PCLKW SYNCHW PDATW[3:0] PCODEW[3:0] Sheet_2 CMDCLKS STATCLKW CMDDATW STATDATW PDACK[1:0]
![PCLKS SYNCHS PDATS[3:0] PCODES[3:0] STATCLKS CMDCLKS PCLKW SYNCHW PDATW[3:0] PCODEW[3:0] Sheet_2 CMDCLKS STATCLKW CMDDATW STATDATW PDACK[1:0]](/thumbs/77/75221431.jpg "PCLKS SYNCHS PDATS[3:0] PCODES[3:0] STATCLKS CMDCLKS PCLKW SYNCHW PDATW[3:0] PCODEW[3:0] Sheet_2 CMDCLKS STATCLKW CMDDATW STATDATW PDACK[1:0]")
STTTW STTLKW POW[:0] PTW[:0] SYNHW PLKW Sheet_ STTTS STTLKS POS[:0] PTS[:0] SYNHS PLKS Sheet_ Spareates PLKS SYNHS PTS[:0] POS[:0] STTLKS STTTS MLKS MTS Sheet_ PLKW PLKS SYNHW SYNHS PTW[:0] PTS[:0] POW[:0]
MT9V128(SOC356) 63IBGA HB DEMO3 Card
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THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia
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MSP430F16x Processor
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institution: University of Hawaii at Manoa
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