Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.
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- Leslie Spencer
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1 PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional) -wire : S0 Temperature Sensor PGE PGE US IP Switches: Multi-function Pins IP Switches GPIO/Timer/INT/P Interfaces onnectors Power and Reset Schematic: Reset ircuit Input Power : V / Regulator V to. V / PGE URT0// Schematic: URT 0&: RS-/ pin/m URT : RS-/ pin/m URT : RS- FULL/Half RS Transceiver : ZTF RS Transceiver : ZTE Note: Please refer to X0xx Network So pplication esign Note for more detailed information. SIX ELETRONIS ORPORTION X00&X00 EV oard - System lock Size ocument Number Rev X00&X00 EV OR.SN. ate: Tuesday, February 0, 00 Sheet of
2 // // // // // // // // // // // // // // // // // // /,/ /,/ // // // // // // // // // // // // // // // // // // P0 P0 P0 P0 P0 P0 P0 P0 P P P P P P P URT0_RX URT0_TX URT_RX URT_TX TM_K TM_GT TM_K TM_GT L_LK INT SPI_SLK SS SS I_SL I_S V P0 P0 P0 P0 P0 P0 P0 P0 P P P P P P P URT0_RX URT0_TX URT_RX URT_TX TM_K TM_GT TM_K TM_GT L_LK INT SPI_SLK SS SS I_SL I_S V U X00&X00 P P L_LK URT0_RX V URT0_TX URT_RX URT_TX I_SL R I_S INT V V SPI_SLK uF P P L_LK RX0 VK TX0 RX / EI TX / EX_0 / INT0 SL S INT RST_N VK VIO SS0 SLK MOSI V + uf/v P V P P V P P P0 *Note_P. V + 0 uf/v TXON TXOP V RXIN RXIP V RSET_G P 0 VIO P P / RE_N VK P / E P P0 V VR R 0 TXON TXOP V X00&X00 RXIN RXIP V RSET_G MISO SS / Q SS / STPZ VK TM_K / EX TM_GT / EX TM_K / EX TM_GT / EX / RX P0 / TX P0 / TS P0 / SR VIO P0 / RI VK P0 / _I / LINK_LE _LKO / SP_LE _O/F_L_LE uF R.K R 0 0 XTLP XTLN V VK VIO XT SYSK_SEL XT XT 0 VIO XT XT SYSK_SEL0 XT XT0 VK P0 / TR P0 / RTS MXTLP MXTLN V V V I_OOT_IS SYS_LK_SEL URN_FLSH_K URN_FLSH_EN V TEST_SPEEUP SYN_US SYS_LK_SEL0 L_MO PROG_SRM_EN V P0 P0 O H ebugger Interface ircuit (Optional) *Note_P. O LK O TI O TO SP_LE LINK_LE FUX_LE V For O Used SP_LE R.K LINK_LE R.K FUX_LE R.K LINK_LE SP_LE FUX_LE J ON0 MXTLP 0 V V V LE G R 0 Link LE LE F R0 0 SPEE LE LE O R 0 Full/ol LE MHz +- 0ppm rystal pf R + 0 uf/v MXTLN pf I onfiguration EEPROM *Note_P. M RYSTL MHz Y 0.uF H/W onfiguration Pins SYS_LK_SEL0 SYS_LK_SEL L_MO SYN_US URN_FLSH_EN URN_FLSH_K I_OOT_IS TEST_SPEEUP PROG_SRM_EN *Note_P. S SW IP- R0 R Reference Transformer Part No. list YLJ0 YuTai Electronics o.,lt TEL:--00,0 http;// EMIL:nico_yu@yeah.net 0 V R.K R.K R.K R.K R0.K R.K R.K R.K R R0 R R R R R R.K,N K K K K K K K K K V RJ- onnector + Transformer (Turns Ratio T:T, with auto-mix) 0.uF S. &./S. &. (SYS_LK_SEL0/SYS_LK_SEL) System LK Select 00 : MHZ 0 : 0MHZ 0 : on't use : 00MHZ(V) S. &. (EXT_T) Local us Mode 0 : Master : Slave(V) S. &. (EXT_T) Synchronous us 0 : sync(v) : Sync S. &. (EXT_T)(Required) urn Flash Enable 0 : isable(v) : Enable S. &. (EXT_T) urn Flash aud Rate 0 : 00(V) : K S. &.0 (EXT_T)(Required) I oot isable 0 : Normal(V) : isable S. &. (EXT_T) Test SpeedUp 0 : Normal(V) : Enable Ext_Prog_Sram_En (EXT_T0) Pull Low : isable(v) Pull High : Enable *Note_P. ON: SINGLE RJ- ONNETOR MOULE WITH INTEGRTE 0/00 SE-TX MGNETIS (Turns Ratio T:T with uto-mix) Power and by-pass capacitors *Note_P. V.V V SS SS V TM_K TM_GT TM_K TM_GT P0 P0 P0 V P0 V P0 LINK_LE SP_LE FUX_LE V.V V L SK00T-0Y-S ohm@00mhz V.V V *Note_P. ddress : 000 U R0.K 0 R.K R.K /N V WP SL I_WP I_SL 0.uF V R.K R.K RXIN RXIP TXON TXOP R. R. V ON RX- RX+ N N N T TX- TX+ V 0.uF 0.uF 0.uF 0.uF 0.uF + uf/v 0.uF + uf/v V 0.uF T0 S I_S R.K R R uF uf YLJ0 R0 M 0.0uF 0.uF V.V V.V V.V L SK00T-0Y-S V V ohm@00mhz V V V uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF uf/v 0.uF uf/v 0.uF 0.uF 0.uF *Note_P.: The I onfiguration EEPROM is used to configure some important X0xx hardware initialization data and is required for most of X00x applications. The X00x supports the 0~ I EEPROM. *Note_P.: X00x on-chip.v to.v regulator is a low dropout regulator (LO), which requires some large external compensating capacitors on its input (pin #) and output (pin #) pins. The,, 0, and capacitors are the compensating capacitors for the on-chip regulator. *Note_P.: The o H ebugger circuit is optional if you don't need to use the o H debugger. The o interface pins are shared with the Ethernet LE pins. *Note_P.: The -bit device address of the I onfiguration EEPROM should be 00000b for X00x. That is the 0,, signals of the 0~ I onfiguration EEPROM should be pulled down. *Note_P.: The TXT and RXT pins of magnetic were connected together inside in order to support the uto-mix function. You can select the magnetic without uto-mix function (i.e. the TXT and RXT pins are separate) but need to short the TXT and RXT pins on your schematic. *Note_P.: The URN_FLSH_EN (pin #0) and I_oot_IS (pin #) configuration pins should be connected to a IP switch for X00x mass production purpose. The other configuration pins can be configured to a default setting based on your requirements. These configuration pins should be pulled high/low through a respective.k/k resistor but couldn't be connected to V/ directly or shared the same resistor each other. *Note_P.: ll power pins should be implemented with a by-pass capacitor, and the by-pass capacitor should be as close as the power pin. The analog powers and digital powers should be isolated with a Ferrite ead. SIX ELETRONIS ORPORTION X00&X00 EV oard - X00&X00 Size ocument Number Rev. X00&X00 EV OR.SN Tuesday, February 0, 00 ate: Sheet of
3 // // // // // // // // // // // // // // // // // // // // // // // // // // // P0 P0 P0 P0 P0 P0 P0 P0 P P P P P P P SS SS URT_RX URT_TX TM_K TM_GT TM_K TM_GT L_LK INT // V P0 P0 P0 P0 P0 P0 P0 P0 P P P P P P P SS SS URT_RX URT_TX TM_K TM_GT TM_K TM_GT L_LK INT V Pull Up/own GPIO Port Signals IP Switch P0 P P P *Note_P. SPI/-Wire/P/URT Interfaces IP Switch SS SS SS SS SS SS URT_RX URT_TX P0 P P P0 P0 P0 P0 P0 P0 P0 0 S S SW IP- R.K R.K R.K R.K SPI_SS SPI_SS WIRE_Q WIRE_STPZ P_EI P_EX0 RS_RO RS_I RS_E RS_RE# URT_RX URT_TX URT_TS URT_SR URT_RI URT_ URT_RTS URT_TR SPI_SS SPI_SS WIRE_Q WIRE_STPZ *Note_P. RS-/GPIO Port [0..] Interfaces IP Switch S SW IP- SW IP- RS_RO RS_I RS_E RS_RE# *Note_P. URT/GPIO Port 0 Interfaces IP Switch S 0 URT_RX URT_TX URT_TS URT_SR URT_RI URT_ URT_RTS URT_TR // // // // // // // // // // // // // // // // GPIO Port [0..] Interfaces onnectors P0 P P P P0 P0 P0 INT TM_K TM_K P_EI P_EX P_EX TM_K TM_GT TM_K TM_GT J ON J ON P P P P P0 P0 P0 P0 Timer [..]/INT Interfaces onnector J ON P Interface onnector J ON R 0 R 0 R 0 R 0 TM_GT TM_GT P_EX0 P_EX P_EX P_EX P_EX P_EX P_EX *Note_P. GPIO Port LE ontrol ircuit P P P P LE LE LE LE P0 P0 P0 P0 P0 P0 P0 P0 P P P P P P P TM_K TM_GT TM_K TM_GT URT_RX URT_TX L_LK INT R 0 R 0 R 0 R 0 R0 R R0 R00 R0 R0 R0 R0 R R0 R R R R R R V K K K K K K K K R.K R.K R.K R.K R0.K R0.K R R R K K K K K K K K K K K V SW IP- *Note_P.: The (SPI_SS, SPI_SS) and (WIRE_Q, WIRE_STPZ) poles can not be set to ON at the same time because these pins are connected to the SS and SS pins respectively. *Note_P.: The URT and RS- interfaces can not be enabled at the same time since the (URT_RX, URT_TX) and (RS_RO, RS_I) pins are connected to the same pins (i.e. and P0). *Note_P.: The GPIO Port LEs can be controlled by the web server of X00x demo firmware. SIX ELETRONIS ORPORTION X00&X00 oard - SW - GPIO - P Size ocument Number Rev X00&X00 EV OR.SN. ate: Tuesday, February 0, 00 Sheet of
4 // // // // // // // // // // // // // // // // // // URT0_RX URT0_TX URT_RX URT_TX URT_RX URT_TX URT_TS URT_SR URT_RI URT_ URT_RTS URT_TR RS_RO RS_RE# RS_I RS_E V V URT0_RX URT0_TX URT_RX URT_TX URT_RX URT_TX URT_TS URT_SR URT_RI URT_ URT_RTS URT_TR RS_RO RS_RE# RS_I RS_E V V URT0/URT RS- Transceiver RX0_IN RX_IN TX0_OUT TX_OUT V_URT URT_TX URT0_TX 0.uF 0.uF 0 R.K U ZTF/SSOP- *Note_P. + - V- R_IN R_IN R_IN R_IN R_IN T_OUT T_OUT T_OUT T_IN T_IN T_IN + V+ V - GREEN SHUTOWN INVLI ROUT 0 ROUT ROUT ROUT ROUT ROUT V_URT URT0_RX URT_RX 0.uF R.K 0.uF 0.uF V_URT U Pin connect to V_URT *Note_P. URT0/URT Interface Switch S RX0_IN RX_IN TX0_OUT TX_OUT SW PT L SK00T-0Y-S V P_ P_ V_URT URT0/URT RS- onnector P_ P_ V P ONNETOR -M L SK00T-0Y-S URT0_RX URT0_TX URT_RX URT_TX V_RS J ON URT RS- onnector RI_IN TR_OUT TS_IN TX_OUT RTS_OUT RX_IN SR_IN _IN URT_RX URT_TS URT_RI URT_RTS P ONNETOR -M J ON URT_TX URT_SR URT_ URT_TR URT RS- Transceiver RX_IN _IN SR_IN TS_IN RI_IN TX_OUT TR_OUT RTS_OUT URT_RTS URT_TR URT_TX 0.uF 0.uF 0 U *Note_P. ZTF/SSOP- + - V- R_IN R_IN R_IN R_IN R_IN T_OUT T_OUT T_OUT T_IN T_IN T_IN + V+ V - GREEN SHUTOWN INVLI ROUT 0 ROUT ROUT ROUT ROUT ROUT V_URT R.K URT_RX URT_ URT_SR URT_TS URT_RI 0.uF 0 0.uF 0.uF V_URT U Pin connect to V_URT + uf/v 0.uF + uf/v 0.uF *Note_P.: The URT0 and URT interfaces share the same RS- port on the X00x 0-pin development board. You can select the URT0 or URT interface by switching the URT0/URT interface switch. RS- onnector RS_TXP RS_TXN RS_RXP RS_RXN RS_TXP RS_TXN RS_RXP RS_RXN RS_RO RS_RE# RS_E RS_I ON ON J0 ON J ON RS- Transceiver RS_RO RS_RE# RS_E RS_I R 00 R 00 R 00 R 00 RS_RXP RS_RXN *Note_P. V_RS RS_TXP RS_TXN RS_RXP RS_RXN RS_TXN RS_TXP Optional for RS- Half-duplex mode R R U N RO RE# E I ZTE 0,N 0,N V N Z 0 Y N 0 0.uF Optional for RS- Termination RS_TXP RS_RXP R0 00 R 00 RS_TXN RS_RXN *Note_P.: The URT and RS- interfaces can not be enabled at the same time since the (URT_RX, URT_TX) and (RS_RO, RS_I) pins are connected to the same pins (i.e. and P0). Please refer to page # for more details. SIX ELETRONIS ORPORTION X00&X00 EV oard - URT Size ocument Number Rev X00&X00 EV OR.SN. ate: Tuesday, February 0, 00 Sheet of
5 // // // // // // // // // // // // WIRE_Q WIRE_STPZ SPI_SS SPI_SS SPI_SLK I_SL I_S V V WIRE_Q WIRE_STPZ SPI_SS SPI_SS SPI_SLK S[I_MISO I_SL I_S V V -Wire Interface ircuit/onnector V_WIRE V_WIRE R0 R R K,N WIRE_STPZ Q.K 0 WIRE_Q PMOSFET XP0MR,N R.K,N *Note_P. J0 ON SPI Interface ircuit/onnector U SPI_SS S V SO HOL SPI_WP# WP SK R SI K T V_SPI 0.uF SPI_HOL# SPI_SLK R.K V L SK00T-0Y-S V_SPI + uf/v 0.uF V L SK00T-0Y-S V_WIRE *Note_P. V_SPI *Note_P. V_SPI + uf/v 0.uF WIRE_STPZ WIRE_Q J ON WIRE_STPZ WIRE_Q SPI_SS SPI_SS J ON R.K R.K R.K SPI_SS SPI_SLK J ON SPI_SS R.K R.K R.K I EEPROM ircuit/onnector V R0 R *Note_P.: There is a -Wire temperature sensor connected to the J0 -Wire connector on the X00x 0-pin development board to demonstarte an example of the -Wire applications. I_SL I_S J ON I_SL I_S.K.K *Note_P.: The X00x SPI interface supports types of interface timing mode, namely, Mode 0 ~ Mode by configuring the SPI_SLK and SPI_SSx signals. Please refer to Section.0 of X00x datasheet for details. SIX ELETRONIS ORPORTION X00&X00 EV oard - Serial us Size ocument Number Rev X00&X00 EV OR.SN. ate: Tuesday, February 0, 00 Sheet of
6 // /,/ /,,,/ V V V V.0V/ Power Input POWER JK J S SW SPST F FUSE/ R V U RT-PL VIN VOUT J/ R 00 Output.V/ V V/.V Power onnectors V V V V J ON J ON V V V V Power LE K LE + uf/v R 0 0.uF R + uf/v 0.uF + uf/v 0.uF onnectors 0 J ON Reset ircuit *Note_P. V Option J ON S SW PUSHUTTON R 00K uf N U VIN VSS VOUT XN0MR,N R 0 R.K,N J ON J ON *Note_P.: You can consider using a R reset circuit on your X00x applications if you don't have special requirement. SIX ELETRONIS ORPORTION X00&X00 EV oard - Power-Reset Size ocument Number Rev X00&X00 EV OR.SN. ate: Tuesday, February 0, 00 Sheet of
7 V.00 Init V.0 R is changed from.k to.k R0 and R are changed from 0 to.k,n U and U Pin connect to V_URT V.0 The circuit is supported both X00 and X00 V.0 00//. dd some notes to indicate the important information of this schematic.. dd the page number information for all off-page symbols. V. 00/0/. dded more information of the configuration pins circuit in Note_P.. V. 00//. hanged default setting to high for Local us Mode of H/W onfiguration Pins. SIX ELETRONIS ORPORTION X00&X00 EV oard - History Size ocument Number Rev X00&X00 EV OR.SN. ate: Tuesday, February 0, 00 Sheet of
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isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty
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ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board
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esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use
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PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]
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V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH
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Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive
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PCLKS SYNCHS PDATS[3:0] PCODES[3:0] STATCLKS CMDCLKS PCLKW SYNCHW PDATW[3:0] PCODEW[3:0] Sheet_2 CMDCLKS STATCLKW CMDDATW STATDATW PDACK[1:0]
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STTTW STTLKW POW[:0] PTW[:0] SYNHW PLKW Sheet_ STTTS STTLKS POS[:0] PTS[:0] SYNHS PLKS Sheet_ Spareates PLKS SYNHS PTS[:0] POS[:0] STTLKS STTTS MLKS MTS Sheet_ PLKW PLKS SYNHW SYNHS PTW[:0] PTS[:0] POW[:0]
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P300. Technical Manual
+ I/Os, solenoid drivers Technical Manual icasso venue, avis, C, US Tel: -- Fax: -- Email: sales@tern.com http://www.tern.com COYRIHT, i-engine, -Engine, R-Engine and CTF are trademarks of TERN, Inc. mes
FUNCTION. Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers Digital Audio Interface - Test pin header. Regulator 1.2V.
[K-] K- K Evaluation oard Rev.0 GENERL ESRIPTION The K- is an evaluation kit for the K; a digital signal processor (SP) with channels digital data interface. It realizes an easy evaluation of the audio
PCB NO. DM205A SOM-128-EX VER:0.6
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SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:
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Quad 10GBASE-T to XAUI Converter
T-ENET-QU-10G PS-248-3 FETURES + + (4) 10G Ethernet hannels + + Protocol conversion between 10GSE-T and XUI + + Perfect for routing multiple 10 Gigabit Ethernet connections into systems and to and from
Service Information. Service. Service. Service FW-V220. Product Service Group CE Audio A02-160
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General Description. Features. Kit Contents. MAX32660 EV System Photo
lick here for production status of specific part numbers. MX0 Evaluation System Evaluates: MX0 General escription The MX0 evaluation system offers a compact development platform that provides access to
FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
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Grabber. Technical Manual
Grabber 0 MHZ Analog Signal Digitizer Technical Manual 0 th Street, Davis, CA, USA Tel: 0--00 Fax: 0--0 Email: sales@tern.com http://www.tern.com COPYRIGHT Grabber, and A-Engine are trademarks of TERN,
Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
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opyright ERN. This documentation describes Open Hardware and is licensed under the ERN OHL v... You may redistribute and modify this under the terms of the ERN OHL v... (http://ohwr.org/ernohl). This documentation
STEVAL-IDP003V1. IO-Link industrial modular sensor board based on L6362A. Description. Features
STEVAL-IDP00V IO-Link industrial modular sensor board based on LA Data brief Features Main supply voltage: V maximum STML0CZ microcontroller IO-Link PHY using the LA device for data communication with
MAU100 Series. 1W, Miniature SIP, Single & Dual Output DC/DC Converters MINMAX. Block Diagram. Key Features
MAU Series W, Miniature SIP, Single & DC/DC s Key Features Efficiency up to 0 Isolation MTBF >,000,000 Hours Low Cost Input,, and Output 3.3,,9,,,{,{9,{ and { Temperature Performance -0 to UL 9V-0 Package