PI3USB30532, PI3USB31532

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1 PIUSB0, PIUSB evaluation boards User s manual By Paul Li Table of Content.0 Introduction.0 Quick start.0 The over-stress evaluation test setup.0 The GPIO and IC control of PIUSBX.0 Appendix: PIUSB0, PIUSB and PD controller evaluation boards Schematics Page of

.0 Introduction The PIUSB0, PIUSB type-c evaluation boards are using a demo version of the Cypress CCG PD controller to control PIUSBX for the evaluation of the crossover switch functions of DP and

2 .0 Introduction The PIUSB0, PIUSB type-c evaluation boards are using a demo version of the Cypress CCG PD controller to control PIUSBX for the evaluation of the crossover switch functions of DP and USB.0..0 Quick start.. Connect the setup (figure ): Connect the +V >A power and 0V ground to external +V >A power supply for both source and sink evaluation boards. Connect to DP source (NB, etc.) and DP sink monitor using the two DP cables provided. Connect between source and sink evaluation boards using the type-c cable provided. Connect to USB.0 host using the USB.0 cable provided. Connect to USB.0 device (HDD, etc.) not provided. Figure, PIUSB0, PIUSB PD source and sink evaluation boards test setup. Start the test DP test After connections and power-on, plug the type-c cable (re-plug if needed) till the PD controller randomly fall-in DP mode (rather than USB.0 mode) as the DP mode LEDs indication below. DP mode LEDs indication (the same for both type-c cable flip and non-flip): Source evaluation board: D, D, D0 = ON; D, D, D = off Page of

3 Sink evaluation board: D, D, D, D = ON; D, D = off USB.0 test After connections and power-on, plug the type-c cable (re-plug if needed) till the PD controller randomly fall-in USB.0 mode (rather than DP mode) as the USB.0 mode LEDs indication below. SUB.0 mode LEDs indication (the same for both type-c cable flip and non-flip): Source evaluation board: D, D0, D = ON; D, D, D = off; Sink evaluation board: D, D, D = ON; D, D, D = off.0 The over stress evaluation test setup The PIUSBX evaluation boards shipping package includes two DP cables and one type-c cable to provide an overstress test setup (figure ) as to compare to the less stressful real cases using PIUSBX in source and sink system designs, as the comparison below.. Evaluation setup (figure ) has total cable, two PIUSBX passive switches in cascading, six connectors and extra trace on the two evaluation boards, as: Trace + DP source connector DP cable DP connector + PIUSBX + trace + type-c source connector type-c cable Type-C sink connector + PIUSBX + trace + DP connector DP cable DP connector in monitor. Real source system design using PIUSBX has total - type-c cable, one PIUSBX, two connectors. No cascading of PIUSBX, no extra traces, cables, connectors on evaluation boards, as: Trace + PIUSBX + type-c source connector type-c cable Type-C sink connector in monitor. Real sink system design using PIUSBX has total - type-c cable, one PIUSBX, two connectors. No cascading of PIUSBX, no extra traces, cables, connectors on evaluation boards, as: Trace + type-c source connector - type-c cable Type-C sink connector + PIUSBX in DP monitor.0 The GPIO and IC control of PIUSBX There is no need to change the original-default settings of the PIUSBX evaluation boards for all the PD evaluation tests. But for just in case needed, manual GPIO and IC control tests can be performed as following. Page of

4 Figure, the GPIO and IC control settings for source evaluation board (settings for sink evaluation board are similar) GPIO control Please refer to the configuration table for source application and configuration table for sink application in PIUSBX datasheet and figure for GPIO crossover switching control settings, also with the settings below: MODE=0 MODE= A0=0 IC control Please refer to the configuration table for source application and configuration table for sink application in PIUSBX datasheet, figure and figure for IC crossover switching control settings, also with the settings below: MODE= MODE= A0=0 A=0 Page of

PIUSBX has total three IC registers as Conf [:0], which is mapped between the IC control signals and the configuration tables (source, sink) as in figure-.

5 PIUSBX has total three IC registers as Conf [:0], which is mapped between the IC control signals and the configuration tables (source, sink) as in figure-. When using IC interface to control PIUSBX, the IC controller (in PD or MCU) will need sending total three bytes to PIUSB0 in sequence as: Start # byte for address as (assuming A_A0 set to 00, while last 0 for write) # byte for chip-id as fixed # byte for Conf [:0] control as (assuming Conf [:0]= as for USB+DPx swapped) Stop (must have stop, otherwise uncertainty may occur) Figure, the IC-control of the configuration table for source-sink (source-sink tables are the same) IC-control of PIUSBX in real application For both source and sink applications, when a type-c plug is plugging into the source or sink type-c connectors with PIUSBX and PD, the IC controller (in PD or MCU) shall IC-control PIUSBX as: DPx only, non-swap: Start (last 0 for write) stop DPx only, swapped: Page of

6 Start stop USB.0 only, non-swap: Start stop USB.0 only, swapped: Start stop USB+DPx, non-swap: Start stop USB+DPx, swapped: Start stop.0 Appendix: PIUSB0, PIUSB and PD controller evaluation boards schematics Page of

7 SHELL + 0 RX+ RX- AUX+ AUX- SHELL SHELL P CONF0/A CONF/SCL CONF/SDA DP0+ DP0-0 SHLD SHLD # 0u_00 J P +V NC 0 R C DP_PWR DP_PWR_RTN 0u_00 HPD AUX_CH (n) AUX_CH (p) CEC CAB_DET ML_Lane 0 (p) 0 ML_Lane 0 (n) ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) J CON_DP_Sink_Rec ept On bottom layer VUSB C C 0.uf USB_TX- USB_TX+ USB_RX- USB_RX+ DPWR D 0 CON_USB.0 TB_RECEPTACLE +V LED@LD00 Q R.K D SW R 0 R 0 R 0 R 0 R 0 R 0 SW_X_HALF_PITCH R 0 R 0 R0 0 R 0 R R R R R R.K.K.K.K.K K 0 +V CONF0/A CONF/SCL CONF/SDA A0 MODE MODE CONF/SDA CONF/SCL CONF0/A +V MODE DP+ DP- DP+ DP- DP+ 0 DP- TX+ TX- MODE A0 R 0K R 0K From _OUT U RX+ RX- TX+ TX- TX+ TX- RX+ RX- SBU SBU +V R.K 00 LED@LD00 D R0 0 PIUSBX SRC pinout J P0.K 00 R M Q R.K 00 N00 0V LED@LD00 D0 R C 0.u C 0.u C 0.u C 0.u C 0.u C 0.u C0 0.u C 0.u R M DMP0L0V.A DMP0L0V.A Q Q R 00K DMP0L0V.A Q EC 0UF_0V J P J P0 B A B A B A0 B A B A B A B A B A B A B0 A B A B A U TX+ RX+ TX- RX- CC SBU SBU CC RX- TX- RX+ TX+ Type-C Recep. Fo r DF P o nly J P R.K 00 LED@LD00 D R J P N00 0V V ext. _OUT DMP0L0V.A DMP0L0V.A Q Q C R R0.0K UF.K Q J P C 0UF/0V VUSB +V U +V EC VIN + VOUT u_ C NC EN 0u_00 PTM0 R.K 00 LED@LD00 D R R 00 Q0 C 0.UF R 00K R 0K K 00 Any NMOS>V/0.A 00K CCG C_CTRL R 00K +V R 00K R0.K 00 LED@LD00 R D 00K N00 0V HPD 0K _M ON +V CONF/SCL +V Q NC DMP0L0V.A R Q NC 0.ohm 00 DMP0L0V.A Header-pins top view J P0 C 0pf C 0pf CCX CCX CONF/SDA CONF0/A CCG DISCHARGE CCG P_CTRL PIUSB0, PIUSB source evaluation board schematic Pericom Semiconductor Corporation Size Document Name Rev C PIUS B0 P IUSB source EV B A Date: Tuesday, February, 0 Sheet of Page of //0

8 SHELL SHLD SHLD 0 TX+ TX- AUX+ AUX- P CONF0/A CONF/SCL CONF/SDA DP0+ DP0- SHELL SHELL 0 # +VSK C C C C C C C C 0u 0.u 0.u 0.u 0.u 0.u 0.u 0.u +VSK J J ML_Lane 0 (p) ML_Lane 0 (n) ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) 0 ML_Lane (p) ML_Lane (n) CAB_DET CEC AUX_CH (p) AUX_CH (n) HPD DP_PWR_RTN 0 DP_PWR CON_DP_Sourc e_rec ept J P USB_RX- USB_RX+ USB_TX- USB_TX+ C R M 0u_00 VUSB_SK C +VSK R M R 0 R 0 0u_00 R 0 R0 0 MODE DP+ DP- DP+ DP- DP+ 0 DP- RX+ RX- MODE A0 U TX+ TX- RX+ RX- RX+ RX- TX+ TX- SBU SBU 0 PIUSBX sink pinout R M R M +VSK C 0.u C0 0.u C 0.u C 0.u C 0.u C 0.u C 0.u C 0.u R M R M EC 0UF_0V V option _SK J P B A B A B A0 B A B A B A B A B A B A B0 A B A B A TX+ RX+ TX- RX- CC SBU SBU CC RX- TX- RX+ TX+ Type-C Recep. Fo r UF P o nly J P J P0 V ext. J P J P VUSB_SK +VSK U +VSK EC VIN VOUT + u_ C NC EN 0u_00 PTM0 CON_USB.0 TA_RECEPTACLE From _OUT_SK J P0 SW R 0 R 0 R 0 R 0 R0 0 R 0 SW_X_HALF_PITCH R R R R R R.K.K.K.K.K K 0 +VSK CONF0/A_SK CONF/SCL_SK CONF/SDA_SK A0_SK MODE_SK MODE_SK +VSK R0 R.K 00 LED@LD00 D R.K 00 R.K 00 N00 0V LED@LD00 D R 00K DMP0L0V.A DMP0L0V.A Q Q Q R 00K CCG C_CTRL_SK Q DMP0L0V.A R 00K DMP0L0V.A DMP0L0V.A Q Q C R R.0K UF.K Q R.K 00 LED@LD00 D R _OUT_SK N00 0V 00K R.K 00 LED@LD00 R D 00K C 0UF/0V R.K 00 LED@LD00 D R0 Q N00 0V R 00 C0 0.UF R 00K R 0K K 00.K +VSK LED@LD00 R _M ON_SK D NC (0K) +VSK Q N00 0V HPD_SK R M CONF/SCL_SK _SK +VSK DMP0L0V.A R 0.ohm 00 DMP0L0V.A Q0 NC Q NC Header-pins top view J P C 0pf C 0pf CC_SK CC_SK CONF/SDA_SK CONF0/A_SK CCG DISCHARGE_SK CCG P_CTRL_SK Pericom Semiconductor Corporation Size Document Name Rev C PIUSB0 PIUSB sink EVB A Date: Tuesday, February, 0 Sheet of PIUSB0, PIUSB sink evaluation board schematics Page of //0

9 0 0 0 # +V U +V R R R 0K 0K.K.K.K R R J P 0.uf C0 C 0.uf uf C uf C 0 D D_ IO VCCD CC_VCONN_CTRL_OCP_M ON_P. HOTPLUG_DET_P. IC_MSTR SDA_P. IC_MSTR SCL_P.0 _M ON_P. _P_CTRL_P. _C_CTRL_P. _DISCHARGE_P. CC CC_VCONN_CTRL SWD_IO_P. SWD_CLK_P. RD VTARG 0 IC_SCL_P0. IC_SDA_P0.0 C_INT_P. CC_VCONN_CTRL_OCP_M ON_P.0 CC_VCONN_CTRL CCG SWD PROGRAMMING HEADER CCG_XRES CCG_SWD_CLK CCG_SWD_IO HDR X, M OLEX -- +V R.K C 0.uf XRES CC VCONN VCONN EPAD CCG CYPQFN CCG P_CTRL SDA CCX CCX _DISCHARGE Socket bottom view (for header-pins) J P +V HPD _M ON SCL CCG C_CTRL CC_VCONN_CTRL CC_VCONN_CTRL Using the same CCG board with different firmware for both PIUSBX sink EVB and source EVB PD controller schematic for PIUSB0, PIUSB evaluation boards Pericom Semiconductor Corporation Siz e Doc ument Nam e Rev B CCG board for both PIUS BX sink source EVB A Date: Tues day, February, 0 Sheet of Page of //0

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