PART TEMP RANGE PIN-PACKAGE

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1 9-0850; Rev 4; 6/0 Ω μ INT INT μ PART TEMP RANGE PIN-PACKAGE MAX7359ETG+ -40 C to +85 C 24 TQFN-EP* MAX7359EWA+ -40 C to +85 C 25 WLP * TOP VIEW AD0 GND IC COL INPUT +62V TO +36V V CC MAX7359 COL_ ROW_ 8 8 SWITCH ARRAY, UP TO 64 SWITCHES INT V CC NC COL7/PORT7 ROW0 ROW MAX7359 EP* COL COL2/PORT2 COL5/PORT5 COL6/PORT6 ROW7 ROW INT AD0 ROW2 ROW3 COL3/PORT3 COL4/PORT4 ROW4 ROW5 GND TQFN (35mm x 35mm) *EP = EXPOSED PAD Maxim Integrated Products

2 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND) V CC -03V to +4V COL2/PORT2 COL7/PORT7-03V to +4V,, AD0, INT -03V to +6V All Other Pins-03V to (V CC + 03V) DC Current on COL2/PORT2 COL7/PORT7 25mA GND Current 80mA Continuous Power Dissipation (T A = +70 C) 24-Pin TQFN (derate 54mW/ C above +70 C) 229mW 25-Bump WLP (derate 92mW/ C above +70 C)94mW Junction-to-Case Thermal Resistance (θ JC ) (Note ) 24-Pin TQFN54 C/W 25-Bump WLP 7 C/W Junction-to-Ambient Thermal Resistance (θ JA ) (Note ) 24-Pin TQFN65 C/W 25-Bump WLP 53 C/W Operating Temperature Range (T MIN to T MAX ) -40 C to +85 C Junction Temperature+50 C Storage Temperature Range -65 C to +50 C Lead Temperature (TQFN only, soldering, 0s) +300 C Soldering Temperature (reflow) +260 C Note : Package thermal resistances were obtained using the method described in JEDEC specification JESD5-7, using a fourlayer board For detailed information on package thermal considerations, refer to chinamaxim-iccom/thermal-tutorial Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS (V CC = +62V to +36V, T A = T MIN to T MAX, unless otherwise noted Typical values are at V CC = +25V, T A = +25 C) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage V CC V Operating Supply Current I CC All key switches open, oscillator running, COL2 COL7 configured as key switches N keys pressed ( x N) μa Sleep-Mode Supply Current I SL 06 5 μa POR 0 6 V POR Hysteresis PORHYST V CC rising 42 mv Key-Switch Source Current I KEY μa Key-Switch Source Voltage V KEY Operating mode V Key-Switch Resistance R KEY (Note 4) 5 kω Startup Time from Shutdown t START 2 24 ms Output Low Voltage COL2/PORT2 to COL7/PORT7 V OLPORT I SINK = 0mA 02 V INT Output V OLINT I SINK = 0mA 05 V Oscillator Frequency F OSC 64 khz SERIAL-INTERFACE SPECIFICATIONS Serial Bus Timeout t OUT With bus timeout enabled 0 40 ms Input High Voltage,, AD0 Input Low Voltage,, AD0 V IH V IL Output Low Voltage V OLPORT I SINK = 0mA 04 V Input Leakage Current V CC = 0V to +6V - + μa 07 x V CC 03 x V CC V V 2

3 I 2 C TIMING CHARACTERISTICS (V CC = +62V to +36V, T A = T MIN to T MAX, unless otherwise noted Typical values are at V CC = +25V, T A = +25 C) (Notes 2, 3) Input Capacitance (,, AD0) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS C IN (Notes 4, 5) 0 pf Serial-Clock Frequency f Bus timeout disabled khz Bus Free Time Between a STOP and a START Condition t BUF 3 μs Hold Time (Repeated) START Condition Repeated START Condition Setup Time t HD, STA 06 μs t SU, STA 06 μs STOP Condition Setup Time t SU, STO 06 μs Data Hold Time t HD, DAT (Note 6) 09 μs Data Setup Time t SU, DAT 00 ns Clock Low Period t LOW 3 μs Clock High Period t HIGH 07 μs Rise Time of Both and Signals, Receiving Fall Time of Both and Signals, Receiving t R (Notes 4, 5) t F (Notes 4, 5) C b 300 ns C b 300 ns Fall Time of Transmitting t F, TX (Notes 4, 7) C b 250 ns Pulse Width of Spike Suppressed t SP (Notes 4, 8) 50 ns C ap aci ti ve Load for E ach Bus Li ne C b (Note 4) 400 pf Note 2: All parameters are tested at T A = +25 C Specifications over temperature are guaranteed by design Note 3: All digital inputs at V CC or GND Note 4: Guaranteed by design Note 5: C b = total capacitance of one bus line in pf t R and t F measured between +03V CC and +07V CC Note 6: A master device must provide a hold time of at least 300ns for the signal (referred to V IL of the signal) to bridge the undefined region of s falling edge Note 7: I SINK 6mA Note 8: Input filters on the,, and AD0 inputs suppress noise spikes less than 50ns 3

4 (V CC = +25V, T A = +25 C, unless otherwise noted) GPO PORT OUTPUT LOW VOLTAGE vs SINK CURRENT V CC = +24V T A = +85 C MAX7359 toc GPO PORT OUTPUT LOW VOLTAGE vs SINK CURRENT V CC = +30V T A = +85 C MAX7359 toc GPO PORT OUTPUT LOW VOLTAGE vs SINK CURRENT V CC = +36V T A = +85 C MAX7359 toc03 VOL (mv) 50 VOL (mv) 50 VOL (mv) T A = -40 C 00 T A = -40 C 00 T A = -40 C 50 T A = +25 C 50 T A = +25 C 50 T A = +25 C I SINK (ma) I SINK (ma) I SINK (ma) SUPPLY CURRENT (μa) SUPPLY CURRENT vs SUPPLY VOLTAGE AUTOSLEEP = OFF T A = +85 C T A = +25 C T A = -40 C MAX7359 toc04 KEY-SWITCH SOURCE CURRENT (μa) KEY-SWITCH SOURCE CURRENT vs SUPPLY VOLTAGE COL0 = GND T A = +85 C T A = +25 C T A = -40 C MAX7359 toc05 SHUTDOWN SUPPLY CURRENT (μa) SLEEP MODE SUPPLY CURRENT vs SUPPLY VOLTAGE MAX7359 toc SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 4

5 INT I 2 C INTERFACE *GPO MAX7359 BUS TIMEOUT 64kHz OSCILLATOR CONTROL REGISTERS FIFO POR KEY SCAN COLUMN ENABLE GPO ENABLE CURRENT DETECT ROW ENABLE CURRENT SOURCE COLUMN DRIVES OPEN- DRAIN ROW DRIVES COL0 COL COL2* COL3* COL4* COL5* COL6* COL7* ROW0 ROW ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 5

6 TQFN WLP A ROW2 2 A2 ROW3 3 A3 COL3/PORT3 4 B3 COL4/PORT4 5 A4 ROW4 6 A5 ROW5 7 B5 ROW6 8 B4 ROW7 9 C5 COL6/PORT6 0 C4 COL5/PORT5 D5 COL2/PORT2 2 E5 COL 3 E4 COL0 4 D4 IC 5 D3 GND 6 E3 AD0 7 E2 8 D2 9 E INT INT 20 D V CC μ 2 C2, C3 NC 22 C COL7/PORT7 23 B2 ROW0 24 B ROW EP INT 6

7 INT INT PIN COL0 COL COL2/PORT2 COL3/PORT3 COL4/PORT4 COL5/PORT5 COL6/PORT6 COL7/PORT7 ROW0 KEY 0 KEY 8 KEY 6 KEY 24 KEY 32 KEY 40 KEY 48 KEY 56 ROW KEY KEY 9 KEY 7 KEY 25 KEY 33 KEY 4 KEY 49 KEY 57 ROW2 KEY 2 KEY 0 KEY 8 KEY 26 KEY 34 KEY 42 KEY 50 KEY 58 ROW3 KEY 3 KEY KEY 9 KEY 27 KEY 35 KEY 43 KEY 5 KEY 59 ROW4 KEY 4 KEY 2 KEY 20 KEY 28 KEY 36 KEY 44 KEY 52 KEY 60 ROW5 KEY 5 KEY 3 KEY 2 KEY 29 KEY 37 KEY 45 KEY 53 KEY 6 ROW6 KEY 6 KEY 4 KEY 22 KEY 30 KEY 38 KEY 46 KEY 54 KEY 62 ROW7 KEY 7 KEY 5 KEY 23 KEY 3 KEY 39 KEY 47 KEY 55 KEY 63 ADDRESS CODE (hex) READ/WRITE POWER-UP VALUE (hex) REGISTER FUNCTION DESCRIPTION 0x00 Read only 0x3F Keys FIFO Read FIFO key scan data out 0x0 R/W 0x0A Configuration Power down, key release enable, autowakeup, and I2C timeout enable 0x02 R/W 0xFF Debounce Key debounce time setting and GPO enable 0x03 R/W 0x00 Interrupt INT frequency setting 0x04 R/W 0xFE Ports Ports 2 7 and INT GPO control 0x05 R/W 0x00 Key repeat Delay and frequency for key repeat 0x06 R/W 0x07 Sleep Idle time to autosleep 7

8 SPECIAL FUNCTION The key number indicated by D5:D0 is a key event D7 is always for a key press of key 62 and key 63 When D7 is 0, the key read is the last data in the FIFO When D7 is, there is more data in the FIFO When D6 is, key data read from FIFO is a key release When D6 is 0, key data read from FIFO is a key press KEYS FIFO REGISTER DATA D7 D6 D5 D4 D3 D2 D D0 FIFO empty flag Key release flag X X X X X X FIFO is empty 0 0 FIFO is overflow Continue to read data in FIFO 0 Key 63 is pressed Read one more time to determine whether there is more data in FIFO Key 63 is released Read one more time to determine whether there is more data in FIFO 0 Key repeat Indicates the last data in FIFO Key repeat Indicates more data in FIFO 0 0 Key 62 is pressed Read one more time to determine whether there is more data in FIFO Key 62 is released Read one more time to determine whether there is more data in FIFO

9 REGISTER BIT DESCRIPTION VALUE FUNCTION DEFAULT VALUE D7 Sleep 0 Sleep mode Operating mode I2C write, autosleep and autowakeup all can change this bit This bit can be read back by I2C any time for current status 0 D6 Reserved 0 D5 INTERRUPT D4 Reserved 0 D3 Key release enable D2 Reserved 0 D D0 Wakeup Timeout enable This bit must always be 0 Improper operation may result by writing a to this location 0 INT cleared when FIFO empty INT cleared after host read In this mode, I2C should read FIFO until interrupt condition removed, or further INT may be lost This bit must always be 0 Improper operation may result by writing a to this location 0 Disable Enable This bit must always be 0 Improper operation results by writing a to this location 0 Disable Key press wakeup enable 0 I2C timeout enabled I2C timeout disabled

10 REGISTER DATA REGISTER DESCRIPTION D7 D6 D5 D4 D3 D2 D D0 PORTS ENABLE DEBOUNCE TIME Debounce time is 9ms X X X Debounce time is 0ms X X X Debounce time is ms X X X Debounce time is 2ms X X X Debounce time is 37ms X X X 0 0 Debounce time is 38ms X X X 0 Debounce time is 39ms X X X 0 Debounce time is 40ms X X X GPO ports disabled (full key-scan functionality) X X X X X GPO port 7 enabled 0 0 X X X X X GPO ports 7 and 6 enabled 0 0 X X X X X GPO ports 7, 6, and 5 enabled 0 X X X X X GPO ports 7, 6, 5, and 4 enabled 0 0 X X X X X GPO ports 7, 6, 5, 4, and 3 enabled 0 X X X X X GPO ports 7, 6, 5, 4, 3, and 2 enabled X X X X X X Power-up default setting 0

11 INT INT INT INT INT INT INT REGISTER DESCRIPTION REGISTER DATA D7 D6 D5 D4 D3 D2 D D0 FIFO-BASED INT TIME-BASED INT INT used as GPO FIFO based INT disabled Not all zero INT asserts every debounce cycles INT asserts every 2 debounce cycles INT asserts every 29 debounce INT asserts every 30 debounce INT asserts every 3 debounce Time based INT disabled Not all zero INT asserts when FIFO has 2 key events INT asserts when FIFO has 4 key events INT asserts when FIFO has 6 key events INT asserts when FIFO has 6 key events Both time base and FIFO based interrupts active Not all zero Not all zero Power-up default setting INT

12 REGISTER BIT DESCRIPTION VALUE FUNCTION DEFAULT VALUE 0 Clear port 7 low D7 PORT 7 Control Set port 7 high (high impedance) 0 Clear port 6 low D6 PORT 6 Control Set port 6 high (high impedance) 0 Clear port 5 low D5 PORT 5 Control Set port 5 high (high impedance) 0 Clear port 4 low D4 PORT 4 Control Set port 4 high (high impedance) 0 Clear port 3 low D3 PORT 3 Control Set port 3 high (high impedance) 0 Clear port 2 low D2 PORT 2 Control Set port 2 high (high impedance) 0 Clear port INT low D INT Port Control Set port INT high (high impedance) D0 Reserved 0 0 REGISTER DESCRIPTION REGISTER DATA D7 D6 D5 D4 D3 D2 D D0 ENABLE AUTOREPEAT RATE AUTOREPEAT DELAY Autorepeat is disabled 0 X X X X X X X Autorepeat is enabled AUTOREPEAT RATE AUTOREPEAT DELAY Key-switch autorepeat delay is 8 debounce cycles X X X Key-switch autorepeat delay is 6 debounce cycles X X X Key-switch autorepeat delay is 24 debounce cycles X X X Key-switch autorepeat delay is 2 debounce cycles X X X 0 Key-switch autorepeat delay is 20 debounce cycles X X X 0 Key-switch autorepeat delay is 28 debounce cycles X X X Key-switch autorepeat frequency is 4 debounce cycles X X X X Key-switch autorepeat frequency is 8 debounce cycles 0 0 X X X X Key-switch autorepeat frequency is 2 debounce cycles 0 0 X X X X Key switch autorepeat frequency is 32 debounce cycles X X X X Power-up default setting

13 Ω W REGISTER REGISTER DATA AUTOSLEEP REGISTER RESERVED AUTOSHUTDOWN TIME D7 D6 D5 D4 D3 D2 D D0 No Autosleep Autosleep for (ms) Power-up default settings

14 t LOW t SU, DAT tsu, STA t HD, STA t HD, DAT tsu, STO t R t F t F, TX t BUF t HIGH t HD, STA t R t F START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION S START CONDITION P STOP CONDITION DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED 4

15 W W PIN AD0 DEVICE ADDRESS A7 A6 A5 A4 A3 A2 A A0 GND R/W V CC R/W R/W 0 0 R/W START CONDITION CLOCK PULSE FOR ACKNOWLEDGE BY TRANSMITTER BY RECEIVER S 0 A3 A2 A MSB LSB R/W ACK 5

16 COMMAND BYTE IS STORED ON RECEIPT OF ACKNOWLEDGE CONDITION D7 D6 D5 D4 D3 D2 D D0 ACKNOWLEDGE FROM MAX7359 S SLAVE ADDRESS 0 A COMMAND BYTE A P R/W ACKNOWLEDGE FROM MAX7359 ACKNOWLEDGE FROM MAX7359 ACKNOWLEDGE FROM MAX7359 ACKNOWLEDGE FROM MAX7359 D7 D6 D5 D4 D3 D2 D D0 D7 D6 D5 D4 D3 D2 D D0 S SLAVE ADDRESS 0 A COMMAND BYTE A DATA BYTE A P R/W BYTE AUTOINCREMENT COMMAND BYTE ADDRESS W REGISTER FUNCTION ADDRESS CODE (hex) Keys FIFO 0x00 0x00 Autoshutdown 0x06 0x00 All other 0x0 thru 0x05 Addr + 0x0 AUTOINCREMENT ADDRESS (hex) 6

17 ACKNOWLEDGE FROM MAX7359 S SLAVE ADDRESS 0 A COMMAND BYTE A DATA BYTE A P R/W ACKNOWLEDGE FROM MAX7359 ACKNOWLEDGE FROM MAX7359 D7 D6 D5 D4 D3 D2 D D0 D7 D6 D5 D4 D3 D2 D D0 N BYTES AUTOINCREMENT COMMAND BYTE ADDRESS μ Ω 7

18 REGULAR KEY-PRESS EVENT GHOST-KEY EVENT EXAMPLES OF VALID THREE-KEY COMBINATIONS KEY-SWITCH MATRIX KEY-SWITCH MATRIX KEY-SWITCH MATRIX +33V +33V +8V COL5/PORT5 V CC COL4/PORT4 KEY 0 KEY 8 KEY 6 KEY 24 KEY 32 KEY 40 COL3/PORT3 COL6/PORT6 COL2/PORT2 COL KEY KEY 9 KEY 7 KEY 25 KEY 33 KEY 4 COL7/PORT7 COL0 KEY 2 KEY 0 KEY 8 KEY 26 KEY 34 KEY 42 AD0 MAX7359 ROW0 +5V ROW ROW2 KEY 3 KEY KEY 9 KEY 27 KEY 35 KEY 43 V CC μc INT GND INT GND ROW3 ROW4 ROW5 ROW6 ROW7 KEY 4 KEY 5 KEY 6 KEY 2 KEY 3 KEY 4 KEY 20 KEY 2 KEY 22 KEY 28 KEY 29 KEY 30 KEY 36 KEY 37 KEY 38 KEY 44 KEY 45 KEY 46 KEY 7 KEY 5 KEY 23 KEY 3 KEY 39 KEY 47 8

19 TOP VIEW (BUMPS ON BOTTOM) A B C D + ROW2 ROW COL7/ PORT7 V CC 2 ROW3 ROW0 NC MAX COL3/ PORT3 COL4/ PORT4 NC GND 4 ROW4 ROW7 COL5/ PORT5 IC 5 ROW5 ROW6 COL6/ PORT6 COL2/ PORT2 PROCESS: BiCMOS chinamaxim-iccom/packages 24 TQFN-EP T243A WLP W252F INT AD0 COL0 COL E WLP (23mm 23mm) 9

20 0 7/07 4/ / /09, 2, 3, 9 4 6/0 2, 3 20 Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products

INT RST TEMP RANGE PIN- PACKAGE TOP MARK PKG CODE PART. -40 C to +125 C -40 C to +125 C 16 QSOP E16-4 MAX7323AEE+ 16 TQFN-EP* 3mm x 3mm MAX7323ATE+

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