PI2EQX6804-ANJE EvalBoard Rev.A User Guide
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1 PIEQX0-ANJE EvalBoard Rev.A User Guide Introduction Pericom Semiconductor s PIEQX0-A is a low power, SAS, SATA, XAUI signal Re-Driver. The device provides programmable equalization, amplification, and emphasis by using elect bits, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PIEQX0-A supports eight 00-Ohm Differential CML data I/O s between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user s platform. The integrated equalization circuitry provides fl edibility with signal integrity of the signal before the re-driver, whereas the integrated emphasis circuitry provides flexibility with signal integrity of the signal after the redriver. In addition to providing signal re-conditioning, Pericom s PIEQX0-A also provides power management Stand-by mode operated by a Power Down pin. This design guide describes how to use PIEQX0-A SATA ReDriver in the demo board. Figure shows top view and bottom view of PIEQX0-A demo board. This demo board is just for SAS application using SAS connector. Figurea Top View of PIEQX0-A demo board Figureb Bottom View of PIEQX0-A demo board Page of AN 0/0/0 //00
2 Board Operation Logical Block Diagram Figure shows the logical block diagram of PIEQX0-A. Figure. Logical Block Diagram of PIEQX0-A Page of AN 0/0/0 //00
3 Board Circuit ) Power Supply On the demo board, the power supply is from one miniusb connector (J) by +V power transforming to +.V for PIEQX0-A. Figure shows the power circuit. J VBUS D- D+ ID Mini USB.0 Ty pe B Female D D LED B00LW + EC 00uF C +.0V C.u U VIN EN LM L SW.uH FB R 0k C pf C 0u 00mA R C 0K L BL00LL0 C +V 00u C + R 0 R0 00K C NP Figure. Power Circuit for PIEQX0-A demo board Figure shows the location for J. J location Figure. J location on PIEQX0-A demo board ) Configuration Control PIEQX0-A provides two ways configuration control depending on the state of the MODE input (PIN G). MODE determines whether IC configuration status is from the input pins or via IC control, when MODE is set high, the configuration input pins set the configuration operating state as stored in configuration registers, changes to these control registers are disabled and initial condition is protected from any changes to insuring a known operating state. When MODE pin is low, reprogramming of these control registers via IC is allowed. NOTE that the MODE pin is not latched and is always active to enable or disable IC acces. During initial power-on, the value at the configuration input pins: LB#, PD#, DE_ [A...B], SEL [0...] _A, D [0 ] _A, S0_A, S_A, SEL [0...] _B, D [0 ] _B, S0_B, S_B, will be latched to the configuration registers as initial startup states. All these pins have internal 00K pull-up resistor. Figure shows the switch and location of these configuration control pins on the demo board. Page of AN 0/0/0 //00
4 SW CHS-0TA 0 A A A0 S_A S0_A S_B S0_B MODE SW CHS-0TA 0 SEL_B SEL_B SEL0_B SEL_A SEL_A SEL0_A LB# PD# SW CHS-0TA 0 PRE_A PRE_B D_A D_A D0_A D_B D_B D0_B SW location Figurea Control Pin connecton with SW, SW, SW SW location SW location Figureb SW, SW and SW location on PIEQX0-A demo board Figure shows input equalizer selection table for Channel A and B. Figure Input equalizer selection table for Channel A and B Page of AN 0/0/0 //00
5 Figure shows output configuration table for Channel A and B. Figure Output Configuration Table for Channel A and B For detail IC configuration function please refer to Page- on the datasheet. There is one connector-jp as Figure on the demo board for IC connection. JP location SCL SDA Figure JP location for IC connection Also there are three LED lights for power supply, signal detect output for Channel A and B. D: signal detect output for Channel A, not available D: signal detect output for Channel B, not available D: Power supply Page of AN 0/0/0 //00
6 Appendix A: PCB Schematic JP D D D D D D SAS CONN A A A B B B A A A B B B A A A B B B A0 A A B0 B B A B C 0n C 0n C 0n C 0n C 0n C 0n C 0n C 0n C 0n C 0n C 0n C0 0n C 0n C 0n C 0n C 0n C B B C G G K K C B B0 C0 G G K K A A D D J H H J A RX0+ RX0- B TX0+ TX0- A RX+ RX- B TX+ TX- A RX+ RX- B TX+ TX- A0 RX+ RX- B0 TX+ TX- A B UB B0TX+ B0TX- BTX+ BTX- BTX+ BTX- BTX+ BTX- PIEQX0@LFBGA00P B0RX+ B0RX- BRX+ BRX- BRX+ BRX- BRX+ BRX- A A D D J H H0 J0 C 0n C 0n C 0n C 0n C0 0n C 0n C 0n C 0n C 0n C 0n C 0n C 0n C 0n C0 0n C 0n C 0n A A A B B B A A A B B B A A A B B B A0 A A B0 B B A B JP UA A0RX+ A0RX- ARX+ ARX- ARX+ ARX- ARX+ ARX- PIEQX0@LFBGA00P A0TX+ A0TX- ATX+ ATX- ATX+ ATX- ATX+ ATX- A RX0+ RX0- B TX0+ TX0- A RX+ RX- B TX+ TX- A RX+ RX- B TX+ TX- A0 RX+ RX- B0 TX+ TX- A B D D D D D D D D D D SAS CONN Page of AN 0/0/0 //00
7 Appendix A: PCB Schematic (cont d) 00mA +V + 0 R 00u C SW CHS-0TA JP CONN_P 0 0 R.K.K R R C C C C C u C SEL_A SEL_A SEL0_A +V PRE_A PRE_B D_A D_A D0_A D_B D_B D0_B R 0 R 0 Q MMBT0 +V D LED Q MMBT0 D LED PD# LB# SW CHS-0TA SW CHS-0TA U VIN EN LM SW FB +V 0 A A A0 S_A S0_A S_B S0_B MODE SEL_B SEL_B SEL0_B SEL_A SEL_A SEL0_A LB# PD# 0 PRE_A PRE_B D_A D_A D0_A D_B D_B D0_B S_B S0_B MODE SEL_B SEL_B SEL0_B K F H E E F F G F F F0 E E E UD PIEQX0@LFBGA00P A A A0 S_A S0_A S_B S0_B Mode SEL_B SEL_B SEL0_B SEL_A SEL_A SEL0_A A SCL SDA A PRE_A B PRE_B H D_A D D_A E D0_A E D_B K D_B J D0_B G SIG_A E SIG_B F PD# LB# C F Q SK0@SOT- Q SK0@SOT- B B B B C C C C D H H H H J J J J UC +V VDD A VDD A A VDD A A0 VDD A0 D VDD D D VDD D D VDD D VDD D0 VDD B G VDD G G VDD G G VDD G G0 VDD G0 K VDD K K VDD K K VDD K K0 VDD K0 PIEQX0@LFBGA00P C E E0 F F J 0K 0K R R C C S_A S0_A +V +V R 0K 00n K C0 R C0 A A A0 J D VBUS D- D+ ID D + EC 00uF C Mini USB.0 Ty pe B Female LED R 0 C.u L.uH R 0k C pf R0 00K C NP C 0u C R 0K L BL00LL0 C B00LW +.0V Page of AN 0/0/0 //00
8 History Version.0 Original Version Aug., 00 Page of AN 0/0/0 //00
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