7.5V~~12V DC INPUT 0.925V*(1+26.1/10.2)=3.3V 7.5V~~12V DC ADAPTER 0.925V*(1+44.2/10)=5V VCC_IN VCC_IN 5VD 5VD D5 1N4148 C102 10NF 3.

Transcription

1 V_IN N.V~~V INPUT J JK SW R0 OM OM [0R,0] 0 N NO N NO SW,PT,IP SW/PSW0S V_IN + 0uF/V 0.uF nF 00uF R0 00K U EN VIN OMP R.K/% S SW EP 9 SS F UF 0 0NF + RT9 FR9 L 0UH/IP R09.K % R0 0.K %.V +0 0uf V.V_J R9.V_L.V~~V PTER 0.9V*(+./0.)=.V V_IN R 00K/NI V U V R0 /NI EN VIN OMP SW RT9/NI L 0UH/IP/I + 00uF/NI + 0nF/NI + 0nF/NI S EP 9 SS F R.K %/NI + 0uf V/NI R.K/% + 0.UF/NI R 0K %/NI 0.9V*(+./0)=V

2 .V_L SM LE.V_L GPIO SEU_LE SEU_LE LE SELE R9 0 SEURITY LE.V WLN_LE WLN_LE WLE Wireless T LE GPIO0 RST_P RST_P Software Reset/ Factory efault GPIO9 SEU_LE R9.V_L LINK LINK /NI R9 0 WNLE WN Port LE LINK LINK LINK R.K/NI R9 0 LE R90.K S SW TT-SPST-R LE LINK LINK LINK R0 0 R0 0 R0 0 LNLE LNLE LNLE0 LE LE 9 LE 0 LNLE R99 0 LN Port LE LN Port LE LN Port LE LN0 Port LE GPIO WPS_LE WPS_LE.V_L R0.K/NI LE WPSLE+.V_L R0 0 LE.V_L R0 0 POWER LE LE

3 LN WN(Port 0) M- RXIP0 M- M+ M0- RXIM TXOP M- TP M- M+ RXIP RXIP M+ M- TXOM TXOM M0- M- M+ TXOM TXOM TXOP0 M- M- M- TP M0+ M- M+ RXIM TXOP M- M+ M+ M0- TXOM0 M- M+ M- M+ M+ M+ M- RXIM M0- M0+ M- M- RXIP RXIP RXIM0 M0+ TXOP TXOP RXIM M+ M0+ M+ M+ M+ M+ TP SO_.V TXOM RXIM RXIP TXOP TXOM TXOP RXIP RXIM RXIP RXIM TXOP TXOM0 TXOP0 RXIP0 RXIM0 TXOM TXOP TXOM RXIM RXIP T/R R/T X T/R R/T U HN0G RJ-* U RJ-X-No-Shield N N 0pF.uF/NI 0pF U9 RJ-XP 0pF 0pF RX TX X U0 hng 0 R /S T/R R/T X T/R R/T U HN0G pF

4 SPI_LK WLN_LE LINK LINK LINK LINK URT_TX TX SPI_LK WLN_LE LINK LINK LINK LINK URT_TX TX RT0 oot Up Strapping Pin Name SPI_LK WLN_LE_N EPHY_LE_N escription XTL_FREQ _HI ig Endian RM_FROM _EE Value=0 0MHz Little Endian from boot strapping Value= 0MHz ig Endian from EEPROM {EPHY_LE_N, EPHT_LE_N} RM_SIZE INI/P(SR) 0: M/M : M/M.V_J.V_L.V_L.V_L.V_L.V_J R.K/NI R.K.V_L R.K/NI R9.K ohm.v_l R0.K/NI R.K ohm.v_l R.K R.K/NI.V_L R.K/NI SPI_LK WLN_LE LINK LINK LINK SPI_LK WLN_LE_N EPHY_LE_N EPHY_LE_N EPHY_LE_N.V_L.V_L.V_J.V_J.V.V_L R.K/NI R.K ohm.v_l R.K/NI R.K ohm.v_j R.K/NI R.K.V_J R.K/NI.V R.K R9.K/NI LINK URT_TX TX EPHY_LE_N EPHY_LE0_N TX TX {EPHY_LE_N, EPHT_LE0_N} {, TX, TX} PU_LK _SEL HIP_ MOE[:0] : M/M : M/M PU clock select 0: 0MHz : Reserved : 0MHz : 00MHz vector to set chip function/test/debug modes 0 : Normal mode(boot fromspi serial flash) : ini-us mode : Reserved : Reserved : Reserved : ini-phy mode : SN mode : TEST/EUG mode R0.K ohm R.K

5 .V_S SRM_S0N MT MT MT T SRM_LK_P SRM_SN RFU MT SRM_ MT MT MT SRM_MQM MT0.V_S SRM_RSN MT MT MT SRM_0 MT MT0 SRM_WEN MT MT9 MT[0:] MT SRM_MQM[0:] MR MR MR0 MR MR MR MR MR MR MR9 MR0 MR MR[0:] MR SRM_MQM0 SRM_MKE MT[0:] [] MR[0:] [] SRM_MQM[0:] [].V_S.V_S.V_S.V_S.V SRM_LK_P SRM_S0N SRM_WEN SRM_RSN SRM_SN SRM_0 SRM_ SRM_MKE 0.uF SRM TSOP P U SRM MX KE LK S 9 WE RS S V V V VSS VSS VSS QML QMH 9 Q0 Q Q Q Q Q 0 Q Q Q Q9 Q0 Q Q Q 0 Q Q VQ VQ 9 VQ VQ 9 VSSQ VSSQ VSSQ VSSQ N 0 L0 /S 0.uF R 0K 0.uF 0.uF 0.uF R9.K 9.uF 0 0.uF R0 /NI 0pF/NI 0.uF 0.uF

6 SPI_S0 WP_SPI HOL_SPI SPI_LK SPI_MISO SPI_LK.V_J.V_J SPI_MISO SPI_S0 SPI_LK U MXL0MI /S O /WP V /HOL LK I R.K 0.uF SR.K

7 lose to U S_OMP G _V SO_.V SO_OMP SO_F _V _V _V SO_.V G MOS_S LOSEL.V SO_.V _V _V.V SO_.V SO_.V _V.V R.9K % 0.uF pf.uf.uf 0.uF L /S + 9 0uF + 00uF U PM0 G S G S R /S uf L.uH/VL0.uF.nF 0.uF 0.nF.uF 0.uF R K % L9 /S R.K/NI UG RT0SF UGTE H LGTE J F H OMP G _V H _V J EXT_LO_P H VOUT_P G LO_V G LOSEL G R K % R ohm %

8 UF.V 0 F G SO_IO_V_ SO_IO_V SO_IO_V SO_O_V F9 SO_O_V G9 SO_O_V H SO_O_V H9 SO_O_V J SO_.V 0.uF 9 SO_.V PLL_V_V 0 SO_.V 0 SO_.V PLL_V_V SO_.V SO_.V 0.uF 0.uF 0.uF 9 E E E E E E E9 F F F F F F F G G G H H H J J J J9 K9 K0 L0 M0 M M N0 N N P0 P RT0SF 0.uF.uF

9 .V lose to RT0 UE RXIM R 9.9 % RX TXOM R 9.9 % TX 9 0.uF 0 0.uF K K K K EPHY_V EPHY_V EPHY_V EPHY_V EPHY_TXN_p EPHY_TXP_p EPHY_RXN_p EPHY_RXP_p M9 L9 N9 P9 TXOM TXOP RXIM RXIP TXOM TXOP RXIM RXIP RXIP R 9.9%.nF TXOP R 9.9%.nF RXIM0 R 9.9 % RX0 EPHY_TXN_p EPHY_TXP_p EPHY_RXN_p EPHY_RXP_p N P M L TXOM TXOP RXIM RXIP TXOM TXOP RXIM RXIP TXOM R 9.9 % TX RXIM R 9.9 % RX RXIP0 R 9.9 %.nf.nf.nf EPHY_TXN_p EPHY_TXP_p EPHY_RXN_p EPHY_RXP_p M L N P TXOM TXOP RXIM RXIP TXOM TXOP RXIM RXIP TXOP R 9.9% RXIP R9 9.9% TXOM0 TXOP0 R0 9.9 % R 9.9% TX0.nF RXIM R 9.9 % RX TXOM R 9.9 % TX EPHY_TXN_p EPHY_TXP_p EPHY_RXN_p EPHY_RXP_p N P L M TXOM TXOP RXIM RXIP TXOM TXOP RXIM RXIP RXIP R 9.9%.nF TXOP R 9.9%.nF lose to RT0 R 9.K % LINK LINK LINK LINK EPHT_REF_RES LINK LINK LINK LINK P M M L L K EPHY_REF_RES EPHY_LE_N EPHY_LE_N EPHY_LE_N EPHY_LE_N EPHY_LE0_N EPHY_TXN_p0 EPHY_TXP_p0 EPHY_RXN_p0 EPHY_RXP_p0 N P L M TXOM0 TXOP0 RXIM0 RXIP0 TXOM0 TXOP0 RXIM0 RXIP0 TXOM TXOP R 9.9 % R 9.9% TX.nF RXIM RXIP R9 9.9 % R0 9.9% RX.nF RT0SF PHY address ˇd0 -> Internal PHY for port 0 PHY address ˇd -> Internal PHY for port PHY address ˇd -> Internal PHY for port PHY address ˇd -> Internal PHY for port PHY address ˇd -> Internal PHY for port PHY address ˇd -> default for the external Port PHY address ˇd ~ ˇd are free for the external PHY.

10 U R.V SO_.V SO_.V N P UPHY0_V_V UPHY0_VL_V /NI 0.uF UPHY0_VRES UPHY0_PP UPHY0_PM V US+ US- V R.K % P P N UPHY0_VRES UPHY0_PP UPHY0_PM P US STK/NI FU V-PORT/NI V-PORT/NI U pf/ni RT0SF 保保保 /N U pf/ni.uf/ni

11 U SPI_MISO SPI_LK SPI_S0 SPI_MISO SPI_LK SPI_S0 SR SFLSH_LK M J N P L SPI_MISO SPI_LK SPI_S0 SPI_S RTS_N P TR_N N TX K _N J SR_N L TS_N K RIN M RX N TX SEU_LE PWR_LE WPS_LE RST_P TX SEU_LE WPS_LE RST_P TP URT_TX URT_TX.V IMP09S***/N.V R 0K R I_SLK I_S GPIO0 TX RX N P URT_RX R.K.V_J.V_J J HEER x.mm V U 0.uF/N RESET R 0uF PURST_N 0 PORST_N RT0SF JTG_TRST_N JTG_TI JTG_TO JTG_TMS JTG_TLK

12 MT MT MT0 MT MT MT MT MT MT0 MT MT MT9 MT MT MT MT MR MR MR MR0 MR MR MR MR MR9 MR MR MR0 MR SRM_WEN SRM_RSN SRM_S0N SRM_SN SRM_MQM0 SRM_MQM SRM_0 SRM_ SRM_MKE MR MR MR MR MR MR[0:] MR MR9 MR SRM_MQM0 MR MR SRM_MQM MR0 S_LK_P MR0 MR SRM_RSN SRM_0 SRM_S0N MT MT MT MT MT[0:] MT0 MT MT9 MT0 MT MT MT MT MT MT MT MT SRM_SN SRM_WEN SRM_ SRM_MKE SRM_LK_P MT[0:] [0] MR[0:] [0].V.V SRM_MKE SRM_WEN SRM_SN SRM_RSN SRM_S0N SRM_0 SRM_ SRM_LK_P SRM_MQM0 SRM_MQM R ohm 0 0pF/NI U RT0SF M M0 G MQM0 J0 MQM M M0 L M M MLK H MKE MRS_N L MS_N MWE_N MS0_N K M0 E0 M M M M E M F M E M G M0 E M9 E M F M F M G M F M G M H M H M H M K M J M J M J M K M0 L M9 J M K M L MS_N SRM_IO_V F0 SRM_IO_V G0 SRM_IO_V H0.uF

13 LORF_Out layout close U SO_.V_J R SO_.V SO_.V RF_V WL_LORF_OUT_V WL_LORF_IN_VX.V LO_In.uF 0pF 0pF 0pF 00pF uf R RF0_RF_V WL_RF0_IF_V WL_RF V WL_RF0_RF_V WL_G_V 9 G_RES_K 0.uF.V 9 0pF.V.V Input 0nF 9 WL_RF V WL_G_RES_K 0 00pF R K % layout close LOPLL_Out uf 00pF PLL_V WL_LOPLL_OUT_V WL_VO_VO_V WL_PLL_V WL_PLL_X WL_PLL_X 0 R K %/NI R K ohm OS_O U.x. XTL/.x./0MHz SO_.V SO_.V 9 WL V WL_PLL_V_P PLL_V_P pf L, layout close and F 0pF 9.uF 0pF 0.uF.V_J L P_V_0 E WL_RF0_P_VP WL_RF0_P_VN WL_RF0_G_INP WL_RF0_G_INN WL_RF0_P_OUTP WL_RF0_P_OUTN WLN_LE_N K WL_RF0_P_V E nf RF0_P_OUTP RF0_P_OUTN WLN_LE WLN_LE.V L RF0_P_V pf/ni RF0_G_INP RF0_G_INN 0pF 0pF.pF P0_OUT+ P0_OUT- L.nH.pF L.nH.pF L 0.pF.nH L.pF.nH RF0IN_G P0_OUT_ RFOUT_G0 9.pF/NI 0.pF/NI 0 NI NI RF0IN_G0 RT0SF.uF (NTENN) (RX) E G IO US-NT-R NTE.nH NTES 焊焊.pF NI ON RF0IN_G0_ RF0IN_G0 M M (NTENN) (RX) SM/UFLR M NI.pF (NTENN0) (TX0/RX0) ON0 NTE0 RFOUT_G0 SM/UFLR 0pF NI.nH 9.pF M