Revisions. Prototype Release J.H. 21 May 12

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1 Table of ontents Notes lock iagram MP MU in SKT MP MU Power, RST, LIN, N JTG & NEXUS M onnections M onnections Rev X escription Prototype Release Revisions Update from VT - hange shunt on J to pins - - hange shunt on J to pins - - hange shunts on J to wirejumpers from -,-,-,- - hange R, R, R, R, R0 and R to zero ohms. Update from VT - Remove R thru R,R0 & R and connect pin of,,,,, and to GN. - hange connection to J pin to M_PT and J pin to M_PT. - hange connection to J pin to be PT,pin to be PT0,pin to be P,and pin to be PT. - Update default shunt positions to match. - Update MU to the new library parts. ate May 0 Jul 0 Nov pproved J.H. J.H. J.H. X - rystal & OS ircuits, Series resistor options were replaced by Jumpers. (0-000) 0 Mar arbara - Q MFR-PN changed to PTTE. X - Y00 Prefered MFR-PN changed to XG00000PTVZ - SW MFR-PN changed to 0MSQE - R changed to two pin jumper JP. Mar Mar Mar 0 Release 0 pr Marilyn & arbara Marilyn & arbara X. R - K changed to.k(0-00). R - 0.K changed to.0k(0-0). R -.K changed to 0(0-0). R -.K changed to K(0-0). - PF changed to 0PF(0-). - 00PF changed to 0PF(0-). R0-00K changed to K(0-0). dded x HR (J) and 0K pullup resistor(r) on the S_FS to V_PRE.. dded pull down resistor R0-00K (0-) on S_IO. 0. S_IO net pulled up to S_VORE through R -0K(0-).. -UF changed to.uf(0-0). -UF changed to.uf(0-0). -.UF changed to.0uf(0-). dded pull down resistors 00K (R, R and R) on the nets S_IO, S_IO and S_IO respectively.. -0uF changed to uf(0-). J HRx repalced by R & R.K(0-0) & also marked as NP. Sep X. -(0-), J-xH(-) Q-(0-) added on V_PRE circuitry.. SW(0-0), R-.K(0-0) -0.uf(0-),R-0K (0-) added near to J0 onnector.. R0-.K(0-00)&R-.0K (0-0)connected to F_ORE,. IO_ F_ORE connected to J0-rd Pin Sep X X. J-xH(-) added across R to S_IO.. R0-.K(0-00) are connected to S_VORE,instead of F_VORE.. Pin of Q(0-)connected to GN.. Pin of Q(0-)connected to GN. Pin of J connected to Pin of Q. 00 Release. hanged default assigned net names to user defined net names(vpre_ and GTE_LS) Sep 0 Sep. Removed the pull up resistors on the Power S's select pin (U.) and replaced two pull down resistors (.K.K) by a single pull down resitor (.K ohm). 0 Release 0 Oct U, replaced - with -0 0 Mar K utomotive Product Group 0 William annon rive West ustin, TX - This document contains information proprietary to Freescale and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale. esigner: Jay Hartvigsen rawn by: Jay Hartvigsen pproved: arbara _ X IP lassification: FP: FIUO: PUI: _ rawing Title: MPP-S Title Page Size ocument Number Rev SH-: SPF- Tuesday, March 0, 0 ate: Sheet of

2 . Interrupted lines coded with the same letter or letter combinations are electrically connected.. evice type number is for reference only. The number varies with the manufacturer. Power & Ground Nets. Special signal usage: _ enotes - ctive-low Signal <> or [] enotes - Vectored Signals. Interpret diagram in accordance with merican National Standards Institute specifications, current revision, with the exception of logic block symbology. MOTHER OR SUPPLIE POWER.V_M_SR.V_M_SR.V.V V_M_SR V_M_LR V V From the M switching regulator - only used to provide power back to the M I/'O circuits From the M linear regulator - used for.v on the daughter card EXTERNLLY SUPPLIE POWER EXT_PWR V External power supplied through the barrel connector to the System asis hip (S) - M0 EXT_PWR_SW V EXT_PWR out of the power switch - used by the S to detect input power V EXT_PWR_SW after the reverse voltage protection diode.v LR.V External power into pin of the terminal block.v LR.V External power into pin of the terminal block V LR V External power into pin of the terminal block SYSTEM SIS HIP (S) POWER NETS V Power into the pre-regulator switching regulator in the S V_PRE.V Power out of the pre-regulator switching regulator in the S S_VORE.V Power out of the core switching regulator in the S S_VUX.V Power out of the VUX linear regulator in the S S_V.V Power out of the V linear regulator in the S VN V Power out of the N linear regulator in the S POWER TO THE MU V_LV_ORE.V Power to the core logic on the MU V_LV_EXT.V Power derived from V_HV_PMU and regulated by the MU through an external transistor V_LV_PLL.V Power to the pll circuit on the MU V_HV_PMU.V Power to the pmu circuit on the MU.V Power to the I/O circuits on the MU V_HV_OS0.V Power to the oscillator circuit on the MU V_HV_FL0.V Power to the flash memory circuit on the MU V_HV_V0/.V Power to the circuit on the MU V_HV_R0.V Reference voltage to the 0 circuit on the MU V_HV_R.V Reference voltage to the circuit on the MU GROUN NETS GN VSS_PLL VSS_OS VSS 0V 0V 0V 0V Filtered ground for the on chip PLL circuit Filtered ground for the on chip oscillator circuit Filtered ground for the on chip circuits IP lassification: FP: PUI: rawing Title: MPP-S Notes Size ocument Number Rev SH-: SPF- Tuesday, March 0, 0 ate: Sheet of

3 Sheet Sheet Sheet MPP MU in Socket 0 MHz XTL MHz rystal Oscillator SM for External lock Power Selector for V_LV_ORE External Power Jack External Power Switch & LE External Power Terminal lock Terminal lock Power LEs S Power Supply MPP MU M_RGM oot Selector Power Selector for V_LV_PLL Vcca/Vaux Voltage Sel Header Power Selector for V_HV_PMU Power Selector for S I/O & MU FU_F0, Header S Power LEs (V_PRE, V, Sheet Power Selector for V_HV_OS0 Power Selector for V_HV_FL0 Power Selector for V_HV_V0/ Power Selector for V_HV_R0 Power Selector for V_HV_R VSS_PLL, VSS_OS, VSS filters VUX, VN, VORE) S FS0 and FS LEs N Interface LIN Interface RESET & POR Push uttons & LEs SPI, N, & LIN Source Headers Nexus onnector JTG onnector Motherboard onnectors Sheets and IP lassification: FP: PUI: rawing Title: MPP-S lock iagram Size ocument Number Rev SH-: SPF- Tuesday, March 0, 0 ate: Sheet of

4 .V LR.V_M_SR.V LR.V_M_SR S_VORE.V LR.V_M_SR efault: - (Use SR on M) J HR_X S_VORE 0UF 0UF 0 0.0UF 0.0UF 0.0UF 0.0UF TP.V LR.V_M_SR efault: - (Use SR on M) J HR_X S_VUX V_HV_OS0 L0 VOS V_HV_OS0 0 0 OHM 0.UF 0.0UF TP.V LR.V_M_SR efault: - (Use SR on M) J HR_X S_VORE V_HV_FL0 V_HV_FL UF 0.0UF TP.V LR.V_M_SR efault: - (Use SR on M) J HR_X S_VUX VV L 0 OHM V_HV_V0/.0 UF V_HV_V0/ 0.0UF 0.0UF TP efault: - (Use SR on M) J V_HV_PMU V_HV_PMU TP VSS_OS VSS_OS VSS VSS VSS HR_X 0UF 0UF 0.UF V_M_LR V LR V_M_LR V LR.V_M_SR.V LR.V_M_SR.V LR efault: - (Use SR on M) J TRL V_LV_EXT V_LV_ORE R 0 VI 0.0UF NP V_LV_ORE TP NJT Q0 V_LV_PLL L0 V_LV_PLL 0 OHM 0.0UF TP VSS_PLL 0 J0 0 HR_X efault: - (Use SR on M) S_V VR0 S_V TP J V_HV_R0 V_HV_R L L V_HV_R0 VR V_HV_R OHM 0 OHM HR_X.0 UF 0.0UF 0.0UF.0 UF 0.0UF 0.0UF efault: - (Use SR on M) VSS VSS VSS VSS VSS VSS TP0 HR_X.UF.UF.UF.UF.UF.UF 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF pag{,,} pag{,,,} pag{,,,} PT[0..] PT[0..] PT[0..] PT0 PT PT PT PT PT PT PT PT PT PT0 PT PT PT PT PT PT0 PT PT PT PT PT PT PT PT PT PT0 PT PT PT PT PT U PPPFK0MLQ + SKT QFP TH 0/GPIO0/ETIMER_0_ET0/SPI_SK/REQ0 /GPIO/ETIMER_0_ET/SPI_SOUT/REQ /GPIO/ETIMER_0_ET/FLEXPWM_0_/M_RGM_S/SPI_SIN/REQ /GPIO/ETIMER_0_ET/SPI_S0/FLEXPWM_0_/M_RGM_S/REQ /GPIO/ETIMER ET0/SPI_S/ETIMER_0_ET/FLEXPWM /REQ/M_RGM_F /GPIO/SPI_S0/ETIMER ET/SPI0_S/REQ /GPIO/SPI_SK/ETIMER ET/REQ /GPIO/SPI_SOUT/ETIMER ET/REQ /GPIO/ETIMER ET/SPI_SIN/REQ /GPIO/SPI_S/ETIMER ET/FLEXPWM_0_/FLEXPWM_0_FULT0 0/GPIO0/SPI_S0/FLEXPWM_0_0/FLEXPWM_0_X/SIUL_REQ /GPIO/SPI_SK/FLEXPWM_0_0/FLEXPWM_0_/REQ0 /GPIO/SPI_SOUT/FLEXPWM_0_/FLEXPWM_0_/REQ /GPIO/FLEXPWM_0_/FLEXPWM_0_FULT0/SPI_SIN/REQ /GPIO/N_TX/ETIMER ET/REQ /GPIO/ETIMER ET/N0_RX/N_RX/REQ 0/GPIO/N0_TX/ETIMER ET/SSM_EUG0/REQ /GPIO/ETIMER ET/SSM_EUG/N0_RX/N_RX/REQ /GPIO/LIN0_TX/SSM_EUG/SIUL_REQ /GPIO/SSM_EUG/LIN0_RX /GPIO0/TO_MUX /GPIO/TI /GPIO/M_RGM_LK_OUT/SPI_S/REQ /GPI/0_N0/LIN0_RX /GPI/0_N/ETIMER_0_ET /GPI/0 N 0/GPI/0 N /GPI/0 N /GPI/0 N /GPI/_N0/LIN_RX /GPI0/_N/ETIMER_0_ET/REQ /GPI/_N/REQ0 V_LV_ V_LV_ V_LV_/V_LV_REGORE 0 V_LV_ V_LV_/V_LV_OR V_LV_/V_LV_OR V_LV_PLL V_HV_PMU/V_HV_PMU_UX V_HV_OS V_HV_FL V_HV_V 0 V_HV_RE0 V_HV_RE E0/GPI/_N/_N E/GPI/0_N E/GPI/0_N E/GPI/0_N E/GPI0/0_N E/GPI/0_N E/GPI/_N/_N E0/GPI/_N/_N E/GPI/_N/_N E/GPI/_N/_N E/GPIO/ETIMER_0_ET/SPI_S/SPI_S/SIUL_REQ E/GPIO/ETIMER ET/SPI_S/FLEXPWM /SIUL_REQ E/GPIO/SPI0_S/SIUL_REQ F0/GPIO0/FLEXPWM_0_/ETIMER_0_ET/SIUL_REQ F/GPIO/SPI0_S F/GPIO/NP_WRPPER_MO F/GPIO/NP_WRPPER_MO F/GPIO/NP_WRPPER_MO F/GPIO/NP_WRPPER_MKO F/GPIO/NP_WRPPER_MSEO 0 F/GPIO/NP_WRPPER_MSEO0 F0/GPIO0/NP_WRPPER_EVTO F/GPIO/NP_WRPPER_EVTI_IN F/GPIO/ETIMER ET/FLEXPWM /SIUL_REQ0 0 F/GPIO/ETIMER ET/FLEXPWM /SIUL_REQ F/GPIO/LIN_TX/N_TX F/GPIO/LIN_RX/N_RX PTE0 PTE PTE PTE PTE PTE PTE PTE0 PTE PTE PTE PTE PTE PTF0 PTF PTF PTF PTF PTF PTF PTF PTF0 PTF PTF PTF PTF PTF PTE[0..] PTF[0..] pag{,} pag{,,,} pag{,} PT[0..] pag{} TRL pag{} VPP_TEST efault: - (pull low) PT0 PT PT PT PT PT PT PT0 PT PT PT PT PT PT0 PT PT PT PT PT PT PT PT PT PT0 PT PT PT J HR TH X TRL VPP_TEST /GPI/_N /GPI/0_N /GPI/0_N /GPIO/SPI0_S0/FLEXPWM_0_X/SSM_EUG/REQ /GPIO/SPI0_SK/SSM_EUG/FLEXPWM_0_FULT/REQ /GPIO/SPI0_SOUT/FLEXPWM_0_/SSM_EUG/REQ /GPIO/FLEXPWM_0_/SSM_EUG/SPI0_SIN 0/GPIO/SPI_S/FLEXPWM_0_/FLEXPWM_0_FULT /GPIO/ETIMER_0_ET/SPI_S /GPIO/ETIMER_0_ET/SPI_S /GPIO/ETIMER ET/FLEXPWM 0/TU_0_EXT_IN/FLEXPWM_0_EXT_SYN /GPIO/ETIMER ET/TU_0_EXT_TGR/SPI_S/FLEXPWM 0 /GPIO/FLEXRY_FR TXEN/ETIMER ET0/FLEXPWM_0_/TU_0_EXT_IN/FLEXPWM_0_EXT_SYN 0/GPIO/FLEXRY_FR TX/ETIMER ET/FLEXPWM_0_ /GPIO/ETIMER ET/TU_0_EXT_TGR/FLEXRY_FR RX /GPIO0/ETIMER ET/FLEXPWM_0_X/FLEXRY_FR RX /GPIO/FLEXRY_FR TX/ETIMER ET/FLEXPWM_0_ /GPIO/FLEXRY_FR TXEN/ETIMER ET/FLEXPWM_0_ /GPIO/SPI0_S/FLEXPWM_0_FULT/SENT0_SENT_RX0 /GPIO/SPI0_S/FLEXPWM_0_X/FLEXPWM_0_FULT /GPIO/SWG_OUT/SPI_S/SPI0_S/SENT_SENT_RX0 /GPIO/SPI_S/ETIMER ET/SPI0_S/FLEXPWM_0_FULT /GPIO/FLEXPWM_0_X0/LIN_TX 0/GPIO/FLEXPWM_0_0/ETIMER_0_ET0 /GPIO/FLEXPWM_0_0/ETIMER_0_ET /GPIO0/FLEXPWM_0_X/SPI_S/LIN_RX /GPIO/FLEXPWM_0_/ETIMER_0_ET TRL VPP_TEST L00 OHM VSS_PLL VSS_LV_ 0 VSS_LV_/VSS_LV_PLL VSS_LV_ VSS_LV_/VSS_LV_REGORE VSS_LV_ VSS_LV_ VSS_LV_/VSS_LV_OR VSS_LV_/VSS_LV_OR VSS_PLL L00 OHM VSS_HV_IO_ VSS_HV_IO_ VSS_HV_IO_ VSS_HV_IO_ 0 L000 OHM VSS_OS VSS_HV_OS VSS_HV_V VSS_OS VSS_HV_RE0 VSS_HV_RE VSS VSS G/GPIO/FLEXPWM_0_X/SPI_S 0 G/GPIO/FLEXPWM_0_/ETIMER_0_ET 0 G/GPIO00/FLEXPWM_0_/ETIMER_0_ET 00 G/GPIO0/FLEXPWM_0_X/SPI_S G/GPIO0/FLEXPWM_0_ G/GPIO0/FLEXPWM_0_ G/GPIO0/FLEXRY_FR_G0/SPI0_S/REQ/FLEXPWM_0_FULT0 G/GPIO0/FLEXRY_FR_G/SPI_S/SIUL_REQ/FLEXPWM_0_FULT G0/GPIO0/FLEXRY_FR_G/SPI_S/FLEXPWM_0_FULT G/GPIO0/FLEXRY_FR_G/FLEXPWM_0_FULT J/GPIO/ETIMER ET/ETIMER ET/N_RX J/GPIO/ETIMER ET/NP_NEX_RY/TU EXT_IN HR X TH K_EN J efault: - (disable) J ON SM E/ V GN EXT_LK Y0 OUT MHz OS RESET EXT_POR 0 FU_F0 FU_F TMS TK JOMP MO0 NMI XTL XTL 0 EXTL EXTL R. R 0 JP NP JP EX NP X Y00 X NP JP 0MHz Providing EXternal clock Via SM,J JP : No Shunt (Removing Jumper wire between rystal & EXTL) JP : Shunt - (dding Jumper wire between SM & EXTL) JP : Shunt - (Terminating the MU EXTL trace to GN via.) JP : Shunt - (Terminating the MU XTL trace to GN) 0.UF To use the OS is similar to using the SM connector, but the jumper to the. ohm resistor is not used (JP-NP) R 0 R 0 R 0 JP NP JP PTG PTG PTG PTG PTG PTG PTG PTG PTG0 PTG PTJ PTJ PTG[..] pag{,} Note: To test with the Leopard chip remove the zero ohm resistors to the port J bus and EXT_POR_ and move them to the NP locations to connect to V_HV_PMU. V_HV_PMU R NP 0 R NP 0 R NP 0 PTJ[..] XTL EXTL pag{} pag{} pag{,} LPJ pag{} LPJ pag{} RESET_ pag{,,,} EXT_POR_ pag{,} LEXT_POR_ pag{} FU_F0 pag{,} FU_F pag{,} TMS pag{,} TK pag{,} JOMP pag{,} MO0 pag{,} NMI_ pag{,} X IP lassification: FP: FIUO: PUI: rawing Title: MPP-S MP MU in SKT Size ocument Number Rev SH-: SPF- Tuesday, March 0, 0 ate: Sheet of

5 efault: -, -, - (oot from Flash or Static) R R0 R 0.0K 0.0K 0.0K 0 0.UF 0.UF RGM_F RGM_S RGM_S V_HV_OS0 V_HV_PMU V_HV_FL0 V_HV_V0/ V_LV_PLL V_HV_R0 V_LV_ORE V_HV_R pag{,,} pag{,,,} pag{,,,} PT[0..] PT[0..] TP NP LK_OUT PT[0..] PT PT0 PT PT PT PT PT PT PT PT PT PT0 PT PT PT PT PT PT0 PT PT PT PT PT PT PT PT PT PT0 PT PT PT PT PT U NP PPPFKMLQ 0/GPIO0/ETIMER_0_ET0/SPI_SK/REQ0 /GPIO/ETIMER_0_ET/SPI_SOUT/REQ /GPIO/ETIMER_0_ET/FLEXPWM_0_/M_RGM_S/SPI_SIN/REQ /GPIO/ETIMER_0_ET/SPI_S0/FLEXPWM_0_/M_RGM_S/REQ /GPIO/ETIMER ET0/SPI_S/ETIMER_0_ET/FLEXPWM /REQ/M_RGM_F /GPIO/SPI_S0/ETIMER ET/SPI0_S/REQ /GPIO/SPI_SK/ETIMER ET/REQ /GPIO/SPI_SOUT/ETIMER ET/REQ /GPIO/ETIMER ET/SPI_SIN/REQ /GPIO/SPI_S/ETIMER ET/FLEXPWM_0_/FLEXPWM_0_FULT0 0/GPIO0/SPI_S0/FLEXPWM_0_0/FLEXPWM_0_X/SIUL_REQ /GPIO/SPI_SK/FLEXPWM_0_0/FLEXPWM_0_/REQ0 /GPIO/SPI_SOUT/FLEXPWM_0_/FLEXPWM_0_/REQ /GPIO/FLEXPWM_0_/FLEXPWM_0_FULT0/SPI_SIN/REQ /GPIO/N_TX/ETIMER ET/REQ /GPIO/ETIMER ET/N0_RX/N_RX/REQ 0/GPIO/N0_TX/ETIMER ET/SSM_EUG0/REQ /GPIO/ETIMER ET/SSM_EUG/N0_RX/N_RX/REQ /GPIO/LIN0_TX/SSM_EUG/SIUL_REQ /GPIO/SSM_EUG/LIN0_RX /GPIO0/TO_MUX /GPIO/TI /GPIO/M_RGM_LK_OUT/SPI_S/REQ /GPI/0_N0/LIN0_RX /GPI/0_N/ETIMER_0_ET /GPI/0 N 0/GPI/0 N /GPI/0 N /GPI/0 N /GPI/_N0/LIN_RX /GPI0/_N/ETIMER_0_ET/REQ /GPI/_N/REQ0 V_LV_ V_LV_ V_LV_/V_LV_REGORE 0 V_LV_ V_LV_/V_LV_OR V_LV_/V_LV_OR V_LV_PLL V_HV_PMU/V_HV_PMU_UX V_HV_OS V_HV_FL V_HV_V 0 V_HV_RE0 V_HV_RE F0/GPIO0/FLEXPWM_0_/ETIMER_0_ET/SIUL_REQ F/GPIO/SPI0_S F/GPIO/NP_WRPPER_MO F/GPIO/NP_WRPPER_MO F/GPIO/NP_WRPPER_MO F/GPIO/NP_WRPPER_MKO F/GPIO/NP_WRPPER_MSEO 0 F/GPIO/NP_WRPPER_MSEO0 F0/GPIO0/NP_WRPPER_EVTO F/GPIO/NP_WRPPER_EVTI_IN F/GPIO/ETIMER ET/FLEXPWM /SIUL_REQ0 0 F/GPIO/ETIMER ET/FLEXPWM /SIUL_REQ F/GPIO/LIN_TX/N_TX F/GPIO/LIN_RX/N_RX PTE0 PTE PTE PTE PTE PTE PTE PTE0 PTE PTE PTE PTE PTE PTF0 PTF PTF PTF PTF PTF PTF PTF PTF0 PTF PTF PTF PTF PTF PTE[0..] PTF[0..] pag{,} pag{,,,} pag{,} PT[0..] pag{} TRL pag{} VPP_TEST PT0 PT PT PT PT PT PT PT0 PT PT PT PT PT PT0 PT PT PT PT PT PT PT PT PT PT0 PT PT PT TRL VPP_TEST /GPI/_N /GPI/0_N /GPI/0_N /GPIO/SPI0_S0/FLEXPWM_0_X/SSM_EUG/REQ /GPIO/SPI0_SK/SSM_EUG/FLEXPWM_0_FULT/REQ /GPIO/SPI0_SOUT/FLEXPWM_0_/SSM_EUG/REQ /GPIO/FLEXPWM_0_/SSM_EUG/SPI0_SIN 0/GPIO/SPI_S/FLEXPWM_0_/FLEXPWM_0_FULT /GPIO/ETIMER_0_ET/SPI_S /GPIO/ETIMER_0_ET/SPI_S /GPIO/ETIMER ET/FLEXPWM 0/TU_0_EXT_IN/FLEXPWM_0_EXT_SYN /GPIO/ETIMER ET/TU_0_EXT_TGR/SPI_S/FLEXPWM 0 /GPIO/FLEXRY_FR TXEN/ETIMER ET0/FLEXPWM_0_/TU_0_EXT_IN/FLEXPWM_0_EXT_SYN 0/GPIO/FLEXRY_FR TX/ETIMER ET/FLEXPWM_0_ /GPIO/ETIMER ET/TU_0_EXT_TGR/FLEXRY_FR RX /GPIO0/ETIMER ET/FLEXPWM_0_X/FLEXRY_FR RX /GPIO/FLEXRY_FR TX/ETIMER ET/FLEXPWM_0_ /GPIO/FLEXRY_FR TXEN/ETIMER ET/FLEXPWM_0_ /GPIO/SPI0_S/FLEXPWM_0_FULT/SENT0_SENT_RX0 /GPIO/SPI0_S/FLEXPWM_0_X/FLEXPWM_0_FULT /GPIO/SWG_OUT/SPI_S/SPI0_S/SENT_SENT_RX0 /GPIO/SPI_S/ETIMER ET/SPI0_S/FLEXPWM_0_FULT /GPIO/FLEXPWM_0_X0/LIN_TX 0/GPIO/FLEXPWM_0_0/ETIMER_0_ET0 /GPIO/FLEXPWM_0_0/ETIMER_0_ET /GPIO0/FLEXPWM_0_X/SPI_S/LIN_RX /GPIO/FLEXPWM_0_/ETIMER_0_ET TRL VSS_HV_IO_ VSS_HV_IO_ VSS_HV_IO_ VSS_HV_IO_ G/GPIO/FLEXPWM_0_X/SPI_S 0 G/GPIO/FLEXPWM_0_/ETIMER_0_ET 0 G/GPIO00/FLEXPWM_0_/ETIMER_0_ET 00 G/GPIO0/FLEXPWM_0_X/SPI_S G/GPIO0/FLEXPWM_0_ G/GPIO0/FLEXPWM_0_ G/GPIO0/FLEXRY_FR_G0/SPI0_S/REQ/FLEXPWM_0_FULT0 G/GPIO0/FLEXRY_FR_G/SPI_S/SIUL_REQ/FLEXPWM_0_FULT G0/GPIO0/FLEXRY_FR_G/SPI_S/FLEXPWM_0_FULT G/GPIO0/FLEXRY_FR_G/FLEXPWM_0_FULT J/GPIO/ETIMER ET/ETIMER ET/N_RX J/GPIO/ETIMER ET/NP_NEX_RY/TU EXT_IN RESET EXT_POR 0 FU_F0 FU_F TMS TK JOMP MO0 NMI XTL EXTL 0 XTL EXTL PTG PTG PTG PTG PTG PTG PTG PTG PTG0 PTG LPJ LPJ LEXT_POR_ PTG[..] pag{,} LPJ pag{} LPJ pag{} RESET_ pag{,,,} LEXT_POR_ pag{} FU_F0 pag{,} FU_F pag{,} TMS pag{,} TK pag{,} JOMP pag{,} MO0 pag{,} NMI_ pag{,} XTL pag{} EXTL pag{} 0 VSS_LV_ VSS_LV_/VSS_LV_PLL VSS_LV_ VSS_LV_/VSS_LV_REGORE VSS_LV_ VSS_LV_ VSS_LV_/VSS_LV_OR VSS_LV_/VSS_LV_OR 0 VSS_HV_OS VSS_HV_RE0 VSS_HV_RE VSS_HV_V 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF J HR_X U0 OE 0 OE OE OE V GN Y Y Y Y 0.UF LV E0/GPI/_N/_N E/GPI/0_N E/GPI/0_N E/GPI/0_N E/GPI0/0_N E/GPI/0_N E/GPI/_N/_N E0/GPI/_N/_N E/GPI/_N/_N E/GPI/_N/_N E/GPIO/ETIMER_0_ET/SPI_S/SPI_S/SIUL_REQ E/GPIO/ETIMER ET/SPI_S/FLEXPWM /SIUL_REQ E/GPIO/SPI0_S/SIUL_REQ 0 VPP_TEST VSS_PLL VSS_OS VSS IP lassification: FP: PUI: rawing Title: MPP-S MP MU Size ocument Number Rev SH-: SPF- Tuesday, March 0, 0 ate: Sheet of

6 V P ON PWR J ON T SW ON EXT_PWR OFF 0MSQE.V LR.V LR EXT_PWR_SW 0.UF 0.0UF V LR R.K uf MRS0TG TP + 0UF TP0 L uh.uf.uf S_VSENSE TP S_VUX 0 0.UF TP TP L MRS0TG V_PRE VSW VPRE_ V_PRE 0 0.UF uh MRS0TG Q UK- GTE_LS OOT_PRE J HR_X J -V_PRE-Mode - & - uck only Jumpers off uck or oost OOT_ORE UF 0uF VSW_ORE 0.UF TP L.uH MR0LSFTG TP F_ORE TP OMP_ORE S_VORE R.K R.0K X Y R K TP R 0 0PF 0PF S_VORE UF 0.UF TP TP TP TP S_VORE R0.K SW IO_ F_ORE R.0K J Female M N M R.K 0.UF R 0K pag{,} FU_F0 pag{,} FU_F N_SHL PF TP 0.UF J0 0 VN HR_X J HR X TH PF uf S_VORE NH NL R 0. R 00K VN efault: -, - (Terminate N) J.UF R 0.0K R0 00K R 00K V =.V & VUX =.V R 00K E R0 0. Q P- S_VUX_E S_VUX_ S_VUX R.K S_IO0 S_IO S_IO S_IO S_IO S_IO L ZJYSR-P S_SEL R_NH R_NL 0 0 U VSENSE VUX_E VUX_ VUX N_V SELET IO_0 IO_ IO_ IO_ IO_ IO_ NH NL LIN SW_PRE SW_PRE GN_OM OOT_PRE GN GTE_LS GN VPRE EP SW_ORE OOT_ORE F_ORE OMP_ORE VORE_SNS V_E V_ V VIO 0 MOSI MISO SLK S MUX_OUT INT RST FS0 EUG RX TX 0 RXL TXL M0LE S_VORE S_FS0_ S_FS TP S_V.UF 0.UF S_MOSI S_MISO S_SK S_S S_MUX_OUT S_INT_ S_RST_ J HR X TH efault: - shunt TP V_PRE R 0.0K R0 K R 0.0K S_VORE R 0.0K R 0.0K efault: -, -, -, - (onnect SPI to Mother oard. S_MUX_OUT doesn't connect to 0) 0 J HR X efault: No Shunts (RESET & NMI don't go to the S) J HR_X SPI0_SOUT SPI0_SIN SPI0_SK SPI0_S0 0 R 0.0K NMI_ RESET_ M_PT M_PT M_PT M_PT PT PT PT PT PT PT[0..] pag{,,,} PT[0..] pag{,,,} M_PT pag{} M_PT pag{} M_PT pag{} M_PT pag{} NMI_ pag{,} RESET_ pag{,,,} L 0 OHM NUP0L NL_T HR_X N_TERM NH_T N TERMINTION efault: -, -, -, - (N and LIN connect to the Mother oard) EXT_POR_ N0_TX N0_RX PT0 PT EXT_POR_ pag{,} LIN ON PLUG J efault: - (Master Mode) J HR X TH MSTER/SLVE R LIN_MS LIN.0K 00PF W Vsup MMST S_N_RX S_N_TX S_LIN_RX S_LIN_TX 0 J HR X LIN0_TX LIN0_RX S Power Indicators M_N_RX M_N_TX M_LIN_RX M_LIN_TX PT PT M_N_RX M_N_TX M_LIN_RX M_LIN_TX pag{} pag{} pag{} pag{} 0PF R 0.0K U UF RESET POR FS FS0 LE_YELLOW LE_YELLOW LE_YELLOW NP LE_YELLOW S_VORE LE_YELLOW VN 0 LE_YELLOW S_VUX LE_YELLOW S_V V_PRE LE_YELLOW LE_YELLOW LE_YELLOW SW P RST_SW R 0.0K RST_SW_ SNLV0 U00 SNLV0 R 0.0K U00 V GN SNLV0 LE_RST_R LE_POR_R LE_FS_R LE_FS0_R R 0 R 0 R.K NP R 0 LE_VORE_R External (Terminal lock) Power Indicators.V LR R0 0.V LR LE_VN_R LE_VUX_R LE_V_R R.K V LR R 0 R 0 LE_VPRE_R R.K LE R R.K SW P R 0.0K POR_SW R 0.0K POR_SW_ U00E 0 SNLV0 U00F SNLV0 U00 SNLV0 R 0.0K.V LR Q._GN_R R R 0 PTT LE_YELLOW LE_. R R 0 LE_YELLOW LE_. R R 0 LE_YELLOW LE_V R R.K X IP lassification: FP: FIUO: PUI: rawing Title: MPP-S Power, RST, LIN, N Size ocument Number Rev SH-: SPF- ate: Tuesday, March 0, 0 Sheet of

7 JTG & NEXUS PRLLEL TRE pag{,} PTJ[..] pag{,,,} PTF[0..] pag{,} MO0 NEXUS PRLLEL TRE pag{,,,} RESET_ pag{,,} PT[0..] pag{,,,} PT[0..] pag{,} TK pag{,} TMS pag{,} JOMP PT PT PT JOMP M_RGM_F RESET_ TO TK TMS TI P R0 0.0K NEXUS_EVTI_IN NP_NEX_RY_ NP_WRPPER_MO NP_WRPPER_MO NP_WRPPER_MO MO0 NP_WRPPER_EVTO_ NP_WRPPER_MKO NP_WRPPER_MSEO_ NP_WRPPER_MSEO0_ PTF PTJ PTF PTF PTF PTF0 PTF PTF PTF 0 G G G G G HR_X_F JTG J PT TI PT TO TK PTF NP_WRPPER_EVTI_IN EXT_POR_ RESET_ 0 TMS PTJ NP_NEX_RY_ JOMP ON_X pag{,} EXT_POR_ IP lassification: FP: PUI: rawing Title: MPP-S JTG & NEXUS Size ocument Number Rev SH-: SPF- Tuesday, March 0, 0 ate: Sheet of

8 Mother oard connections - pag{,,} PT[0..] PT[0..] pag{,,,} PT[0..] PT[0..] pag{,} PTE[0..] PTE[0..] pag{,} PTG[..] PTG[..] pag{,,,} PTF[0..].V_M_SR.V_M_SR V_M_LR.V_M_SR.V_M_SR J0.V_M_SR.V_M_SR.V_M_SR J0 PT0 PT RESET_ PT PT PT 0 PT PT 0 PT PT PT PT0 PT PT PT 0 0 PT0 PT PT M_PT 0 M_PT pag{} M_PT M_PT M_PT M_PT pag{} 0 pag{} M_PT M_N_RX M_N_TX M_PT pag{} pag{} M_N_RX M_N_TX pag{} PT0 PT PT 0 PT PT 0 N_TX PT 0 PTF LIN_RX 0 LIN_TX PTF PTG PTG FR_G_ PTG0 PTG FR_G_ 0 0 PTG PTG PTG 0 PTG PTG 0 PTG PT N_RX PTE PTE PTE PTE PTE 0 0 PTE PTE PTE0 PTE PTE PTE PTE 0 PTE SH SH SH SH SH SH SH SH SH SH SH SH SH SH SH SH SH SH0 SH SH SH SH SH SH SH SH0 SH SH SH SH SH SH ON X0 SKT ON X0 SKT pag{,,,} RESET_.V_M_SR _MIN V_M_SR V_M_SR _MIN.V_M_SR J HR TH X efault: - (Use.V for M transceivers) IP lassification: FP: PUI: rawing Title: MPP-S M onnections Size ocument Number Rev SH-: SPF- Tuesday, March 0, 0 ate: Sheet of

9 Mother oard connections - pag{,,,} pag{,} pag{,,,} pag{,} pag{,,,} PT[0..] PT[0..] PTF[0..] PTJ[..] PT[0..] PT[0..] PT[0..] PTF[0..] PTJ[..].V_M_SR.V_M_SR.V_M_SR.V_M_SR.V_M_SR.V_M_SR.V_M_SR V_M_SR.V_M_SR V_M_SR V_M_LR J00 J00 _MIN _MIN ON X0 SKT SH SH SH SH SH SH SH0 SH SH SH SH SH SH SH SH0 SH 0 0 PT PT PT PT PT PT0 PT R0 0 RPT 0 RPT R00 0 PT PT 0 PT PT PT 0 0 PT PT 0 0 PT PT PT PT PT PT M_LIN_TX M_LIN_RX pag{} M_LIN_TX M_LIN_RX pag{} PTF0 PTF PTF R0 0 RPTF RPTF R0 0 PTF PTF R0 0 RPTF 0 RPTF R0 0 PTF PTF R0 0 RPTF 0 RPTF R0 0 PTF PTF0 R 0 RPTF0 RPTF R0 0 PTF PTF PTF 0 0 PT FR TX PT PT FR TXEN 0 FR TX PT0 PT FR TXEN 0 FR RX PT PT FR RX PTJ 0 RPTJ R0 0 PTJ SH SH SH SH SH SH SH SH SH SH SH SH SH SH SH SH ON X0 SKT IP lassification: FP: PUI: rawing Title: MPP-S M onnections Size ocument Number Rev SH-: SPF- Tuesday, March 0, 0 ate: Sheet of