[AKD5384] AK5384 Evaluation Board Rev.A
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- Cathleen Baker
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1 HI KI [K8] K8 K8 valuation oar Rev. GNRL RIPTION K8 is an evaluation boar for the igital auio bit 9k ch / converter, K8. The K8 inclues the input circuit an also has a igital interface transmitter. urther, the K8 can achieve the interface with igital auio systems via optconnector. Orering guie K8 K8 valuation oar UNTION IT with optical output N connector for an external clock input V,V TV GN,GN Opt Out LIN/ RIN/ Input uffer K8 K0 (IT) Opt Out lock Generator P ata 0pin Heaer igure. K8 lock iagram * ircuit iagram an P layout are attache at the en of this manual. <KM000> 00/0
2 HI KI [K8] Operation sequence ) et up the power supplies lines. [V] (re) =..V : for V of K8 (typ..0v) [V] (re) =..V : for V of K8 (typ..0v) [TV] (orange) =.0.V : for TV of K8 (typ..0v) [V] (green) = V : for Opamp [ V] (blue) = V : for Opamp [V] (re) = V : for logic [GN] (black) = 0V : for analog groun [GN] (black) = 0V : for logic groun ach supply line shoul be istribute from the power supply unit. ) et up the evaluation moe, jumper pins an IP switches. (ee the followings.) ) Power on. The K8 an K0 shoul be reset once bringing W = L upon powerup. Note: When the K8 is TM moe, the K0 oes not support TM moe. o, PORT (IT) an PORT (IT) are not use. PORT (P) shoul be use. valuation moe () lave Moe () / evaluation using IT function of K0 PORT (IT) an PORT (IT) are use. IT generates auio biphase signal from receive ata an which is output through optical connector (TOTX). It is possible to connect KM s / converter evaluation boars on the igitalamplifier, which equips IR input. Nothing shoul be connecte to PORT (P). In case of using external clock through a N connector (J), select XT on JP8 (LK) an short JP (XT) an open JP0 (XT). JP JP JP JP8 JP0 IK LRK XT LK XT XTL XT () eeing all clocks from PORT (P) Uner the following setup, all external clocks (MLK, IK, LRK) can be fe through PORT (P). The / converte ata is output from TO/TO of PORT (P). lso, the / converte ata is output through optical connector (TOTX). JP JP JP JP8 JP0 IK LRK XT LK XT XTL XT <KM000> 00/0
3 HI KI [K8] () Master Moe () / evaluation using IT function of K0 PORT (IT) an PORT (IT) are use. IT generates auio biphase signal from receive ata an which is output through optical connector (TOTX). It is possible to connect KM s / converter evaluation boars on the igitalamplifier, which equips IR input. Nothing shoul be connecte to PORT (P). In case of using external clock through a N connector (J), select XT on JP8 (LK) an short JP (XT) an open JP0 (XT). JP IK JP LRK JP XT JP8 LK JP0 XT XTL XT Other jumper pins set up. JP (GN) : nalog groun an igital groun OPN : eparate. HORT : ommon. (The connector GN can be open.) <efault>. JP (V) : elect V for K8 V : upply from V connector <efault> RG : upply from regulator. V connector shoul be supplie V.. JP () : elect IK frequency : In case of MLK=fs/fs/8fs <efault> 8 : In case of MLK=8fs or IK frequency of TM8 moe : IK frequency of TM moe. JP (MLK) : upply MLK frequency for H00 : In case of MLK=fs : In case of MLK=fs <efault> 8/8 : In case of MLK=8fs/8fs. JP9 (LR) : elect LRK frequency : In case of MLK=fs/fs/8fs <efault> 8 : In case of MLK=8fs <KM000> 00/0
4 HI KI [K8] lock etting Moe fs MLK JP() JP(MLK) JP9(LR) fs =.08M 8k 8fs =.0M 8 8/8 8 fs =.09M 8fs =.M 8/8 fs = 8.9M k 8fs =.88M 8 8/8 8 fs =.8M 8fs =.M 8/8 fs =.89M Normal.k 8fs =.9M 8 8/8 8 fs =.9M 8fs =.888M 8/8 fs =.88M 8k 8fs = 8.M 8 8/8 8 fs =.M efault 8fs =.8M 8/8 88.k fs =.9M 8fs =.888M 8 8/8 8 9k fs =.M 8fs =.8M 8 8/8 8 8k fs =.09M TM k fs =.8M.k fs =.9M 8k fs =.M 8k fs =.08M 8 fs =.09M 8 k fs = 8.9M 8 fs =.8M 8 TM8.k fs =.89M 8 fs =.9M 8 8k fs =.88M 8 fs =.M 8 88.k fs =.9M 8 9k fs =.M 8 Table. lock etting <KM000> 00/0
5 HI KI [K8] IP witch set up [W] (MO): etting the evaluation moe for K8 an K0 ON is H, O is L. No. Name O ( L ) ON ( H ) efault I M justifie I ompatible O ( L ) TM O ( L ) ee Table TM0 O ( L ) M/ lave moe Master moe O ( L ) K MLK = fs MLK = fs ON ( H ) K ON ( H ) ee Table K0 O ( L ) Table. Moe etting TM TM0 Moe IK L L Normal 8 8fs efault L H TM fs H L N/ N/ H H TM8 8fs Table. Moe etting of K8 Moe K K0 MLK fs 0 L L fs 9k L H N/ N/ H L fs 8k efault H H 8fs 8k Table. MLK requency etting of K0 Note: K0 oes not support MLK=8fs. The function of the toggle W Uppersie is H an lowersie is L. [W] (PN): Resets the K8 an K0. Keep H uring normal operation. <KM000> 00/0
6 HI KI [K8] Input ircuit nalog signal is input to LIN/RIN pins via J J connectors. R, R8, R an R shoul be change epening on the output impeance of signal source. R R.k LIN R0 0 8 U NJM 8 OP_MP OP_MP R9 U NJM 8 OP_MP OP_MP R8 0k u R 0 J LIN LIN R 0 8 R R.k RIN R 0 0 U NJM 8 OP_MP OP_MP R U NJM 8 OP_MP OP_MP R 0k 9 u R8 0 J RIN RIN R9 0 R0 R.k LIN R 0 U NJM 8 OP_MP OP_MP R U NJM 8 OP_MP OP_MP R 0k u R 0 J LIN LIN R 0 R R8.k RIN R 0 U NJM 8 OP_MP OP_MP R0 U NJM 8 OP_MP OP_MP R9 0k u R 0 J RIN RIN R 0 igure. LIN/RIN Input circuits * KM assumes no responsibility for the trouble when using the circuit examples. <KM000> 00/0
7 HI KI [K8] MURMNT RULT [Measurement conition] Measurement unit : uio Precision, ystem Two ascae MLK : fs IK : fs fs : 8k, 9k it : bit Power upply : V = V = TV =.0V Interface : IT Temperature : Room [Measurement Results] Parameter Result Unit nalog Input haracteristics LIN / RIN LIN / RIN /(N) (fs=8k, ) (fs=9k, ) Range (fs=8k, 0, weighte) (fs=9k, 0) /N (fs=8k, weighte) (fs=9k) 00.8 / / / / / / / / / / / / 0. Interchannel Isolation 9. /. 0. /.0 <KM000> 00/0
8 HI KI [K8] [ Plot : fs=8k] KM K8 THN vs. Input Level V=V=TV=.0V, fs=8k, fin=k r igure. THN vs. Input Level KM K8 THN vs. Input requency V=V=TV=.0V, fs=8k, Input=.0r k k k 0k 0k igure. THN vs. Input requency <KM000> 00/0 8
9 HI KI [K8] KM 0 0 K8 Linearity V=V=TV=.0V, fs=8k, fin=k r igure. Linearity KM K8 requency Response V=V=TV=.0V, fs=8k, Input=.0r k k k 0k 0k igure. requency Response <KM000> 00/0 9
10 HI KI [K8] KM K8 rosstalk V=V=TV=.0V, fs=8k, Input=.0r k k k 0k 0k igure. rosstalk KM K8 T Plot V=V=TV=.0V, fs=8k, Input=.0r, fin=k k k k 0k 0k igure. T Plot <KM000> 00/0 0
11 HI KI [K8] KM K8 T Plot V=V=TV=.0V, fs=8k, Input=0r, fin=k k k k 0k 0k igure. T Plot KM K8 T Plot V=V=TV=.0V, fs=8k, fin=none k k k 0k 0k igure 8. T Plot <KM000> 00/0
12 HI KI [K8] [ Plot : fs=9k] KM K8 THN vs. Input Level V=V=TV=.0V, fs=9k, fin=k r igure 9. THN vs. Input Level KM K8 THN vs. Input requency V=V=TV=.0V, fs=9k, Input=.0r k k k 0k 0k 0k igure 0. THN vs. Input requency <KM000> 00/0
13 HI KI [K8] KM 0 0 K8 Linearity V=V=TV=.0V, fs=9k, fin=k r igure. Linearity KM K8 requency Response V=V=TV=.0V, fs=9k, Input=.0r k k k 0k 0k 0k igure. requency Response <KM000> 00/0
14 HI KI [K8] KM K8 rosstalk V=V=TV=.0V, fs=9k, Input=.0r k k k 0k 0k 0k igure. rosstalk KM K8 T Plot V=V=TV=.0V, fs=9k, Input=.0r, fin=k k k k 0k 0k 0k igure. T Plot <KM000> 00/0
15 HI KI [K8] KM K8 T Plot V=V=TV=.0V, fs=9k, Input=0r, fin=k k k k 0k 0k 0k igure. T Plot KM K8 T Plot V=V=TV=.0V, fs=9k, fin=none k k k 0k 0k 0k igure. T Plot <KM000> 00/0
16 HI KI [K8] Revision History ate (YY/MM/) Manual Revision oar Revision Reason ontents 0//0 KM irst eition 0/0/ KM000 ircuit hange onenser: apacitance Value hange:,8: open p IMPORTNT NOTI These proucts an their specifications are subject to change without notice. efore consiering any use or application, consult the sahi Kasei Microsystems o., Lt. (KM) sales office or authorize istributor concerning their current status. KM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information containe herein. ny export of these proucts, or evices or systems containing them, may require an export license or other official approval uner the law an regulations of the country of export pertaining to customs an tariffs, currency exchange, or strategic materials. KM proucts are neither intene nor authorize for use as critical components in any safety, life support, or other hazar relate evice or system, an KM assumes no responsibility relating to any such use, except with the express written consent of the Representative irector of KM. s use here: (a) hazar relate evice or system is one esigne or intene for life support or maintenance of safety or for applications in meicine, aerospace, nuclear energy, or other fiels, in which its failure to function or perform may reasonably be expecte to result in loss of life or in significant injury or amage to person or property. (b) critical component is one whose failure to function or perform may reasonably be expecte to result, whether irectly or inirectly, in the loss of the safety or effectiveness of the evice or system containing it, an which must therefore meet very high stanars of performance an reliability. It is the responsibility of the buyer or istributor of an KM prouct who istributes, isposes of, or otherwise places the prouct with a thir party to notify that party in avance of the above content an conitions, an the buyer or istributor agrees to assume any an all responsibility an liability for an hol KM harmless from any an all claims arising from the use of sai prouct in the absence of such notification. <KM000> 00/0
17 GN JP GN GN N U N T NJM8M0 OUT GN IN LIN LIN RIN RIN LIN.n V LIN RIN.n RIN LIN LIN RIN RIN LIN LIN RIN RIN 8.n.n 8 TT M/ M/ RG V JP L V (short) V u I TM TM u VOM V V I TM TM0 K PN V V 0 TV 9 TO R K PN L (short) TO L (short) TV u V u MLK R TMIN MLK TO IK R R TO JP IK 8_IK IK TT OV OV K8 LRK R JP LRK 8_LRK LRK Title K8 ize ocument Number Rev K8 ate: Monay, October, 00 heet of
18 V V OP_MP LIN LIN OP_MP OP_MP OP_MP OP_MP RIN RIN OP_MP OP_MP OP_MP OP_MP OP_MP OP_MP OP_MP RIN OP_MP LIN OP_MP RIN OP_MP OP_MP OP_MP OP_MP LIN Title ize ocument Number Rev ate: heet of INPUT K8 Monay, October, 00 Title ize ocument Number Rev ate: heet of INPUT K8 Monay, October, 00 Title ize ocument Number Rev ate: heet of INPUT K8 Monay, October, 00 for NJM for NJM u u R 0 R 0 R R 9 u 9 u R.k R.k J LIN J LIN 8 U NJM U NJM R R R0 R0 R 0 R 0 R 0k R 0k J LIN J LIN 8 U NJM U NJM J RIN J RIN R.k R.k R8.k R8.k R 0 R 0 u u 8 U NJM U NJM R 0 R R8 0k R8 0k 8 8 R 0 R R0 R0 u u R9 0k R9 0k R 0 R 0 8 U NJM U NJM R 0k R 0k J RIN J RIN 8 U NJM U NJM R.k R.k R0 0 R0 0 R 0 R 0 9 u 9 u 8 8 u u 8 U NJM U NJM R9 0 R9 0 R 0 R 0 R R R9 R9 R R 8 U NJM U NJM 8 U NJM U NJM R 0 R R R R8 0 R
19 V L HU9 H U H PN V 8 9 R 0k U H W PN I U8 G 9 G V V 0 0 GN 0 MLK U PN MLK TRN V V U 0 U 9 U 8 U I I V R k PORT IN V I GN IT TO Y 8 TI V TO IK LRK Y Y Y V TI TI TI TXN 0 V 9 V 8 R k PORT IN V I GN IT Y Y 8 V V TXP TXN 8 Y 9 IK TXP 9 8 Y8 0 LRK TXN T 0 N L K V K I0 TXP TXN TXP K0 MLK MLK IK LRK TO TO PORT P I TM TM0 M/ K K K0 W V MO RP k I TM TM0 M/ K Title K8 ize ocument Number Rev IT ate: Monay, October, 00 heet of
20 X.M MLK R JP XT J XT M U9 HU0 p U9 HU0 8 p XTL JP8 LK XT V U PR Q LK L Q JP 8/8 MLK U0 fs 0 LK Q 9 Q RT Q Q Q Q Q Q8 Q9 Q0 Q Q H00 8 JP9 LR 8 JP fs fs R8 JP0 XT V U Q Q Q Q RO NP 0 NT LK 9 LO LR U V 0 V 9 0 GN 8 IR G 9 M/ U H RP RP k k V for H, HU0, H00, 0 u 8 9 U H 0 U H U H U9 HU0 U9 9 8 HU0 U9 0 HU0 U9 V U PR 0 Q 9 LK L Q 8 8 T _LRK 8_IK HU0 Title K8 ize ocument Number Rev LOGI ate: Monay, October, 00 heet of
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SYNCHRONOUS SEQUENTIAL CIRCUITS
CHAPTER SYNCHRONOUS SEUENTIAL CIRCUITS Registers an counters, two very common synchronous sequential circuits, are introuce in this chapter. Register is a igital circuit for storing information. Contents
SN54HC42, SN74HC42 4-LINE TO 10-LINE DECODERS (1 of 10)
SNH, SNH -LINE TO -LINE EOERS ( of ) SLS EEMER REVISE MY Full ecoding of Input Logic ll Outputs re High for Invalid onditions lso for pplications as -Line to -Line ecoders Package Options Include Plastic
P D = 5 W Transient Voltage Suppressor. Package. Description. Features. Applications. Typical Application. (1) (2) (1) Cathode (2) Anode
P D = 5 W Transient Voltage Suppressor Data Sheet Description The is a power Zener diode designed for the protection of automotive electronic units, especially from the surge generated during load dump
DATA SHEET. BC817DPN NPN/PNP general purpose transistor DISCRETE SEMICONDUCTORS. Product data sheet Supersedes data of 2002 Aug 09.
DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D302 NPN/PNP general purpose transistor Supersedes data of 2002 Aug 09 2002 Nov 22 FEATURES High current (500 ma) 600 mw total power dissipation Replaces
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type SSM3K02F
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type SSM3K02F High Speed Switching Applications Unit: mm Small package Low on resistance : R on = 200 mω (max) (V GS = 4 V) : R on = 250 mω (max) (V
7-stage binary ripple counter
Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).
Low Capacitance, Low Charge Injection, ±15 V/+12 V icmos Quad SPST Switches ADG1212-EP
Enhanced Product Low Capacitance, Low Charge Injection, ±15 V/+12 V icmo Quad PT witches FEATURE 1 pf off capacitance 2.6 pf on capacitance
P D = 5 W / 6 W Transient Voltage Suppressor. Description. Package SZ-10. Features. Selection Guide. Applications. Typical Application
P D = 5 W / 6 W Transient Voltage Suppressor SZ-0N Series Data Sheet Description The SZ-0N series are power Zener diodes designed for the protection of automotive electronic units, especially from the
FDV301N Digital FET, N-Channel
FVN igital FET, N-Channel General escription This N-Channel logic level enhancement mode field effect transistor is produced using ON Semiconductor's proprietary, high cell density, MOS technology. This
Standard Products UT54ACS273/UT54ACTS273 Octal D-Flip-Flops with Clear. Datasheet December 16, 2011
Standard Products UT54AS273/UT54ATS273 Octal -Flip-Flops with lear atasheet ecember 16, 2011 www.aeroflex.com/logic FEATUES ontains eight flip-flops with single-rail outputs Buffered clock and direct clear
XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger
Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
CD54/74HC30, CD54/74HCT30
/70, /7T0 ata sheet acquired from arris Semiconductor SS ugust 997 - Revised September 00 igh Speed MOS Logic -Input NN ate [ /Title ( 0, 7 0, 7 T0) /Subject (igh Speed MOS Logic - eatures uffered Inputs
5-stage Johnson decade counter
Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
74LVC1G General description. 2. Features. Single D-type flip-flop with set and reset; positive edge trigger
Rev. 06 19 February 2008 Product data sheet 1. General description The is a single positive edge triggered -type flip-flop with individual data () inputs, clock (P) inputs, set (S) and reset (R) inputs,
Features. Symbol Parameter N-Channel P-Channel Units. Drain-Source Voltage, Power Supply Voltage V V GSS. Gate-Source Voltage, 8-8 V I D
FC6C ual N & P Channel, igital FET General escription These dual N & P Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor's proprietary, high cell density,
Maintenance/ Discontinued
CC Area Image Sensor MWAE mm (type-/) Wide CC Area Image Sensor Overview The MWAE is a mm (type-/) interline transfer CC (IT-CC) solid state image sensor device. This device uses photodiodes in the optoelectric
P D = 5 W / 6 W Transient Voltage Suppressor. Package SZ-10. Description. Features. Selection Guide. Applications. Typical Application
P D = 5 W / 6 W Transient Voltage Suppressor SZ-0N Series Data Sheet Description The SZ-0N series are power Zener diodes designed for the protection of automotive electronic units, especially from the
Top View. Part Number Case Packaging DMP6180SK3Q-13 TO252 (DPAK) 2,500/Tape & Reel
6V P-CHNNEL ENHNCEMENT MOE MOSFET Product Summary Features and Benefits BV SS -6V R S(ON) Max I T C = +25 C mω @ V = -V -4 4mΩ @ V = -4.5V -2 Low On-Resistance Low Input Capacitance Totally Lead-Free &
N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package using
Rev. 24 March 29 Product data sheet. Product profile. General description N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package
Green. Pin1. Part Number Case Packaging DMTH3004LPSQ-13 POWERDI ,500/Tape & Reel
NEW PROUCT AVANCE INFORMATION Product ummary BV 3V R (ON) Max 3.8mΩ @ V G = V 6mΩ @ V G = 4.5V escription and Applications I Max T C = +25 C 45A 5A This MOFET is designed to meet the stringent requirements
Octal D-type transparent latch; 3-state
Rev. 02 18 October 2007 Product data sheet 1. General description 2. Features The is an octal -type transparent latch featuring separate -type inputs for each latch and 3-state true outputs for bus-oriented
74LVC823A 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
INTEGRATED CIRCUITS inputs/outputs; positive-edge trigger (3-State) 1998 Sep 24 FEATURES 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic Supply voltage range of 2.7V to 3.6V Complies
TC4013BP,TC4013BF,TC4013BFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4013BP,TC4013BF,TC4013BFN TC4013B Dual D-Type Flip Flop TC4013B contains two independent circuits of D type flip-flop. The input level applied
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
TC74LCX244F,TC74LCX244FW,TC74LCX244FT,TC74LCX244FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LCX244F/FW/FT/FK TC74LCX244F,TC74LCX244FW,TC74LCX244FT,TC74LCX244FK Low-Voltage Octal Bus Buffer with 5-V Tolerant Inputs and Outputs The
74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.
Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
DATA SHEET. 74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state INTEGRATED CIRCUITS
INTEGRTE CIRCUITS T SHEET Octal -type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Supersedes data of 2003 Jun 20 2004 Mar 22 FETURES 5 V tolerant inputs and outputs, for
TL601, TL604, TL607, TL610 P-MOS ANALOG SWITCHES
TL0, TL0, TL0, TL0 P-MO NLOG WITCHE L0 D, JUNE 9 REVIED OCTOBER 9 witch ± 0-V nalog ignals TTL Logic Capability -to 0-V upply Ranges Low (00 Ω) On-tate Resistance High (0 Ω) Off-tate Resistance -Pin Functions
Dual JK flip-flop with reset; negative-edge trigger
Rev. 04 19 March 2008 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate MOS device that complies with JEDE standard no. 7. It is pin compatible with
74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.
Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
74AHC2G126; 74AHCT2G126
Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line
DG2707. High Speed, Low Voltage, 3, Differential 4:1 CMOS Analog Multiplexer/Switch. Vishay Siliconix FEATURES DESCRIPTION APPLICATIONS
G2707 High Speed, Low Voltage, 3, ifferential 4:1 CMOS Analog Multiplexer/Switch ESCRIPTION The G2707 is a high speed, low voltage, 3, differential 4:1 multiplexer. It operates from a 1.65 V to 4.3 V single
2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.
74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function
74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.
Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.
MMBV2101LT1 Series, MV2105, MV2101, MV2109, LV2209. Silicon Tuning Diodes pf, 30 VOLTS VOLTAGE VARIABLE CAPACITANCE DIODES
MMBVLT Series, MV5, MV, MV9, LV9 Preferred evice Silicon Tuning iodes These devices are designed in popular plastic packages for the high volume requirements of FM Radio and TV tuning and AFC, general
74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type SSM3J117TU. Characteristic Symbol Test Condition Min Typ. Max Unit
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type SSMJ7TU High-Speed Switching Applications 4 V drive Low ON-resistance: R on = 225 mω (max) (@V GS = ) R on = 7 mω (max) (@V GS = V) Absolute Maximum
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
8-bit binary counter with output register; 3-state
Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
1 pc Charge Injection, 100 pa Leakage, CMOS 5 V/+5 V/+3 V Quad SPST Switches ADG611/ADG612/ADG613
a FEATURE 1 pc Charge Injection 2.7 V to 5.5 V ual upply +2.7 V to +5.5 V ingle upply Automotive Temperature Range 4 C to +125 C 1 pa Max @ 25 C Leakage Currents 85 On-Resistance Rail-to-Rail witching
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 217 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
60 V, 0.3 A N-channel Trench MOSFET
Rev. 01 11 September 2009 Product data sheet 1. Product profile 1.1 General description ESD protected N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT2 (TO-26AB) Surface-Mounted
Quad SPST CMOS Analog Switches
G441, G442 Quad PT MO Analog witches ERIPTION The G441, G442 monolithic quad analog switches are designed to provide high speed, low error switching of analog and audio signals. The G441 has a normally
74AHC14; 74AHCT14. Hex inverting Schmitt trigger
Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
N-channel TrenchMOS logic level FET
Rev. 2 3 November 29 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
CD74HC195. High Speed CMOS Logic 4-Bit Parallel Access Register. Features. Description. Ordering Information. PInout. [ /Title (CD74 HC195 ) /Subject
Data sheet acquired from Harris Semiconductor SCHS165 September 1997 High Speed CMOS Logic 4-Bit Parallel Access Register [ /Title (CD74 HC195 ) /Subject High peed MOS ogic -Bit aralel ccess egiser) /Autho
The 74LV08 provides a quad 2-input AND function.
Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0
PSMN006-20K. N-channel TrenchMOS SiliconMAX ultra low level FET
Rev. 7 November 29 Product data sheet. Product profile. General description SiliconMAX ultra low level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
DATA SHEET. PMEM4010ND NPN transistor/schottky diode module DISCRETE SEMICONDUCTORS. Product data sheet Supersedes data of 2002 Oct 28.
DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D302 NPN transistor/schottky diode module Supersedes data of 2002 Oct 28 2003 Jul 04 FEATURES 600 mw total power dissipation High current capability
Pin 1 S S G. Bottom View. Part Number Case Packaging DMT3004LFG-7 POWERDI ,000/Tape & Reel DMT3004LFG-13 POWERDI ,000/Tape & Reel
YYWW NEW PROUCT Product ummary BV 3V R (ON) max 4.5mΩ @ V G = V 7.mΩ @ V G = 4.5V escription and Applications I max T C = +5 C (Note 9) 5A 5A This MOFET has been designed to minimize the on-state resistance
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
S S. Top View Bottom View
YYWW Product Summary BV SS 3V R S(ON) Max.mΩ @ V GS = V.mΩ @ V GS = 4.V escription and Applications I Max T C = + C 7A A This MOSFET is designed to minimize the on-state resistance (R S(ON)) and yet maintain
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 217 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
FDC3535. P-Channel Power Trench MOSFET -80 V, -2.1 A, 183 mω. FDC3535 P-Channel Power Trench MOSFET
FC55 P-Channel Power Trench MOSFET -8 V, -. A, 8 mω Features Max r S(on) = 8 mω at V S = - V, I = -. A Max r S(on) = mω at V S = -.5 V, I = -.9 A High performance trench technology for extremely low r
Linear Regulator Application Information
Linear Regulator Application Information IC Product Name BD00IA5WEFJ Topology LDO Linear Regulator Voltage source Input Output 1 2.4V to 5.5V 1.0V, 500mA *1 2 2.4V to 5.5V 1.2V, 500mA *1 3 2.4V to 5.5V
I D T A = +25 C. Part Number Case Packaging DMC4029SK4-13 TO ,500/Tape & Reel
AVANCE INFORMATION COMPLEMENTARY PAIR ENHANCEMENT MOE MOSFET Product Summary evice BV SS R S(ON) Max I T A = +5 C Q 4V 4mΩ @ V GS = V 8.3A 3mΩ @ V GS = 4.5V 7.A Q -4V 45mΩ @ V GS = -V -6.A 55mΩ @ V GS
NPN/PNP transistor pair connected as push-pull driver in a SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package.
Rev. 0 26 September 2006 Product data sheet. Product profile. General description NPN/PNP transistor pair connected as push-pull driver in a SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package..2
TOSHIBA Field Effect Transistor Silicon P Channel MOS Type SSM3J16TE. DC I D 100 ma Pulse I DP 200
High Speed Switching Applications Analog Switch Applications TOSHIBA Field Effect Transistor Silicon P Channel MOS Type SSMJ6TE Small package Low on-resistance : R on = 8 Ω (max) (@V GS = 4 V) : R on =