AKD5381-B AK5381 Evaluation Board Rev.1

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1 [AKD5381-] AKD5381- AK5381 Evaluation oar Rev.1 GENERAL DECRIPTION AKD5381- is an evaluation boar for the igital auio 4bit 96k A/D converter, AK5381. AKD5381- has analog input circuits an a igital interface transmitter,an can achieve the interface with igital auio systems via opt-connector. Orering guie AKD AK5381 Evaluation oar DIT (AK4114) with optical output UNCTION VA,VD AGND,DGND LIN RIN AK5381 AK4114 (DIT) Opt Out DP Data 10pin Heaer igure 1. AKD5381- lock Diagram * Circuit iagram an PC layout are attache at the en of this manual

2 [AKD5381-] 1. Evaluation oar Manual Operation sequence 1) et up the power supply lines. [VA] (re) =.7 5.5V or 15V : for VA of AK5381 (typ. 5.0V) [VD] (orange) =.7 5.5V : for VD of AK5381, 74HC14 (typ. 5.0V) [VCC] (re) = 3.3V : for AK4114 [AGND] (black) = 0V : for analog groun [DGND] (black) = 0V : for logic groun Each supply line shoul be istribute from the power supply unit. ) et up the evaluation moe, jumper pins an DIP switches. (ee the followings.) 3) Power on. The AK5381 an AK4114 shoul be reset once bringing W = L upon power-up. Evaluation moe (1) lave Moe (1-1) A/D evaluation using DIT function of AK4114 PORT (DIT) is use. DIT generates auio bi-phase signal from receive ata an which is output through optical connector (TOTX141). It is possible to connect s D/A converter evaluation boars on the igital-amplifier, which equips DIR input. Nothing shoul be connecte to PORT1 (DP). JP5 MCLK (1-) All interface signals incluing master clock are fe externally. PORT1 (DP) is use. All interface signals (MCLK, CLK, LRCK) are provie to the AK5381 through PORT1. JP5 (MCLK) shoul be open. The DI1 of W1 (MODE) shoul be set to H. JP5 MCLK - -

3 [AKD5381-] () Master Moe (-1) A/D evaluation using DIT function of AK4114 PORT (DIT) is use. DIT generates auio bi-phase signal from receive ata an which is output through optical connector (TOTX141). It is possible to connect s D/A converter evaluation boars on the igital-amplifier, which equips DIR input. Nothing shoul be connecte to PORT1 (DP). The DI1 of W1 (MODE) shoul be set to H. JP5 MCLK (-) Master clock is fe externally. PORT1 (DP) is use. MCLK is provie to the AK5381 through PORT1. JP5 (MCLK) shoul be open. The DI1 of W1 (MODE) shoul be set to H. JP5 MCLK Other jumper pins set up 1. JP1 (GND) : Analog groun an Digital groun OPEN : eparate. HORT : Common. (The connector DGND can be open.) <Default>. JP (CK1) : etting of CK1 pin for AK5381 H : Master moe L : lave moe <Default> 3. JP3 (VA) : elect VA for AK5381 VA : upply from VA connector <Default> REG : upply from regulator. VA connector shoul be supplie 15V. 4. JP4 (VD) : elect VD for AK5381 VA : upply from VA connector VD : upply from VD connector <Default> - 3 -

4 [AKD5381-] DIP witch set up [W1] (MODE1): etting the evaluation moe for AK5381 an AK4114 ON is H, O is L. CK1 shoul be set by JP. No. Name O ( L ) ON ( H ) 1 CK0 ee Table CK 3 DI M justifie I Compatible 4 DI1 AK4114 Master moe AK4114 lave moe Table 1. Moe etting CK CK1 CK0 Input Level HP Master/lave MCLK CLK L L L CMO ON lave 56/384/51/768fs 48fs or 3fs L L H CMO O lave 56/384/51/768fs 48fs or 3fs L H L CMO ON Master 56fs ( 96k) 64fs L H H CMO ON Master 51fs ( 48k) 64fs H L L TTL ON lave 56/384/51/768fs 48fs or 3fs H L H Reserve H H L CMO ON Master 384fs ( 96k) 64fs H H H CMO ON Master 768fs ( 48k) 64fs Table. Moe etting of AK5381 Note: AK4114 oes not support MCLK=384fs/51fs/768fs. PORT1 (DP) shoul be use when MCLK=384fs/51fs/768fs. The function of the toggle W Upper-sie is H an lower-sie is L. [W] (PDN): Resets the AK5381 an AK4114. Keep H uring normal operation

5 [AKD5381-] Analog Input Circuits Analog signal is input via J1(RIN) an J(LIN) of RCA connectors. J1 RIN C1 10u AINR J LIN C 10u AINL igure. Analog Input circuits * assumes no responsibility for the trouble when using the circuit examples

6 [AKD5381-] MEAUREMENT REULT [Measurement conition] Measurement unit : Auio Precision, ystem Two Cascae MCLK : 56fs CLK : 64fs fs : 48k, 96k it : 4bit Power upply : VA = VD = 5.0V (Using regulator) Interface : DIT Temperature : Room Parameter Result (Lch / Rch) Unit ADC Analog Input Characteristics: /(ND) ( 1 Input) fs=48k fs=96k 89.0 / / 86. D-Range ( 60 Input) fs=48k, A-weighte fs=96k 10.7 / / 99. /N fs=48k, A-weighte fs=96k 10.8 / / 99.4 Interchannel Isolation 13.6 /

7 [AKD5381-] [ADC Plot : fs=48k] AK5381 THDN vs. Input Level VA=VD=5.0V, fs=48k, fin=1k r igure 1. THDN vs. Input Level AK5381 THDN vs. Input requency VA=VD=5.0V, fs=48k, Input=-1r k k 5k 10k 0k igure. THDN vs. Input requency - 7 -

8 [AKD5381-] 0 AK5381 Linearity VA=VD=5.0V, fs=48k, fin=1k r igure 3. Linearity -0.5 AK5381 requency Response VA=VD=5.0V, fs=48k, Input=-1r k k 5k 10k 0k igure 4. requency Response - 8 -

9 [AKD5381-] AK5381 Crosstalk VA=VD=5.0V, fs=48k, Input=-1r k k 5k 10k 0k igure 5. Crosstalk AK5381 T Plot VA=VD=5.0V, fs=48k, Input=-1r, fin=1k k k 5k 10k 0k igure 6. T Plot - 9 -

10 [AKD5381-] AK5381 T Plot VA=VD=5.0V, fs=48k, Input=-60r, fin=1k k k 5k 10k 0k igure 7. T Plot AK5381 T Plot VA=VD=5.0V, fs=48k, fin=none k k 5k 10k 0k igure 8. T Plot

11 [AKD5381-] [ADC Plot : fs=96k] AK5381 THDN vs. Input Level VA=VD=5.0V, fs=96k, fin=1k r igure 9. THDN vs. Input Level AK5381 THDN vs. Input requency VA=VD=5.0V, fs=96k, Input=-1r k k 5k 10k 0k 40k igure 10. THDN vs. Input requency

12 [AKD5381-] 0 AK5381 Linearity VA=VD=5.0V, fs=96k, fin=1k r igure 11. Linearity AK5381 requency Response VA=VD=5.0V, fs=96k, Input=-1r k k 5k 10k 0k 40k igure 1. requency Response - 1 -

13 [AKD5381-] AK5381 Crosstalk VA=VD=5.0V, fs=96k, Input=-1r k k 5k 10k 0k 40k igure 13. Crosstalk AK5381 T Plot VA=VD=5.0V, fs=96k, Input=-1r, fin=1k k k 5k 10k 0k 40k igure 14. T Plot

14 [AKD5381-] AK5381 T Plot VA=VD=5.0V, fs=96k, Input=-60r, fin=1k k k 5k 10k 0k 40k igure 15. T Plot AK5381 T Plot VA=VD=5.0V, fs=96k, fin=none k k 5k 10k 0k 40k igure 16. T Plot

15 [AKD5381-] Revision History Date Manual oar Reason Contents (YY/MM/DD) Revision Revision 04/05/14 KM irst Eition 05/01/14 KM oar Name Change AKD5381 Rev. AKD5381- Rev.0 Circuit Change The information on AK5357 was remove. 06/04/4 KM Error Correction oar Rev: 0 1 IMPORTANT NOTICE These proucts an their specifications are subject to change without notice. efore consiering any use or application, consult the Asahi Kasei Microsystems Co., Lt. () sales office or authorize istributor concerning their current status. assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information containe herein. Any export of these proucts, or evices or systems containing them, may require an export license or other official approval uner the law an regulations of the country of export pertaining to customs an tariffs, currency exchange, or strategic materials. proucts are neither intene nor authorize for use as critical components in any safety, life support, or other hazar relate evice or system, an assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of. As use here: (a) A hazar relate evice or system is one esigne or intene for life support or maintenance of safety or for applications in meicine, aerospace, nuclear energy, or other fiels, in which its failure to function or perform may reasonably be expecte to result in loss of life or in significant injury or amage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expecte to result, whether irectly or inirectly, in the loss of the safety or effectiveness of the evice or system containing it, an which must therefore meet very high stanars of performance an reliability. It is the responsibility of the buyer or istributor of an prouct who istributes, isposes of, or otherwise places the prouct with a thir party to notify that party in avance of the above content an conitions, an the buyer or istributor agrees to assume any an all responsibility an liability for an hol harmless from any an all claims arising from the use of sai prouct in the absence of such notification

16 A C D E E JP1 GND DGND AGND E J1 RIN C1 10u VD D J LIN C 10u U1 1 AINR AINL CK0 CK W1 DI1 MODE CK0 CK DI DI RP1 47k D L 3 CK1 DI 14 DI0 C VA 1 C10 47u C7 0.1u T1 JP3 NJM78M05A REG 1 IN GND OUT 3 C8 47u VA REG C9 0.1u VD REG JP CK1 H R3 5.1 JP4 VD VD VA C3 C4.u 0.1u C5 10u C6 0.1u C11 C1 10u 0.1u VCOM AGND VA VD DGND AK5381 PDN 13 CLK 1 MCLK 11 LRCK 10 DTO 9 R1 51 R 51 R4 51 R5 51 CLK MCLK LRCK DTO C 1 C13 47u VD 1 D1 HU119 R6 10k UA 74HC14 U 74HC14 L H PDN W PDN 3 1 C14 0.1u 6 5 VD UC 74HC14 for 74HC C15 0.1u UD 74HC UE 74HC14 A 1 13 A A U 74HC14 C D Title AKD5381- ize Document Number Rev A3 AK Date: Monay, April 4, 006 heet 1 of E

17 A C D E E REG VCC E C17 10u C16 47u C18 0.1u C u D 48 RX3 NC RX 45 D 1 IP0 INT0 36 NC OCK0 35 DI0 3 DI0 OCK1 34 MCLK C DI TET DI1 NC DI IP1 P/N CM1 33 CM0 3 PDN 31 PDN 30 XTI XTO 9 DAUX 8 CLK LRCK DTO MCLK CLK LRCK DTO PORT DP C 10 XTL0 MCKO 7 11 XTL1 ICK 6 C4 10u C5 10u A A C6 0.1u TVDD DV TX0 TX1 OUT COUT UOUT VOUT DVDD DV MCKO1 TET1 44 RX1 NC 43 4 RX0 AV 41 VCOM 40 R 39 AVDD INT1 U3 AK VIN 14 DTO 5 15 LRCK C0 10p X1 1.88M C1 10p 18 C 0.1u C3 0.1u 3 4 JP5 MCLK PORT IN 3 VCC GND 1 DIT C D Title AKD5381- ize Document Number Rev A3 AK Date: Monay, April 4, 006 heet of E A

AKD5357-B AK5357 Evaluation Board Rev.2

AKD5357-B AK5357 Evaluation Board Rev.2 [AKD5357-] AKD5357- AK5357 Evaluation oar Rev. GENERAL DECRIPTION AKD5357- is an evaluation boar for the igital auio 4bit 96k A/D converter, AK5357. AKD5357- has analog input circuits an a igital interface