About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd.

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Merryl Cole
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Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co.

1 Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, Therefore, please accept that although the terms and marks of "Oki Electric Industry Co., Ltd.", Oki Electric, and "OKI" remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.". It is a change of the company name, the company trademark, and the logo, etc., and NOT a content change in documents. October 1, 2008 OKI Semiconductor Co., Ltd Higashiasakawa-cho, Hachioji-shi, Tokyo , Japan

2 ,19,30-Word -Bit DYNAMIC RAM : FAST PAGE MODE TYPE This version: January Previous version : Aug DESCRIPTION The is a,19,30-word -bit dynamic RAM fabricated in Oki s silicon-gate CMOS technology. The achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The is available in a 26/2-pin plastic SOJ or 26/2-pin plastic TSOP. FEATURES,19,30-word -bit configuration Single 5V power supply, ±10% tolerance Input : TTL compatible, low input capacitance Output : TTL compatible, 3-state Refresh : 208 cycles/32ms Fast page mode, read modify write capability before refresh, hidden refresh, -only refresh capability Packages 26/2-pin 300mil plastic SOJ (SOJ26/2-P ) (Product : -xxsj) 26/2-pin 300mil plastic TSOP (TSOPII26/2-P K) (Product : -xxts-k) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) Cycle Time t RAC (Min.) Power Dissipation Operating (Max.) 50ns 25ns 13ns 13ns 90ns 550mW 60ns 30ns 15ns 15ns 110ns 95mW 70ns 35ns 20ns 20ns 130ns 0mW Standby (Max.) 5.5mW 1/15

3 PIN CONFIGURATION (TOP VIEW) V CC DQ1 DQ2 NC V SS 25 DQ 2 DQ OE 21 A9 V CC DQ1 DQ2 NC V SS 25 DQ 2 DQ OE 21 A9 A10 8 A0 9 A1 10 A2 11 A3 12 V CC A8 18 A7 17 A6 16 A5 15 A 1 V SS A10 8 A0 9 A1 10 A2 11 A3 12 V CC A8 18 A7 17 A6 16 A5 15 A 1 V SS 26/2-Pin Plastic SOJ 26/2-Pin Plastic TSOP (K Type) Pin Name A0 A10 DQ1 DQ OE V CC V SS NC Function Address Input Address Strobe Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5V) Ground (0V) No Connection Note : The same power supply voltage must be provided to every V CC pin, and the same GND voltage level must be provided to every V SS pin. 2/15

4 BLOCK DIAGRAM Timing Generator Timing Generator A0 A10 11 Address Buffers Internal Address Counter Refresh Control Clock 11 Decoders Sense Amplifiers Write Clock Generator I/O Selector Output Buffers Input Buffers OE DQ1 DQ 11 Address Buffers 11 Decoders Word Drivers Memory Cells V CC On Chip V BB Generator V SS 3/15

5 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage V CC Supply relative to V SS V T 0.5 to V CC +0.5 V Short Circuit Output Current I OS 50 ma Power Dissipation P D* 1 W Operating Temperature T opr 0 to 70 C Storage Temperature T stg 55 to 150 C *: Ta = 25 C RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70 C) Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage V CC V V SS V Input High Voltage 2. V CC *1 V Input Low Voltage 0.5 *2 0.8 V Notes: *1. The input voltage is V CC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which V CC is applied). *2. The input voltage is V SS 1.0V when the pulse width is less than 20ns (the pulse width respect to the point at which V SS is applied). PIN CAPACITANCE (Vcc = 5V ± 10%, Ta = 25 C, f = 1 MHz) Parameter Symbol Min. Min. Unit Input Capacitance (A0 A10) C IN1 5 pf Input Capacitance (,,, OE) C IN2 7 pf Output Capacitance (DQ1 DQ) C I/O 7 pf /15

6 DC CHARACTERISTICS (V CC = 5V ± 10%, Ta = 0 to 70 C) Parameter Symbol Condition MSM F-50 MSM F-60 MSM F-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage V OH I OH = 5.0mA 2. V CC 2. V CC 2. V CC V Output Low Voltage V OL I OL =.2mA V Input Leakage Current I LI 0V V I 6.5V; All other pins not under test = 0V µa Output Leakage Current I LO DQ disable 0V V O V CC µa Average Power Supply Current (Operating) I CC1, cycling, = Min ma 1,2 Power Supply Current (Standby) I CC2, = 2 2 2, V CC 0.2V ma 1 Average Power Supply Current I CC3 cycling, =, ma 1,2 (-only Refresh) = Min. Power Supply Current (Standby) =, I CC5 =, DQ = enable ma 1 Average Power Supply Current ( before Refresh) I CC6 = cycling, before ma 1,2 Average Power Supply Current (Fast Page Mode) =, I CC7 cycling, t PC = Min ma 1,3 Notes: 1. I CC Max. is specified as I CC for output open condition. 2. The address can be changed once or less while =. 3. The address can be changed once or less while =. 5/15

7 AC CHARACTERISTICS (1/2) Parameter Symbol MSM F-50 (V CC = 5V ± 10%, Ta = 0 to 70 C) Note1,2,3,11,12 MSM F-60 MSM F-70 Min. Max. Min. Max. Min. Max. Unit Note Random Read or Write Cycle Time ns Read Modify Write Cycle Time t RWC ns Fast Page Mode Cycle Time t PC ns Fast Page Mode Read Modify Write Cycle Time t PRWC ns Access Time from t RAC ns, 5, 6 Access Time from ns, 5 Access Time from Address ns, 6 Access Time from Precharge t CPA ns Access Time from OE ns Output Low Impedance Time from to Data Output Buffer Turnoff Delay Time OE to Data Output Buffer Turn-off Delay Time t CLZ ns t OFF ns 7 t OEZ ns 7 Transition Time t T ns 3 Refresh Period t REF ms Precharge Time ns Pulse Width t 50 10, , ,000 ns Pulse Width (Fast Page Mode) t P , , ,000 ns Hold Time t RSH ns Hold Time referenced to OE t ROH ns Precharge Time (Fast Page Mode) t CP ns Pulse Width t 13 10, , ,000 ns Hold Time t CSH ns to Precharge Time ns Hold Time from Precharge t RHCP ns to Delay Time D ns 5 to Address Delay Time t RAD ns 6 Address Set-up Time ns 6/15

8 AC CHARACTERISTICS (2/2) Parameter Symbol MSM F-50 (V CC = 5V ± 10%, Ta = 0 to 70 C) Note1,2,3,11,12 MSM F-60 MSM F-70 Min. Max. Min. Max. Min. Max. Unit Note Address Hold Time t RAH ns Address Set-up Time ns Address Hold Time ns Address to Lead Time t RAL ns Read Command Set-up Time ns Read Command Hold Time H ns 8 Read Command Hold Time referenced to t RRH ns 8 Write Command Set-up Time t WCS ns 9 Write Command Hold Time t WCH ns Write Command Pulse Width ns OE Command Hold Time t OEH ns Write Command to Lead Time t RWL ns Write Command to Lead Time t CWL ns Data-in Set-up Time ns 10 Data-in Hold Time ns 10 OE to Data-in Delay Time t OED ns to Delay Time t CWD ns 9 Address to Delay Time t AWD ns 9 to Delay Time t RWD ns 9 Precharge Delay Time t CPWD ns 9 Active Delay Time from Precharge to Set-up Time ( before ) to Hold Time ( before ) to Precharge Time ( before ) Hold Time from ( before ) C ns t CSR ns t CHR ns t WRP ns t WRH ns to Set-up Time (Test Mode) t WTS ns to Hold Time (Test Mode) t WTH ns 7/15

9 Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (-only refresh or before refresh) before proper device operation is achieved. 2. The AC characteristics assume t T = 5ns. 3. (Min.) and (Max.) are reference levels for measuring input timing signals. Transition times (t T ) are measured between and is measured with a load circuit equivalent to 2TTL load and 50pF, and -60/-70 is measured with a load circuit equivalent to 2TTL load and 100pF. 5. Operation within the D (Max.) limit ensures that t RAC (Max.) can be met. D (Max.) is specified as a reference point only. If D is greater than the specified D (Max.) limit, then the access time is controlled by. 6. Operation within the t RAD (Max.) limit ensures that t RAC (Max.) can be met. t RAD (Max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (Max.) limit, then the access time is controlled by. 7. t OFF (Max.) and t OEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. H or t RRH must be satisfied for a read cycle. 9. t WCS, t CWD, t RWD, t AWD and t CPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t CWD t CWD (Min.), t RWD t RWD (Min.), t AWD t AWD (Min.) and t CPWD t CPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the, leading edges in an early write cycle, and to the leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a and before refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test CA9 and CA10 are not used and each DQ pin now access -bit locations. Since all DQ pins are used, a total 16 data bits can be written in parallel into the memory array. In a read cycle, if data bits are equal, the DQ pin will indicate a high level. If the data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a -only refresh cycle or a before refresh cycle. 12. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/15

10 TIMING CHART Read Cycle t t CSH D t RSH t t RAD t RAL t RAH Address t RRH t ROH H OE t RAC t OEZ t OFF DQ V OH V OL Open t CLZ Valid Data-out Write Cycle (Early Write) t t CSH D t RSH t t RAD t RAL t RAH Address t WCS t WCH t CWL t RWL OE DQ Valid Data-in Open 9/15

11 Read Modify Write Cycle t RWC t D t CSH t RSH t t RAD t RAH t CWL t RWL Address Colum t CWD t RWD t AWD t OEH OE t RAC t OED t OEZ DQ V I/OH V I/OL t CLZ Valid Data-out Valid Data-in 10/15

12 Fast Page Mode Read Cycle t P t PC t RHCP tcrp D t t CP t t CP t RSH t t RAD t CSH t RAL t RAH Address H H H t RRH OE t RAC t OFF t CPA t OFF t CPA t OFF DQ V OH V OL t CLZ t OEZ Valid Data-out t CLZ Valid Data-out toez t CLZ t OEZ Valid Data-out Fast Page Mode Write Cycle (Early Write) t P t PC t RHPC D t CP t CP t RSH t t t t RAD t CSH t RAL t RAH Address t RWL t CWL t CWL t CWL t WCS t WCH t WCS t WCH t WCS t WCH DQ Valid * Data-in Valid * Data-in Valid * Data-in Note: OE = 11/15

13 Fast Page Mode Read Modify Write Cycle t CSH t P t PRWC trsh D t t CP t t CP t t RAD t RAH tasc t CWL t CWL t RAL Address t PWD t CWD t CPWD t CWD t CPWD t CWD t CWL t RWL t RAC t AWD t CPA t AWD t AWD t ROH t CPA OE t OED t OEZ t OED t OEZ t OED t OEZ DQ V I/OH V I/OL Out In Out In Out In t CLZ t CLZ t CLZ Note: In = Valid Data-in, Out = Valid Data-out -only Refresh Cycle t C t RAH Address t OFF DQ V OH V OL Open Note:, OE = 12/15

14 before Refresh Cycle t C t CP t CSR C t CHR t WRP t WRH t WRP t CEZ DQ V OH V OL Open Note: OE, Address = Hidden Refresh Read Cycle t t D t RSH t CHR t RAD t RAH Address t RRH t RAL t REZ t ROH t WRP t WRH t CEZ OE t RAC t OEZ DQ V OH V OL Open tclz Valid Data-out 13/15

15 Hidden Refresh Write Cycle t t D t RSH t CHR t RAD t RAH Address t RAL t RWL twcs t WCH t WRP t WRH OE DQ Valid Data-in Test Mode-in Cycle t C t CP t CSR t CHR t WTS t WTH t OFF DQ Open Note: OE, Address = 1/15

16 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature.. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 15/15

IBM B IBM P 8M x 8 12/11 EDO DRAM

IBM B IBM P 8M x 8 12/11 EDO DRAM 8M x 812/11, 3.3V, EDO. 8M x 812/11, 3.3V, LP, SR, EDO. Features 8,388,608 word by 8 bit organization Single 3.3 ±0.3V power supply Extended Data Out before Refresh - 4096 cycles/retention Time only Refresh