Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 WE# RAS# A0 A1 A2 A3 Vcc

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1 TECHNOLOGY I. MEG x 6 DRAM MT4CM6C3 MT4LCM6C3 FEATURES JEDEC- and industry-standard x6 timing functions pinouts and packages High-performance low power CMOS silicon-gate process Single power supply (+3.3 ±.3 or 5 ±%) All inputs outputs and clocks are TTL-compatible Refresh modes: -ONLY CAS#-BEFORE- (CBR) and HIDDEN Optional Self Refresh (S) for low power data retention BYTE WRITE and BYTE READ access cycles 24-cycle refresh ( row column addresses) 5-tolerant inputs and I/Os on 3.3 devices OPTIONS MARKING oltage 3.3 LC 5 C Packages Plastic SOJ (4 mil) DJ Plastic TSOP (4 mil) TG Timing 6ns access -6 7ns access (3.3 only) -7 Refresh Rate Standard 6ms period None Self Refresh and 28ms period S Part Number Example: MT4LCM6C3TG-6 Note: The Meg x 6 base number differentiates the offerings in one place - MT4LCM6C3. The third field distinguishes the low voltage offering: LC designates cc = 3.3 and C designates cc = 5. KEY TIMING PARAMETERS SPEED t RC t RAC t PC t AA t CAC t RP -6 ns 6ns 35ns 3ns 5ns 4ns -7 3ns 7ns 4ns 35ns 2ns 5ns GENERAL DESCRIPTION The Meg x 6 DRAM is a randomly accessed solid-state memory containing bits organized in a x6 configuration. The Meg x 6 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins cc DQ DQ2 DQ3 DQ4 cc DQ5 DQ6 DQ7 DQ8 A A A2 A3 cc Note: PIN ASSIGNMENT (Top iew) 42-Pin SOJ (DA-7) ss DQ6 DQ5 DQ4 DQ3 ss DQ2 DQ DQ DQ9 CASL# CASH# OE# A9 A8 A7 A6 A5 A4 ss cc DQ DQ2 DQ3 DQ4 cc DQ5 DQ6 DQ7 DQ8 A A A2 A3 cc 44/5-Pin TSOP (DB-6) MEG x 6 PART NUMBERS PART NUMBER CC PACKAGE REFRESH MT4LCM6C3DJ 3.3 SOJ Standard MT4LCM6C3DJS 3.3 SOJ Self MT4LCM6C3TG 3.3 TSOP Standard MT4LCM6C3TGS 3.3 TSOP Self MT4CM6C3DJ 5 SOJ Standard MT4CM6C3DJS 5 SOJ Self MT4CM6C3TG 5 TSOP Standard MT4CM6C3TGS 5 TSOP Self (CASL# and CASH#). These function in an identical manner to a single CAS# of other DRAMs in that either CASL# or CASH# will generate an internal CAS#. The CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and the last CAS# to transition back HIGH. Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ-DQ8) and CASH# transitioning LOW selects an access cycle for the upper byte (DQ9-DQ6) The # symbol indicates signal is active LOW ss DQ6 DQ5 DQ4 DQ3 ss DQ2 DQ DQ DQ9 CASL# CASH# OE# A9 A8 A7 A6 A5 A4 ss Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

2 TECHNOLOGY I. MEG x 6 GENERAL DESCRIPTION (continued) Each bit is uniquely addressed through the 2 address bits during READ or WRITE cycles. These are entered bits (A-A9) at a time. is used to latch the first bits and CAS# the latter bits. The CAS# function is determined by the first CAS# (CASL# or CASH#) to transition LOW and the last one to transition back HIGH. The CAS# function also determines whether the cycle will be a refresh cycle (-ONLY) or an active cycle (READ WRITE or READ WRITE) once goes LOW. The CASL# and CASH# inputs internally generate a CAS# signal functioning in an identical manner to the single CAS# input of other DRAMs. The key difference is each CAS# input (CASL# and CASH#) controls its corresponding DQ tristate logic (in conjunction with OE# and ). CASL# controls DQ through DQ8 and CASH# controls DQ9 through DQ6. The two CAS# controls give the Meg x 6 DRAM BYTE WRITE cycle capabilities. A logic HIGH on dictates READ mode while a logic LOW on dictates WRITE mode. During a WRITE cycle data-in (D) is latched by the falling edge of or CAS whichever occurs last. Taking LOW will initiate a WRITE cycle selecting DQ through DQ6. If goes LOW prior to CAS# going LOW the output pin(s) remain open (High-Z) until the next CAS# cycle. If goes LOW after CAS# goes LOW and data reaches the output pins data-out (Q) is activated and retains the selected cell data as long as CAS# and OE# remain LOW (regardless of or ). This late pulse results in a READ WRITE cycle. The 6 data inputs and 6 data outputs are routed through 6 pins using common I/O. Pin direction is controlled by OE# and. FAST PAGE MODE FAST PAGE MODE operations allow faster data operations (READ WRITE or READ-MODIFY-WRITE) within a row-address-defined (A -A9) page boundary. The FAST PAGE MODE cycle is always initiated with a row address strobed-in by followed by a column address strobedin by CAS#. CAS# may be toggled-in by holding LOW and strobing-in different column addresses thus executing faster memory cycles. Returning HIGH terminates the FAST PAGE MODE operation. WORD WRITE LOWER BYTE WRITE CASL# CASH# LOWER BYTE (DQ-DQ8) OF WORD STORED INPUT INPUT STORED STORED INPUT INPUT STORED UPPER BYTE (DQ9-DQ6) OF WORD ADDRESS ADDRESS = NOT EFFECTIE (DON'T CARE) Figure WORD AND BYTE WRITE EAMPLE 2 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

3 TECHNOLOGY I. MEG x 6 FAST PAGE MODE (continued) Returning and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is also preconditioned for the next cycle during the HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any cycle (READ WRITE) or refresh cycle ( ONLY CBR or HIDDEN) so that all 24 combinations of addresses (A-A9) are executed at least every 6ms (28ms on the S version) regardless of sequence. The CBR Refresh cycle will also invoke the refresh counter and controller for row-address control. BYTE ACCESS CYCLE The BYTE WRITEs and BYTE READs are determined by the use of CASL# and CASH#. Enabling CASL# will select a lower BYTE access (DQ-DQ8). Enabling CASH# will select an upper BYTE access (DQ9-DQ6). Enabling both CASL# and CASH# selects a WORD WRITE cycle. The Meg x 6 DRAM may be viewed as two Meg x 8 DRAMs that have common input controls with the exception of the CAS# inputs. Figure illustrates the BYTE WRITE and WORD WRITE cycles. Figure 2 illustrates BYTE READ and WORD READ cycles. Additionally both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However an EARLY WRITE on one byte and after a CAS# precharge has been satisfied a LATE WRITE on the other byte are permissible. WORD READ LOWER BYTE READ CASL# CASH# LOWER BYTE (DQ-DQ8) OF WORD STORED OUTPUT OUTPUT STORED STORED OUTPUT OUTPUT STORED UPPER BYTE (DQ9-DQ6) OF WORD ADDRESS ADDRESS Z = High-Z Figure 2 WORD READ EAMPLE 3 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

4 TECHNOLOGY I. MEG x 6 REFRESH Preserve correct memory cell data by maintaining power and executing any cycle (READ WRITE) or refresh cycle (-ONLY CBR or HIDDEN) so that all 24 combinations of addresses are executed within t REF (MA) regardless of sequence. The CBR and Extended and Self Refresh cycles will invoke the internal refresh counter for automatic addressing. The optional Self Refresh mode is available on the S version. The S option allows the user a dynamic refresh data retention mode at the extended refresh period of 28ms i.e. 25µs per row when using distributed CBR refreshes. The S option also allows the user the choice of a fully static low-power data retention mode. The optional Self Refresh feature is initiated by performing a CBR Refresh cycle and holding LOW for the specified t RASS. The Self Refresh mode is terminated by driving HIGH for a minimum time of t RPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh sequence a burst refresh is not required upon exiting Self Refresh. However if the DRAM controller utilizes - ONLY or burst refresh sequence all 24 rows must be refreshed within the average internal refresh rate prior to the resumption of normal operation. STANDBY Returning and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the HIGH time. FUTIONAL BLOCK DIAGRAM CASL# CASH# CAS# -IN BUFFER DQ NO. 2 CLOCK GENERATOR 6 DQ6 A A A2 A3 A4 A5 A6 A7 A8 A9 ADDRESS BUFFER REFRESH CONTROLLER REFRESH COUNTER ADDRESS BUFFERS () DECODER 24 DECODER 24 SENSE AMPLIFIERS I/O GATING 24 x x 24 x 6 MEMORY ARRAY -OUT BUFFER 6 OE# NO. CLOCK GENERATOR cc ss 4 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

5 TECHNOLOGY I. MEG x 6 TRUTH TABLE ADDRESSES FUTION CASL# CASH# OE# t R t C DQs NOTES Standby H H H High-Z READ: WORD L L L H L COL Data-Out READ: LOWER BYTE L L H H L COL Lower Byte Data-Out Upper Byte Data-Out READ: UPPER BYTE L H L H L COL Lower Byte Data-Out Upper Byte Data-Out WRITE: WORD L L L L COL Data-In (EARLY WRITE) WRITE: LOWER L L H L COL Lower Byte Data-In BYTE (EARLY) Upper Byte High-Z WRITE: UPPER L H L L COL Lower Byte High-Z BYTE (EARLY) Upper Byte Data-In READ WRITE L L L H L L H COL Data-Out Data-In PAGE-MODE st Cycle L H L H L H L COL Data-Out READ 2nd Cycle L H L H L H L n/a COL Data-Out PAGE-MODE st Cycle L H L H L L COL Data-In WRITE 2nd Cycle L H L H L L n/a COL Data-In PAGE-MODE st Cycle L H L H L H L L H COL Data-Out Data-In READ-WRITE 2nd Cycle L H L H L H L L H n/a COL Data-Out Data-In HIDDEN READ L H L L L H L COL Data-Out REFRESH WRITE L H L L L L COL Data-In 2 -ONLY REFRESH L H H n/a High-Z CBR REFRESH H L L L H High-Z 3 SELF REFRESH H L L L H High-Z 3 NOTE:. These WRITE cycles may also be BYTE WRITE cycles (either CASL# or CASH# active). 2. EARLY WRITE only. 3. Only one CAS# must be active (CASL# or CASH#). 5 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

6 TECHNOLOGY I. MEG x 6 ABSOLUTE MAIMUM RATINGS* oltage on CC pin Relative to SS: to to +7 oltage on Inputs or I/O pins Relative to SS: to to +7 Operating Temperature T A (ambient)... C to +7 C Storage Temperature (plastic) C to +5 C Power Dissipation... W Short Circuit Output Current... 5mA *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 2 3) PARAMETER/CONDITION NOTES Supply oltage CC Input High oltage: alid Logic ; all inputs I/Os and any IH CC + Input Low oltage: alid Logic ; all inputs I/Os and any Input Leakage Current: Any input at IN ( IN IH MA ); II µa all other pins not under test = Output High oltage: IOUT = -2mA (3.3) -5mA (5.) OH Output Low oltage: IOUT = 2mA (3.3) 4.2mA (5.) OL Output Leakage Current: Any output at OUT ( OUT 5.5); IOZ µa DQ is disabled and in High-Z state 6 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

7 TECHNOLOGY I. MEG x 6 ICC OPERATING CONDITIONS AND MAIMUM LIMITS (Notes: 2 3) (CC MIN CC CC MA ) PARAMETER/CONDITION SYM SPEED UNITS NOTES STANDBY CURRENT: TTL ICC ALL 2 ma ( = CAS# = IH) STANDBY CURRENT: CMOS (non-s version only) ICC2 ALL 5 5 µa 22 ( = CAS# = other inputs = CC -.2) STANDBY CURRENT: CMOS (S version only) ICC2 ALL 5 5 µa 22 ( = CAS# = other inputs = CC -.2) OPERATING CURRENT: Random READ/WRITE ma 3 23 Average power supply current ICC3-7 6 ( CAS# address cycling: t RC = t RC [MIN]) OPERATING CURRENT: FAST PAGE MODE -6 9 ma 3 23 Average power supply current ICC4-7 8 ( = CAS# address cycling: t PC = t PC [MIN]) REFRESH CURRENT: -ONLY ma 3 Average power supply current ICC5-7 6 ( cycling CAS# = IH: t RC = t RC [MIN]) REFRESH CURRENT: CBR ma 3 4 Average power supply current ICC6-7 6 ( CAS# address cycling: t RC = t RC [MIN]) REFRESH CURRENT: Extended (S version only) Average power supply current: CAS# =.2 or CBR cycling; ICC7 ALL 3 3 µa 3 4 = t RAS (MIN); = CC -.2; A-A OE# and DIN = CC -.2 or.2 (DIN may be left open) REFRESH CURRENT: Self (S version only) Average power supply current: CBR with t RASS (MIN) and ICC8 ALL 3 3 µa 3 4 CAS# held LOW; = CC -.2; A-A OE# and DIN = CC -.2 or.2 (DIN may be left open) 7 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

8 TECHNOLOGY I. MEG x 6 CAPACITAE PARAMETER SYMBOL MA UNITS NOTES Input Capacitance: Addresses CI 5 pf 2 Input Capacitance: CASL# CASH# OE# CI2 7 pf 2 Input/Output Capacitance: DQ CIO 7 pf 2 AC ELECTRICAL CHARACTERISTICS (Notes: ) (CC MIN CC CC MA ) AC CHARACTERISTICS * PARAMETER SYM MIN MA MIN MA UNITS NOTES Access time from column address t AA 3 35 ns Column-address hold time (referenced to ) t AR ns Column-address setup time t ASC ns 27 Row-address setup time t ASR ns Column-address to delay time t AWD 55 6 ns 8 Access time from CAS t CAC 5 2 ns 29 Column-address hold time t CAH 2 ns 27 CAS# pulse width t CAS 5 2 ns 35 CAS# LOW to don t care during Self Refresh t CHD 5 5 ns CAS# hold time (CBR Refresh) t CHR 5 ns 4 28 Last CAS# going LOW to first CAS# to return HIGH t CLCH ns 3 CAS# to output in Low-Z t CLZ 3 3 ns CAS# precharge time t CP ns 32 Access time from CAS# precharge t CPA 35 4 ns 28 CAS# to precharge time t CRP 5 5 ns 28 CAS# hold time t CSH 6 7 ns 28 CAS# setup time (CBR Refresh) t CSR 5 5 ns 4 27 CAS# to delay time t CWD 4 45 ns 8 27 Write command to CAS# lead time t CWL 5 2 ns 23 3 Data-in hold time t DH 2 ns 9 29 Data-in setup time t DS ns 9 29 Output disable t OD ns Output enable t OE 5 2 ns 3 OE# hold time from t OEH 5 2 ns 25 during READ-MODIFY-WRITE cycle Output buffer turn-off delay t OFF ns OE# setup prior to during HIDDEN Refresh cycle t ORD ns FAST-PAGE-MODE READ or WRITE cycle time t PC 35 4 ns 3 FAST-PAGE-MODE READ-WRITE cycle time t PRWC ns 3 *3.3 only 8 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

9 TECHNOLOGY I. MEG x 6 AC ELECTRICAL CHARACTERISTICS (Notes: ) (CC MIN CC CC MA ) AC CHARACTERISTICS * PARAMETER SYM MIN MA MIN MA UNITS NOTES Access time from t RAC 6 7 ns to column-address delay time t RAD 5 5 ns 5 Row-address hold time t RAH ns pulse width t RAS 6 7 ns pulse width (FAST PAGE MODE) t RASP ns pulse width (Self Refresh) t RASS µs Random READ or WRITE cycle time t RC 3 ns to CAS# delay time t RCD 2 2 ns 4 27 Read command hold time (referenced to CAS) t RCH ns 6 28 Read command setup time t RCS ns 27 Refresh period (24 cycles) t REF 6 6 ms Refresh period (24 cycles) S version t REF ms precharge time t RP 4 5 ns to CAS# precharge time t RPC ns precharge time (Self Refresh) t RPS 3 ns Read command hold time (referenced to ) t RRH ns 6 hold time t RSH 5 2 ns 36 READ WRITE cycle time t RWC 55 8 ns to delay time t RWD ns 8 Write command to lead time t RWL 5 2 ns Transition time (rise or fall) t T ns Write command hold time t WCH 2 ns 36 Write command hold time (referenced to ) t WCR ns command setup time t WCS ns 8 27 Write command pulse width t WP 5 ns hold time (CBR Refresh) t WRH ns setup time (CBR Refresh) t WRP ns *3.3 only 9 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

10 TECHNOLOGY I. MEG x 6 NOTES. All voltages referenced to SS. 2. This parameter is sampled. CC = +3; f = MHz. 3. ICC is dependent on output loading. Specified values are obtained with minimum cycle time and the output open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range ( C T A 7 C) is ensured. 6. An initial pause of µs is required after power-up followed by eight refresh cycles (-ONLY or CBR) before proper device operation is ensured. The eight cycle wake-ups should be repeated any time the t REF refresh requirement is exceeded. 7. AC characteristics assume t T = 5ns. 8. IH (MIN) and (MA) are reference levels for measuring timing of input signals. Transition times are measured between IH and (or between and IH). 9. In addition to meeting the transition rate specification all input signals must transit between IH and (or between and IH) in a monotonic manner.. If CAS# = IH data output is High-Z.. If CAS# = data output may contain data from the last valid READ cycle. 2. Measured with a load equivalent to two TTL gates pf and OL =.8 and OH = If CAS# is LOW at the falling edge of Q will be maintained from the previous cycle. To initiate a new cycle and clear the Q buffer CAS# must be pulsed HIGH for t CP. 4. The t RCD (MA) limit is no longer specified. t RCD (MA) was specified as a reference point only. If t RCD was greater than the specified t RCD (MA) limit then access time was controlled exclusively by t CAC ( t RAC [MIN] no longer applied). With or without the t RCD limit t AA and t CAC must always be met. 5. The t RAD (MA) limit is no longer specified. t RAD (MA) was specified as a reference point only. If t RAD was greater than the specified t RAD (MA) limit then access time was controlled exclusively by t AA ( t RAC and t CAC no longer applied). With or without the t RAD (MA) limit t AA t RAC and t CAC must always be met. 6. Either t RCH or t RRH must be satisfied for a READ cycle. 7. t OFF (MA) defines the time at which the output achieves the open circuit condition; it is not a reference to OH or OL. 8. t WCS t RWD t AWD and t CWD are restrictive operating parameters in LATE WRITE and READ- MODIFY-WRITE cycles only. If t WCS t WCS (MIN) the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If t RWD t RWD (MIN) t AWD t AWD (MIN) and t CWD t CWD (MIN) the cycle is a READ WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met the state of Q (at access time and until CAS# or OE# goes back to IH) is indeterminate. OE# held HIGH and taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. 9. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 2. During a READ cycle if OE# is LOW then taken HIGH before CAS# goes HIGH Q goes open. If OE# is tied permanently LOW LATE WRITE and READ- MODIFY-WRITE operations are not permissible and should not be attempted. 2. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case = LOW and OE# = HIGH. 22. All other inputs at.2 or CC Column address changed once each cycle. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both t OD and t OEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after t OEH is met. If CAS# goes HIGH prior to OE# going back LOW the DQs will remain open. 25. The DQs open during READ cycles once t OD or t OFF occur. 26. The 3ns minimum is a parameter guaranteed by design. 27. The first CASx edge to transition LOW. 28. The last CASx edge to transition HIGH. 29. Output parameter (DQx) is referenced to corresponding CAS# input; DQ-DQ8 by CASL# and DQ9-DQ6 by CASH#. 3. Last falling CASx edge to first rising CASx edge. 3. Last rising CASx edge to next cycle s last rising CASx edge. 32. Last rising CASx edge to first falling CASx edge. 33. First DQs controlled by the first CASx to go LOW. 34. Last DQs controlled by the last CASx to go HIGH. 35. Each CASx must meet minimum pulse width. 36. Last CASx to go LOW. 37. All DQs controlled regardless CASL# and CASH#. Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

11 TECHNOLOGY I. MEG x 6 READ CYCLE t RC t RAS t RP IH t CSH t RSH t RRH t CRP t RCD t CAS t CLCH CASL#/CASH# IH ADDR IH IH t ASR t AR t RAD t RAH t ASC tcah t RCS t RCH t AA t RAC t CAC t OFF t CLZ DQ OE# IOH IOL IH toe ALID tod DON T CARE UNDEFINED TIMING PARAMETERS t AA 3 35 ns t AR ns t ASC ns t ASR ns t CAC 5 2 ns t CAH 2 ns t CAS 5 2 ns t CLCH ns t CLZ 3 3 ns t CRP 5 5 ns t CSH 6 7 ns t OD ns t OE 5 2 ns t OFF ns t RAC 6 7 ns t RAD 5 5 ns t RAH ns t RAS 6 7 ns t RC 3 ns t RCD 2 2 ns t RCH ns t RCS ns t RP 4 5 ns t RRH ns t RSH 5 2 ns Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

12 TECHNOLOGY I. MEG x 6 EARLY WRITE CYCLE t RC t RAS trp IH t CSH t RSH t CRP t RCD t CAS t CLCH CASL#/CASH# IH t AR t RAD ADDR IH t CWL ALID t ASR t RAH t ASC t CAH t RWL DQ OE# IH IOH IOL IH t WCS t DS t WCR t WCH t WP t DH DON T CARE UNDEFINED TIMING PARAMETERS t AR ns t ASC ns t ASR ns t CAH 2 ns t CAS 5 2 ns t CLCH ns t CRP 5 5 ns t CSH 6 7 ns t CWL 5 2 ns t DH 2 ns t DS ns t RAD 5 5 ns t RAH ns t RAS 6 7 ns t RC 3 ns t RCD 2 2 ns t RP 4 5 ns t RSH 5 2 ns t RWL 5 2 ns t WCH 2 ns t WCR ns t WCS ns t WP 5 ns 2 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

13 TECHNOLOGY I. MEG x 6 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RWC t RAS trp IH t CSH t RSH t CRP t RCD t CAS t CLCH CASL#/CASH# ADDR IH IH IH t ASR t AR t RAD t RAH t ASC t RCS t CAH t RWD t CWD t AWD t CWL t RWL t WP t AA t RAC t CAC DQ OE# IOH IOL IH t OE ALID D OUT t OD ALID D IN t OEH UNDEFINED DON T CARE t CLZ t DS t DH TIMING PARAMETERS t AA 3 35 ns t AR ns t ASC ns t ASR ns t AWD 55 6 ns t CAC 5 2 ns t CAH 2 ns t CAS 5 2 ns t CLCH ns t CLZ 3 3 ns t CRP 5 5 ns t CSH 6 7 ns t CWD 4 45 ns t CWL 5 2 ns t DH 2 ns t DS ns t OD ns t OE 5 2 ns t OEH 5 2 ns t RAC 6 7 ns t RAD 5 5 ns t RAH ns t RAS 6 7 ns t RCD 2 2 ns t RCS ns t RP 4 5 ns t RSH 5 2 ns t RWC 55 8 ns t RWD ns t RWL 5 2 ns t WP 5 ns 3 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

14 TECHNOLOGY I. MEG x 6 FAST-PAGE-MODE READ CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD t CAS t CLCH t CP t CAS t CLCH t CP t CAS t CLCH t CP CASL#/CASH# IH t AR ADDR IH IH t ASR t RAD t RAH t ASC t CAH t ASC t CAH t RCS t RCS t RRH t RCS t RCH t RCH t RCH t AA t AA t ASC t CAH t AA t RAC t CPA t CPA DQ OE# IOH IOL ALID ALID IH ALID t OE t OD t OE t OD t OE t OD UNDEFINED DON T CARE t CAC t OFF t CAC t OFF t CAC t OFF t CLZ t CLZ t CLZ TIMING PARAMETERS t AA 3 35 ns t AR ns t ASC ns t ASR ns t CAC 5 2 ns t CAH 2 ns t CAS 5 2 ns t CLCH ns t CLZ 3 3 ns t CP ns t CPA 35 4 ns t CRP 5 5 ns t CSH 6 7 ns t OD ns t OE 5 2 ns t OFF ns t PC 35 4 ns t RAC 6 7 ns t RAD 5 5 ns t RAH ns t RASP ns t RCD 2 2 ns t RCH ns t RCS ns t RP 4 5 ns t RRH ns t RSH 5 2 ns 4 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

15 TECHNOLOGY I. MEG x 6 FAST-PAGE-MODE EARLY-WRITE CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD t CAS t CLCH t CP t CAS t CLCH t CP t CAS t CLCH t CP CASL#/CASH# ADDR DQ IH IH IH IOH IOL IH t ASR OE# t RAH t RAD UNDEFINED t AR t WCS t ASC t CAH t CWL t WCH t WP t ASC t WCS t CWL t WCH t WCS t WCR t RWL t DS t DH t DS t DH t DS t DH t CAH ALID ALID ALID t WP t ASC t CAH t CWL t WCH t WP DON T CARE TIMING PARAMETERS t AR ns t ASC ns t ASR ns t CAH 2 ns t CAS 5 2 ns t CLCH ns t CP ns t CRP 5 5 ns t CSH 6 7 ns t CWL 5 2 ns t DH 2 ns t DS ns t PC 35 4 ns t RAD 5 5 ns t RAH ns t RASP ns t RCD 2 2 ns t RP 4 5 ns t RSH 5 2 ns t RWL 5 2 ns t WCH 2 ns t WCR ns t WCS ns t WP 5 ns 5 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

16 TECHNOLOGY I. MEG x 6 FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RASP t RP IH t CRP t CSH NOTE t PC t PRWC t RCD t CAS t CLCH t CP t CAS t CLCH t RSH t CP t CAS t CLCH t CP CASL#/CASH# IH t AR ADDR IH t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH t RWD t RCS t CWL t CWL t RWL t CWL IH t AA t WP t AWD t CWD t AA t WP t AWD t CWD t AA t AWD t CWD t WP t RAC t DH t DS t CPA t DH t DS t CPA t DS t DH t CAC t CAC t CAC t CLZ t CLZ t CLZ DQ OE# IOH IOL IH t OE ALID D OUT ALID D IN t OD t OE ALID D OUT ALID D IN t OD t OE ALID D OUT ALID D IN t OD OEH DON T CARE UNDEFINED TIMING PARAMETERS t AA 3 35 ns t AR ns t ASC ns t ASR ns t AWD 55 6 ns t CAC 5 2 ns t CAH 2 ns t CAS 5 2 ns t CLCH ns t CLZ 3 3 ns t CP ns t CPA 35 4 ns t CRP 5 5 ns t CSH 6 7 ns t CWD 4 45 ns t CWL 5 2 ns t DH 2 ns t DS ns t OD ns t OE 5 2 ns t OEH 5 2 ns t PC 35 4 ns t PRWC ns t RAC 6 7 ns t RAD 5 5 ns t RAH ns t RASP ns t RCD 2 2 ns t RCS ns t RP 4 5 ns t RSH 5 2 ns t RWD ns t RWL 5 2 ns t WP 5 ns NOTE:. t PC is for LATE WRITE only. 6 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

17 TECHNOLOGY I. MEG x 6 FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP t RP IH t RSH t CSH t PC t CRP t RCD t CAS t CP t CAS t CP CASL#/CASH# IH t AR ADDR IH t ASR t RAH t ASC t CAH t ASC t CAH t CWL t RAD Q IH OH OL t CAC t CLZ ALID ALID t WCS NOTE t OFF t DS t WP t DH t WCH t RCS t RWL OE# IH trac t AA DON T CARE UNDEFINED TIMING PARAMETERS t AA 3 35 ns t AR ns t ASC ns t ASR ns t CAC 5 2 ns t CAH 2 ns t CAS 5 2 ns t CLZ 3 3 ns t CP ns t CRP 5 5 ns t CSH 6 7 ns t CWL 5 2 ns t DH 2 ns t DS ns t OFF ns t PC 35 4 ns t RAC 6 7 ns t RAD 5 5 ns t RAH ns t RASP ns t RCD 2 2 ns t RCS ns t RP 4 5 ns t RSH 5 2 ns t RWL 5 2 ns t WCH 2 ns t WCS ns t WP 5 ns NOTE:. t PC is for LATE WRITE only. 7 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

18 TECHNOLOGY I. MEG x 6 -ONLY REFRESH CYCLE (OE# and = DON T CARE) t RC t RAS t RP IH t CRP t RPC CASL#/CASH# ADDR IH IH t ASR t RAH Q OH OL CBR REFRESH CYCLE (Addresses and OE# = DON T CARE) t RP t RAS t RP t RAS IH t RPC t CP t CSR t CHR t RPC t CSR tchr CASL#/CASH# IH DQ OH OL IH t WRP t WRH t WRP t WRH DON T CARE UNDEFINED TIMING PARAMETERS t ASR ns t CHR 5 ns t CP ns t CRP 5 5 ns t CSR 5 5 ns t RAH ns t RAS 6 7 ns t RC 3 ns t RP 4 5 ns t RPC ns t WRH ns t WRP ns 8 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

19 TECHNOLOGY I. MEG x 6 HIDDEN REFRESH CYCLE 2 ( = HIGH; OE# = LOW) t RAS t RP t RAS IH t CRP t RCD t RSH t CHR CASL#/CASH# ADDR IH IH t ASR t AR t RAH t RAD t ASC t CAH t AA t RAC t CAC t CLZ t OFF DQx IOH IOL OE# IH t OE t ORD ALID t OD DON T CARE UNDEFINED TIMING PARAMETERS t AA 3 35 ns t AR ns t ASC ns t ASR ns t CAC 5 2 ns t CAH 2 ns t CHR 5 ns t CLZ 3 3 ns t CRP 5 5 ns t OD ns t OE 5 2 ns t OFF ns t ORD ns t RAC 6 7 ns t RAD 5 5 ns t RAH ns t RAS 6 7 ns t RCD 2 2 ns t RP 4 5 ns t RSH 5 2 ns 9 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

20 TECHNOLOGY I. MEG x 6 SELF REFRESH CYCLE (Addresses and OE# = DON T CARE) CAS# DQ IH IH OH OL IH t RP t RPC t CP t RASS t t CHD CSR ( ) ( ) ( ( ) ) t WRP t WRH ( ( ) ) ( ( t RPC ( ( ) ) ) ) t CP ( ( ) ) ( ) ( ) ( ) ( ) NOTE t RPS t WRP t WRH NOTE 2 DON'T CARE UNDEFINED TIMING PARAMETERS t CHD 5 5 ns t CLCH ns t CP ns t CSR 5 5 ns t RASS µs t RP 4 5 ns t RPC ns t RPS 3 ns t WRH ns t WRP ns NOTE:. Once t RASS (MIN) is met and remains LOW the DRAM will enter Self Refresh mode. 2. Once t RPS is satisfied a complete burst of all rows should be executed. 2 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

21 TECHNOLOGY I. MEG x 6 42-PIN PLASTIC SOJ (4 mil) DA-7.79 (27.4).73 (27.25).45 (.29).399 (.3).445 (.3).435 (.5) PIN # INDE.5 (.27) TYP. (25.4).32 (.8).26 (.66).48 (3.76).38 (3.5).5 (2.67).9 (2.29) SEATING PLANE.37 (.94) MA DAMBAR PROTRUSION.2 (.5).5 (.38).38 (9.65).36 (9.4).3 (.76) MIN NOTE:. All dimensions in inches (millimeters) MA or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is." per side. 2 Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.

22 TECHNOLOGY I. MEG x 6 44/5-PIN PLASTIC TSOP (4 mil) DB (2.4).822 (2.88).29 (.75) TYP SEE DETA A.42 (.2).398 (.).467 (.86).459 (.66) PIN # INDE.35 (.8) TYP.8 (.45).2 (.3).7 (.8).5 (.3).47 (.2) MA.4 (.) SEATING PLANE.6 (.5).2 (.5) DETA A.32 (.8) TYP. (.25).24 (.6).6 (.4) NOTE:. All dimensions in inches (millimeters) MA or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is." per side. 8 S. Federal Way P.O. Box 6 Boise ID Tel: Micron DataFax: prodmktg@micron.com Internet: Customer Comment Line: Meg x 6 Micron Technology Inc. reserves the right to change products or specifications without notice. D5.pm5 Rev. 3/ Micron Technology Inc.