EM48AM3284LBB. Revision History. Revision 0.1 (May. 2010) - First release.

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1 Revision History Revision 0.1 (May. 2010) - First release. Revision 0.2 (Sep. 2010) - Delete CL=2 parameters - Input Leakage Current = -2μA ~ +2μA - Change Supply Voltage Rating = -0.5 ~ Delete Deep Power Down Mode - Change AC timing paramters: trc & tis Revision 0.3 () - Change clock input capacitance value 1/22

2 512Mb (4M 4Bank 32) Mobile Synchronous DRAM Features Fully Synchronous to Positive Clock Edge VDD= 1.7V~1.95V for 133MHz & 166MHz Power Supply LVCMOS Compatible with Multiplexed Address Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page Programmable CAS Latency (C/L) - 3 Data Mask (DQM) for Read / Write Masking Programmable Wrap Sequence Sequential (B/L = 1/2/4/8/full Page) Interleave (B/L = 1/2/4/8) Burst Read with Single-bit Write Operation Special Function Support. PASR (Partial Array Self Refresh) Auto TCSR (Temperature Compensated Self Refresh) Programmable Driver Strength Control Full Strength or 1/2, 1/4 of Full Strength Auto Refresh and Self Refresh 8,192 Refresh Cycles / 64ms (7.8us) Description The is Mobile Synchronous Dynamic Random Access Memory (SDRAM) organized as 4Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 512Mb Mobile SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS. Available packages: 90Ball-FBGA (8mmx13mm) Ordering Information Part No -75F -75FE -6F -6FE Package Size Package Type (8x13)mm BGA-90B 16M X 32 Organize Max. Freq Grade Pb Commercial Extend temp. Commercial Extend temp. Free 2/22

3 Parts Naming Rule EOREX reserves the right to change products or specification without notice. 3/22

4 Pin Assignment DQ26 DQ24 VSS A VDD DQ23 DQ21 DQ28 VDDQ VSSQ B VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 C DQ22 DQ20 VDDQ VSSQ DQ29 DQ30 D DQ17 DQ18 VDDQ VDDQ DQ31 NC E NC DQ16 VSSQ VSS DQM3 A3 F A2 DQM2 VDD A4 A5 A6 G A10 A0 A1 A7 A8 A12 H NC BA1 A11 CLK CKE A9 J BA0 /CS /RAS DQM1 NC NC K /CAS /WE DQM0 VDDQ DQ8 VSS L VDD DQ7 VSSQ VSSQ DQ10 DQ9 M DQ6 DQ5 VDDQ VSSQ DQ12 DQ14 N DQ1 DQ3 VDDQ DQ11 VDDQ VSSQ P VDDQ VSSQ DQ4 DQ13 DQ15 VSS R VDD DQ0 DQ2 90ball FBGA / (8mm x 13mm) 4/22

5 Pin Description (Simplified) Pin Name Function J1 J8 J2 G8,G9,F7,F3,G1, G2,G3,H1,H2,J3, G7,H9,H3 J7,H8 J9 K7 K8 K9,K1,F8,F2 R8,N7,R9,N8,P9, M8,M7,L8,L2,M3, M2,P1,N2,R1,N3, R2,E8,D7,D8,B9, C8,A9,C7,A8,A2, C3,A1,C2,B1,D2, D3,E2 A7,F9,L7,R7/ A3,F1,L3,R3 B2,B7,C9,D9,E1, L1,M9,N9,P2/B8, B3,C1,D1,E9,L9, M1,N1,P8 E3,E7,H7,K2, K3 CLK /CS CKE A0~A12 BA0,BA1 /RAS /CAS /WE DQM0~DQM3 DQ0~DQ31 V DD /V SS V DDQ /V SSQ NC (System Clock) Master clock input (Active on the positive rising edge) (Chip Select) Selects chip when active (Clock Enable) Activates the CLK when H and deactivates when L. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. (Address) Row address (A0 to A12) is determined by A0 to A12 level at the bank active command cycle CLK rising edge. CA (CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the pre-charge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS L. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output Mask) DQM controls I/O buffers. (Data Input/Output) DQ pins have the same function as I/O pins on a conventional DRAM. (Power Supply/Ground) V DD and V SS are power supply pins for internal circuits. (Power Supply/Ground) V DDQ and V SSQ are power supply pins for the output buffers. (No Connection) This pin is recommended to be left No Connection on the device. 5/22

6 Absolute Maximum Rating Symbol Item Rating Units V IN, V OUT Input, Output Voltage -0.5 ~ +2.3 V V DD, V DDQ Power Supply Voltage -0.5 ~ +2.3 V T OP Operating Temperature Range Commercial 0 ~ +70 Extended -25 ~ +85 C T STG Storage Temperature Range -55 ~ +125 C P D Power Dissipation 1 W I OS Short Circuit Current 50 ma Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (V CC =1.7V~1.95V, f=1mhz, T A =25 C) Symbol Parameter Min. Typ. Max. Units C CLK Clock Capacitance pf C I Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU pf C O Input/Output Capacitance pf Recommended DC Operating Conditions (T A =-25 C ~85 C) Symbol Parameter Min. Typ. Max. Units V DD Power Supply Voltage Note V V DDQ Power Supply Voltage (for I/O Buffer) V V IH Input Logic High Voltage 0.8*V DDQ V DDQ +0.3 V V IL Input Logic Low Voltage V Note: * All voltages referred to V SS. 6/22

7 Recommended DC Operating Conditions (V DD =1.7~1.95V, T A =-25 C ~85 Cfor extended) Symbol Parameter Test Conditions Speed -6 Speed -7.5 I CC1 Operating Current t RC t RC (min.), I OL =0mA, ma (Note 1) Burst length=1, One bank active I CC2P Precharge Standby Current in CKE V IL (max.), t CK =15ns 1 1 ma Power Down Mode CKE V IL (max.), t CK = 1 1 ma I CC2PS I CC2N I CC2NS Precharge Standby Current in Non-power Down Mode CKE V IL (min.), t CK =15ns, /CS V IH (min.) Input signals are changed one time during 30ns CKE V IL (min.), t CK =, Input signals are stable Units 5 5 ma 2 2 ma I CC3P Active Standby Current in Power CKE V IL (max.), t CK =15ns 3 3 ma Down Mode CKE V IL (max.), t CK = 3 3 ma I CC3PS I CC3N I CC3NS I CC4 Active Standby Current in Non-power Down Mode CKE V IL (min.), t CK =15ns, /CS V IH (min.) Input signals are changed one time during 30ns CKE V IL (min.), t CK =, Input signals are stable ma ma Operating Current (Burst Mode) (Note 2) t CCD 2CLKs, I OL =0mA ma I CC5 Refresh Current (Note 3) t RC t RC (min.) ma I CC6 Slef Refresh Current CKE 0.2, Full Array, Internal TCSR = 85 C *All voltages referenced to V SS. Note 1: I CC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during t CK (min.) Note 2: I CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during t CK (min.) Note 3: Input signals are changed only one time during t CK (min.) ma Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions Min. Typ. Max. Units 0 V I IL Input Leakage Current I V DDQ, V DDQ =V DD ua All other pins not under test=0v I OL Output Leakage Current 0 V O V DDQ, D OUT is disabled ua V OH High Level Output Voltage I O =-0.1mA V DDQ -0.2 V V OL Low Level Output Voltage I O =+0.1mA 0.2 V 7/22

8 Block Diagram Auto/Self Refresh Counter A0 A1 A2 DQM A3 A4 A5 A6 Memory Array Write DQM Control A7 A8 A9 A10 S/A & I/O Gating Data In DOi A11 A12 Col. Decoder Data Out BA0 BA1 Col. Add. Buffer Read DQM Control Mode Register Set Col. Add. Counter Burst Counter Timing Register CLK CKE /CS /RAS /CAS /WE DQM 8/22

9 AC Operating Test Conditions (V DD =1.7~1.95V, T A =-25 C ~85 C) Item Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level Conditions 0.5*VDDQ See diagram as below 0.9*VDDQ/0.2 1ns/1ns 0.5*VDDQ AC Operating Test Characteristics (V DD =1.7~1.95V, T A =-25 C ~85 C for extended) Symbol Parameter Min. Max. Min. Max. Units t CK Clock Cycle Time CL= ns t AC Access Time form CLK CL= ns t CH CLK High Level Width ns t CL CLK Low Level Width ns t OH Data-out Hold Time CL= ns t HZ Data-out High Impedance CL= ns t LZ Data-out Low Impedance Time 1 1 ns t IH Input Hold Time 1 1 ns t IS Input Setup Time ns * All voltages referenced to V SS. Note 5: t HZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 9/22

10 AC Operating Test Characteristics (Continued) (V DD =1.7~1.95V, T A =-25 C ~85 C for extended) Symbol Parameter Units Min. Max. Min. Max. ACTIVE to ACTIVE Command t RC Period (Note 6) ns t RAS t RP t RCD t RRD t CCD t DPL ACTIVE to PRECHARGE Command Period (Note 6) k k ns PRECHARGE to ACTIVE Command Period (Note 6) ns ACTIVE to READ/WRITE Delay Time (Note 6) ns ACTIVE(one) to ACTIVE(another) Command (Note 6) ns READ/WRITE Command to READ/WRITE Command Date-in to PRECHARGE Command 1 1 CLK 2 2 CLK t BDL Date-in to BURST Stop Command 1 1 CLK Data-out to High t ROH Impedance from PRECHARGE Command CL=3 3 3 CLK t REF Refresh Time (8,192 cycle) Ms t DAL Data-in to ACTIVE command ns * All voltages referenced to V SS. Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole number) Recommended Power On and Initialization The following power on and initialization sequence guarantees the device is preconditioned to each user s specific needs. (Like a conventional DRAM) During power on, all V DD and V DDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the NOP state. The power on voltage must not exceed V DD +0.3V on any of the input pins or V DD supplies. (CLK signal started at same time) After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done before or after programming the Mode Register. 10/22

11 Simplified State Diagram SELF SELF Exit CKE CKE BST Read Write with Read with PRE PRE 11/22

12 Address Input for Mode Register Set BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Operation Mode CAS Latency BT Burst Length Burst Length Sequential Interleave A2 A1 A Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Burst Type A3 Interleave 1 Sequential 0 CAS Latency A6 A5 A4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved BA1 BA0 A12 A11 A10 A9 A8 A7 Operation Mode Normal Burst Read with Single-bit Write 12/22

13 Burst Type (A3) Burst Length A2 A1 A0 Sequential Addressing Interleave Addressing X X X X X X X X Full Page* n n n Cn Cn+1 Cn+2 - * Page length is a function of I/O organization and column addressing 32 (CA0 ~ CA8): Full page = 512bits 13/22

14 Extended Mode Register Set ( EMRS ) The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A DS 0 0 PASR Self Refresh Coverage A2 A1 A0 All Banks Two Banks (BA1=0) One Bank (BA0=BA1=0) Reserved Reserved Reserved Reserved Reserved Driver Strength A6 A5 full 0 0 1/2 Strength 0 1 1/4 Strength 1 0 Reserved 1 1 BA1 MRS 0 Normal 1 EMRS 14/22

15 Output Drive Strength The normal drive strength got all outputs is specified to be LV-CMOS. By setting EMRS specific parameter on A6 and A5, driving capability of data output drivers is selected. Partial Array Self Refresh In EMRS setting A0~A2, memory array size to be refreshed during self-refresh operation is programmable in order to reduce power. Data outside the defined area will not be retained during self-refresh. Auto Temperature Compensated Self Refresh (ATCSR) In EMRS setting A9=0, With the built-in temperature sensor, the internal self refresh frequency is controlled autonomously.. 15/22

16 1. Command Truth Table Command Symbol CKE BA0, A11, /CS /RAS /CAS /WE A10 n-1 n BA1 A9~A10 Ignore Command DESL H X H X X X X X X No Operation NOP H X L H H H X X X Burst Stop BSTH H X L H H L X X X Read READ H X L H L H V L V Read with Auto Pre-charge READA H X L H L H V H V Write WRIT H X L H L L V L V Write with Auto Pre-charge WRITA H X L L H H V H V Bank Activate ACT H X L L H H V V V Pre-charge Select Bank PRE H X L L H L V L X Pre-charge All Banks PALL H X L L H L X H X Mode Register Set MRS H X L L L L L L V H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 16/22

17 2. DQM Truth Table Command Symbol CKE n-1 n /CS Data Write/Output Enable ENB H X H Data Mask/Output Disable MASK H X L Upper Byte Write Enable/Output Enable BSTH H X L Read READ H X L Read with Auto Pre-charge READA H X L Write WRIT H X L Write with Auto Pre-charge WRITA H X L Bank Activate ACT H X L Pre-charge Select Bank PRE H X L Pre-charge All Banks PALL H X L Mode Register Set MRS H X L H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 3. CKE Truth Table Item Command Symbol CKE n-1 n /CS /RAS /CAS /WE Addr. Activating Clock Suspend Mode Entry H L X X X X X Any Clock Suspend Mode L L X X X X X Clock Suspend Clock Suspend Mode Exit L H X X X X X Idle CBR Refresh Command REF H H L L L H X Idle Self Refresh Entry SELF H L L L L H X L H L H H H X Self Refresh Self Refresh Exit L H H X X X X Idle Power Down Entry H L X X X X X Power Down Power Down Exit L H X X X X X Remark H = High level, L = Low level, X = High or Low level (Don't care) 17/22

18 4. Operative Command Table Current State Idle Row Active Read Write (Note 7) /CS /R /C /W Addr. Command Action H X X X X DESL Nop or power down L H H X X NOP or BST Nop or power down L H L H BA/CA/A10 READ/READA L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT Row activating L L H L BA, A10 PRE/PALL Nop L L L H X REF/SELF Refresh or self refresh (Note 10) (Note 8) (Note 8) L L L L Op-Code MRS Mode register accessing H X X X X DESL Nop L H H X X NOP or BST Nop L H L H BA/CA/A10 READ/READA (Note 11) Begin read: Determine AP L H L L BA/CA/A10 WRIT/WRITA (Note 11) Begin write: Determine AP L L H H BA/RA ACT L L H L BA, A10 PRE/PALL (Note 12) Pre-charge L L L H X REF/SELF (Note 10) L L L L Op-Code MRS H X X X X DESL Continue burst to end Row active L H H H X NOP Continue burst to end Row active L H H L X BST Burst stop Row active L H L H BA/CA/A10 READ/READA Terminate burst, new read: (Note 13) Determine AP L L L L BA/CA/A10 WRIT/WRITA Terminate burst, start write: (Note 13, 14) Determine AP L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Terminate burst, pre-charging (Note 10) L L L H X REF/SELF L L L L Op-Code MRS H X X X X DESL Continue burst to end Write recovering L H H H X NOP Continue burst to end Write recovering L H H L X BST Burst stop Row active L H L H BA/CA/A10 READ/READA Terminate burst, start read: (Note 13, 14) Determine AP 7, 8 L L L L BA/CA/A10 WRIT/WRITA Terminate burst, new write: (Note 13) Determine AP 7 L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Terminate burst, pre-charging (Note 15) L L L H X REF/SELF L L L L Op-Code MRS Remark H = High level, L = Low level, X = High or Low level (Don't care) 18/22

19 4. Operative Command Table (Continued) (Note 7) Current State Read with AP Write with AP Pre-charging /CS /R /C /W Addr. Command Action H X X X X DESL Continue burst to end Pre-charging L H H H X NOP Continue burst to end Pre-charging L H H L X BST L H L H BA/CA/A10 READ/READA L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PALL L L L H X REF/SELF L L L L Op-Code MRS H X X X X DESL Burst to end Write recovering with auto pre-charge L H H H X NOP Continue burst to end Write recovering with auto pre-charge L H H L X BST L H L H BA/CA/A10 READ/READA L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PALL L L L H X REF/SELF L L L L Op-Code MRS H X X X X DESL Nop Enter idle after t RP L H H H X NOP Nop Enter idle after t RP L H H L X BST L H L H BA/CA/A10 READ/READA L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Nop Enter idle after t RP L L L H X REF/SELF L L L L Op-Code MRS H X X X X DESL Nop Enter idle after t RCD L H H H X NOP Nop Enter idle after t RCD L H H L X BST L H L H BA/CA/A10 READ/READA Row L H L L BA/CA/A10 WRIT/WRITA Activating (Note 9, 16) L L H H BA/RA ACT L L H L BA, A10 PRE/PALL L L L H X REF/SELF L L L L Op-Code MRS Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge 19/22

20 4. Operative Command Table (Continued) (Note 7) Current State /CS /R /C /W Addr. Command Action H X X X X DESL Nop Enter row active after t DPL L H H H X NOP Nop Enter row active after t DPL L H H L X BST Nop Enter row active after t DPL L H L H BA/CA/A10 READ/READA Start read, Determine AP Write (Note 14) L H L L BA/CA/A10 WRIT/WRITA New write, Determine AP Recovering L L H H BA/RA ACT L L H L BA, A10 PRE/PALL L L L H X REF/SELF L L L L Op-Code MRS H X X X X DESL Nop Enter pre-charge after t DPL L H H H X NOP Nop Enter pre-charge after t DPL L H H L X BST Nop Enter pre-charge after t DPL Write L H L H BA/CA/A10 READ/READA (Note 9, 14) Recovering L H L L BA/CA/A10 WRIT/WRITA with AP L L H H BA/RA ACT L L H L BA, A10 PRE/PALL L L L H X REF/SELF L L L L Op-Code MRS H X X X X DESL Nop Enter idle after t RC L H H X X NOP/BST Nop Enter idle after t RC Refreshing L H L X X READ/WRIT L L H X X ACT/PRE/PALL L L L X X REF/SELF/MRS H X X X X DESL Nop L H H H X NOP Nop Mode L H H L X BST Register Accessing L H L X X READ/WRIT ACT/PRE/PALL/ L L X X X REF/SELF/MRS Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle. Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode. All input buffers except CKE will be disabled. Note 9: Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode. All input buffers except CKE will be disabled. Note 11: Illegal if t RCD is not satisfied. Note 12: Illegal if t RAS is not satisfied. Note 13: Must satisfy burst interrupt condition. Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 15: Must mask preceding data which don't satisfy t DPL. Note 16: Illegal if t RRD is not satisfied. 20/22

21 5. Command Truth Table for CKE Current State Self Refresh Self Refresh Recovery Power Down Both Banks Idle Row Active Any State Other than Listed above CKE n-1 n /CS /R /C /W Addr. Action H X X X X X X INVALID, CLK(n-1) would exit self refresh L H H X X X X Self refresh recovery L H L H H X X Self refresh recovery L H L H L X X L H L L X X X L L X X X X X Maintain self refresh H H H X X X X Idle after t RC H H L H H X X Idle after t RC H H L H L X X H H L L X X X H L H X X X X H L L H H X X H L L H L X X H L L L X X X H X X X X X X INVALID, CLK(n-1) would exit power down L H X X X X X Exit power down Idle L L X X X X X Maintain power down mode H H H X X X Refer to operations in Operative H H L H X X Command Table H H L L H X H H L L L H X Refresh H H L L L L Op-Code H L H X X X H L L H X X H L L L H X Refer to operations in Operative Command Table (Note 17) H L L L L H X Self refresh H L Refer to operations in Operative L L L L Op-Code Command Table L X X X X X X (Note 17) Power down H X X X X X X Refer to operations in Operative Command Table L X X X X X X (Note 17) Power down H H X X X X Refer to operations in Operative Command Table H L X X X X X Begin clock suspend next cycle (Note 18) L H X X X X X Exit clock suspend next cycle L L X X X X X Maintain clock suspend Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 17: Self refresh can be entered only from the both banks idle state. Power down can be entered only from both banks idle or row active state. Notes 18: Must be legal command as defined in Operative Command Table 21/22

22 Package Description (8mm x 13mm) 90Ball-FBGA Unit: mm A1 A B ± ± 0.05 C D E F G H J K L M N P R 6.5 ± ± ± ± ± ± MAX 0.45 ± MAX 22/22

eorex EM48AM3284LBA Revision History Revision 0.1 (Jul. 2006) - First release. Revision 0.2 (Aug. 2007).. - Add IDD6 PASR Spec.

eorex EM48AM3284LBA Revision History Revision 0.1 (Jul. 2006) - First release. Revision 0.2 (Aug. 2007).. - Add IDD6 PASR Spec. Revision History Revision 0.1 (Jul. 2006) - First release. Revision 0.2 (Aug. 2007).. - Add IDD6 PASR Spec.(page 7) Revision 0.3 (Dec. 2007).. - TRCD: improved from 30ns to 22.5ns - TRC: improved from