36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs

Transcription

1 . Features M x 36 or 2M x 8. On-chip delay-locked loop (DLL) for wide data valid window. Common /O read and write ports. Synchronous pipeline read with late write operation. Double data rate (DDR-) interface for read and write input ports. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks ( and ) for address and control registering at rising edges only. Two input clocks (C and C) for data output control. Two echo clocks (CQ and CQ) that are delivered simultaneously with data. +.8V core power supply and.5,.8v V DDQ, used with.75,.9v V REF. HSTL input and output levels. Registered addresses, write and read controls, byte writes, and data outputs. Full data coherency. Boundary scan using limited set of JTAG 49. functions. Byte write capability. Fine ball grid array (FBGA) package - 5mm x 7mm body size - mm pitch - 65-ball ( x 5) array Programmable impedance output drivers via 5x user-supplied precision resistor. Description The 36Mb S6DDB4M36 and S6DDB42M8 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common /O bus. The rising edge of clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table on p.8 for a description of the basic operations of these DDR- (Burst of 4) CO SRAMs. Read and write addresses are registered on alternating rising edges of the clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the clock: Read and write addresses Address load Read/write enable Byte writes for burst addresses and 3 Data-in for burst addresses and 3 The following are registered on the rising edge of the clock: Byte writes for burst addresses 2 and 4 Data-in for burst addresses 2 and 4 Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle later than the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the clock. Two full clock cycles are required to complete a write operation. During the burst read operation, at the first and third bursts the data-outs are updated from output registers off the second and fourth rising edges of the C clock (starting.5 cycles later). At the second and fourth bursts, the data-outs are updated with the third and fifth rising edges of the corresponding C clock (see page 9). The and clocks are used to time the data-outs whenever the C and C clocks are tied high. Two full clock cycles are required to complete a read operation The device is operated with a single +.8V power supply and is compatible with HSTL /O interfaces. ntegrated Silicon Solution, nc

2 x36 FBGA Pinout (Top View) A CQ V SS /SA* SA R/W BW 2 BW LD SA V SS /SA* CQ B NC DQ27 DQ8 SA BW 3 BW SA NC NC DQ8 C NC NC DQ28 V SS SA SA SA V SS NC DQ7 DQ7 D NC DQ29 DQ9 V SS V SS V SS V SS V SS NC NC DQ6 E NC NC DQ2 V DDQ V SS V SS V SS V DDQ NC DQ5 DQ6 F NC DQ3 DQ2 V DDQ V DD V SS V DD V DDQ NC NC DQ5 G NC DQ3 DQ22 V DDQ V DD V SS V DD V DDQ NC NC DQ4 H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC DQ32 V DDQ V DD V SS V DD V DDQ NC DQ3 DQ4 NC NC DQ23 V DDQ V DD V SS V DD V DDQ NC DQ2 DQ3 L NC DQ33 DQ24 V DDQ V SS V SS V SS V DDQ NC NC DQ2 M NC NC DQ34 V SS V SS V SS V SS V SS NC DQ DQ N NC DQ35 DQ25 V SS SA SA SA V SS NC NC DQ P NC NC DQ26 SA SA C SA SA NC DQ9 DQ R TDO TC SA SA SA C SA SA SA TMS TD The following pins are reserved for higher densities: 2A for 44Mb, A for 72Mb. BW controls writes to DQ DQ8; BW controls writes to DQ9 DQ7; BW 2 controls writes to DQ8 DQ26; BW 3 controls writes to DQ27 DQ35. x8 FBGA Pinout (Top View) A CQ V SS /SA* SA R/W BW NC/SA LD SA SA CQ B NC DQ9 NC SA NC/SA BW SA NC NC DQ8 C NC NC NC V SS SA SA SA V SS NC DQ7 NC D NC NC DQ V SS V SS V SS V SS V SS NC NC NC E NC NC DQ V DDQ V SS V SS V SS V DDQ NC NC DQ6 F NC DQ2 NC V DDQ V DD V SS V DD V DDQ NC NC DQ5 G NC NC DQ3 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ4 NC NC NC DQ4 V DDQ V DD V SS V DD V DDQ NC NC DQ3 L NC DQ5 NC V DDQ V SS V SS V SS V DDQ NC NC DQ2 M NC NC NC V SS V SS V SS V SS V SS NC DQ NC N NC NC DQ6 V SS SA SA SA V SS NC NC NC P NC NC DQ7 SA SA C SA SA NC NC DQ R TDO TC SA SA SA C SA SA SA TMS TD The following pin is reserved for higher densities: 2A for 72Mb, 7A for 44Mb, 5B for 288Mb. BW controls writes to DQ DQ8; BW controls writes to DQ9 DQ7 2 ntegrated Silicon Solution, nc

3 Pin Description Symbol Pin Number Description, 6B, 6A nput clock. C, C 6P, 6R nput clock for output data control. CQ, CQ A, A Output echo clock. Doff H DLL disable when low. SA, SA 6C, 7C Burst count address inputs. SA SA DQ DQ8 DQ9 DQ7 DQ8 DQ26 DQ27 DQ35 DQ DQ8 DQ9 DQ7 9A, 4B, 8B, 5C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R, 7R, 8R, 9R 3A, 9A, 4B, 8B, 5C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R, 7R, 8R, 9R P, M, L,, J, F, E, C, B P, N, M,, J, G, E, D, C 3B, 3D, 3E, 3F, 3G, 3, 3L, 3N, 3P 2B, 3C, 2D, 2F, 2G, 3J, 2L, 3M, 2N P, M, L,, J, F, E, C, B 2B, 3D, 3E, 2F, 3G, 3, 2L, 3N, 3P M x 36 address inputs. 2M x 8 address inputs. M x 36 DQ pins 2M x 8 DQ pins R/W 4A Read/write control. Read when active high. LD 8A Synchronizes load. Loads new address when low. BW, BW, BW 2, BW 3 7B, 7A, 5A,5B M x 36 byte write control, active low. BW, BW 7B, 5A 2M x 8 byte write control, active low. V REF 2H, H nput reference level. V DD 5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5, 7 Power supply. V DDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4,8,4L,8L Output power supply. V SS 2A, A, 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J, 6, 5L, 6L, 7L, 4M, 8M, 4N, 8N Power supply. ZQ H Output driver impedance control. TMS, TD, TC R, R, 2R EEE 49. test inputs (.8V LVTTL levels). TDO R EEE 49. test output (.8V LVTTL level). ntegrated Silicon Solution, nc

4 Block Diagram 36 (or 8) Data Reg 36 (or 8) Address A, A LD R/W BW x 8 (or 9) Add Reg & Burst 8 (or 9) Control 4 (or 2) Control Logic Write/Read Decode Write Driver M x 36 (2M x 8) Memory Array Sense Amps 72 (or 36) Output Reg 72 (or 36) Output Select Output Driver 36 (or 8) DQ (Data-Out & Data-n) CQ, CQ (Echo Clock Out) C C Clock Gen Select Output Control SRAM Features Read Operations The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R/W in active high state at the rising edge of the clock. R/W can be activated every other cycle because two full cycles are required to complete the burst-of-four read in DDR mode. A second set of clocks, C and C, are used to control the timing to the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device. When the C and C clocks are connected high, the and clocks assume the function of those clocks. n this case, the data corresponding to the first address is clocked.5 cycles later by the rising edge of the clock. The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the clock. The third data-out is clocked by the subsequent rising edge of the clock, and the fourth data-out is clocked by the subsequent rising edge of the clock. Whenever LD is low, a new address is registered at the rising edge of the clock. A NOP operation (LD is high) does not terminate the previous read. The output drivers disable automatically to a high state. Write Operations Write operations can also be initiated at every other rising edge of the clock whenever R/W is low. The write address is also registered at that time. When the address needs to change, LD needs to be low simultaneously to be registered by the rising edge of. Again, the write always occurs in bursts of four. 4 ntegrated Silicon Solution, nc

5 The write data is provided in a late write mode; that is, the data-in corresponding to the first address of the burst, is presented cycle later or at the rising edge of the following clock. The data-in corresponding to the second write burst address follows next, registered by the rising edge of. The third data-out is clocked by the subsequent rising edge of the clock, and the fourth data-out is clocked by the subsequent rising edge of the clock. The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array on the third write cycle. A read cycle to the last two write address produces data from the write buffers. The SRAM maintains data coherency. During a write, the byte writes independently control which byte of any of the four burst addresses is written (see X8/X36 Write Truth Tables on page 9 and Timing Reference Diagram for Truth Table on page 8). Whenever a write is disabled (R/W is high at the rising edge of ), data is not written into the memory. RQ Programmable mpedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V SS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. For example, an RQ of 25Ω results in a driver impedance of 5Ω. The allowable range of RQ to guarantee impedance matching is between 75Ω and 35Ω, with the tolerance described in Programmable mpedance Output Driver DC Electrical Characteristics on page 5. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 3 pf. The ZQ pin can also be directly connected to V DDQ to obtain a minimum impedance setting. ZQ must never be connected to V SS. Programmable mpedance and Power-Up Requirements Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable impedances values. The final impedance value is achieved within 24 clock cycles. Clock Consideration This device uses an internal DLL for maximum output data valid window. t can be placed in a stopped-clock mode to minimize power and requires only 24 cycles to restart. No clocks can be issued until V DD reaches its allowable operating range. Single Clock Mode This device can be also operated in single-clock mode. n this case, C and C are both connected high at power-up and must never change. Under this condition, and control the output timings. Either clock pair must have both polarities switching and must never connect to V REF, as they are not differential clocks. ntegrated Silicon Solution, nc

6 Depth Expansion The following figure depicts an implementation of four 2M x 8 DDR- SRAMs with common /Os. n this application example, the second pair of C and C clocks is delayed such that the return data meets the data setup and hold times at the bus master. Application Example 2M x 8 SRAM # ZQ R=25Ω SRAM #4 ZQ R=25Ω Vt R DQ 7 SA LD R/W BW BW C C DQ 7 SA LD R/W BW BW C C Data-n/Data-Out 7 Address 79 LD Vt R R/W BW 7 Memory Controller Return CL Source CL Vt Return CL Source CL Vt R=5Ω Vt=V REF Power-Up and Power-Down Sequences The following sequence is used for power-up:. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state: ) VDD 2) VDDQ 3) VREF 2. Start applying stable clock inputs (,, C, and C). 3. After clock signals have stabilized, change Doff to HGH logic state. 4. Once the Doff is switched to HGH logic state, wait an additional 24 clock cycles to lock the DLL. NOTES:. The power-down sequence must be done in reverse of the power-up sequence. 2. VDDQ can be allowed to exceed VDD by no more than.6v. 3. VREF can be applied concurrently with VDDQ. 6 ntegrated Silicon Solution, nc

7 State Diagram Power Up Load NOP Load Write Load Dcount = 2 Load New Address Dcount = Load Dcount = 2 Load Read Write Load DDR- Read DDR- Write Dcount = Dcount + Dcount = Dcount + Read Dcount = Always Always Write Dcount = ncrement Read Address ncrement Write Address Notes:. nternal burst counter is fixed as four-bit linear; that is, when first address is A+, next internal burst address is A+. 2. Read refers to read active status with R/W = high. 3. Write refers to write active status with R/W = low. 4. Load refers to read new address active status with LD = low. 5. Load is read new address inactive status with LD = high. The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth tables, as it shows the cycle relationship between clocks, address, data-in, data-out, and controls. All read and write commands are issued at the beginning of cycles t and t w, respectively. Linear Burst Sequence Table Burst Sequence Case Case 2 Case 3 Case 4 SA SA SA SA SA SA SA SA First Address Second Address Third Address Fourth Address ntegrated Silicon Solution, nc

8 Timing Reference Diagram for Truth Table Cycle t t+ t+2 t W t W+ Read A NOP Write B Clock t W+2 Clock LD R / W BW,,2,3 Address A B Data-n/Out (DQ) Q A Q A+ Q A+2 Q A+3 D B D B+ D B+2 D B+3 C Clock C Clock CQ Clock CQ Clock Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.) Mode Clock Controls Data Out / Data n LD R/W Q A / D B Q A+ / D B+ Q A+2 / D B+2 Q A+3 / D B+3 Stop Clock Stop X X Previous State Previous State Previous State Previous State No Operation (NOP) L H H H High-Z High-Z High-Z High-Z Read B L H L H Dout at C (t +.5) Dout at C (t + 2) Dout at C (t + 2.5) Dout at C (t + 3) Write A L H L L D B (t W + ) D B (t W +.5) D B (t W + 2) D B (t W + 2.5) Notes:. The internal burst counter is always fixed as two-bit. 2. X = don t care; H = logic ; L = logic. 3. A read operation is started when control signal R/W is active high. 4. A write operation is started when control signal R/W is active low. 5. Before entering into the stop clock, all pending read and write commands must be completed. 6. For timing definitions, refer to the AC Characteristics on page 6. Signals must have AC specifications at timings indicated in parenthesis with respect to switching clocks,, C, and C. 8 ntegrated Silicon Solution, nc

9 X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on page 8. Operation (t W +) (t W +.5) (t W +2) (t W +2.5) BW BW BW 2 BW 3 D B D B+ D B+2 D B+3 Write Byte L H L H H H D-8 (t W +) Write Byte L H H L H H D9-7 (t W +) Write Byte 2 L H H H L H D8-26 (t W +) Write Byte 3 L H H H H L D27-35 (t W +) Write All Bytes L H L L L L D-35 (t W +) Abort Write L H H H H H Don t care Write Byte L H L H H H D-8 (t W +.5) Write Byte L H H L H H D9-7 (t W +.5) Write Byte 2 L H H H L H D8-26 (t W +.5) Write Byte 3 L H H H H L D27-35 (t W +.5) Write All Bytes L H L L L L D-35 (t W +.5) Abort Write L H H H H H Don t care Write Byte L H L H H H D-8 (t W +2) Write Byte L H H L H H D9-7 (t W +2) Write Byte 2 L H H H L H D8-26 (t W +2) Write Byte 3 L H H H H L D27-35 (t W +2) Write All Bytes L H L L L L D-35 (t W +2) Abort Write L H H H H H Don t care Write Byte L H L H H H D-8 (t W +2.5) Write Byte L H H L H H D9-7 (t W +2.5) Write Byte 2 L H H H L H D8-26 (t W +2.5) Write Byte 3 L H H H H L D27-35 (t W +2.5) Write All Bytes L H L L L L D-35 (t W +2.5) Abort Write L H H H H H Don t care Notes;. For all cases, R/W needs to be active low during the rising edge of occurring at time t W 2. For timing definitions refer to the AC Characteristics on page 6. Signals must have AC specifications with respect to switching clocks and. ntegrated Silicon Solution, nc

10 X8 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on page 8. Operation (t W +) (t W +.5) (t W +2) (t W +2.5) BW BW D B D B+ D B+2 D B+3 Write Byte L H L H D-8 (t W +) Write Byte L H H L D9-7 (t W +) Abort Write L H H H Don t care Write Byte L H L H D-8 (t W +.5) Write Byte L H H L D9-7 (t W +.5) Write All Bytes L H L L D-7 (t W +.5) Abort Write L H H H Don t care Write Byte L H L H D-8 (t W +2) Write Byte L H H L D9-7 (t W +2) Write All Bytes L H L L D-7 (t W +2) Abort Write L H H H Don t care Write Byte L H L H D-8 (t W +2.5) Write Byte L H H L D9-7 (t W +2.5) Write All Bytes L H L L D-7 (t W +2.5) Abort Write L H H H Don t care Notes;. For all cases, R/W needs to be active low during the rising edge of occurring at time t W 2. For timing definitions refer to the AC Characteristics on page 6. Signals must have AC specifications with respect to switching clocks and. ntegrated Silicon Solution, nc

11 Absolute Maximum Ratings tem Symbol Rating Units Power supply voltage V DD -.5 to 2.6 V Output power supply voltage V DDQ -.5 to 2.6 V nput voltage V N -.5 to 2.6 V Data out voltage V DOUT -.5 to 2.6 V Operating temperature T A to 7 C Junction temperature T J C Storage temperature T STG -55 to +25 C Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ntegrated Silicon Solution, nc

12 Recommended DC Operating Conditions (T A = to +7 C) Parameter Symbol Minimum Typical Maximum Units Notes Supply voltage V DD.8-5%.8 + 5% V Output driver supply voltage V DDQ.4.9 V nput high voltage V H V REF +. V DDQ +.2 V, 2 nput low voltage V L -.2 V REF -. V, 3 nput reference voltage V REF V, 5 Clocks signal voltage V N - CL -.2 V DDQ +.2 V, 4. All voltages are referenced to V SS. All V DD, V DDQ, and V SS pins must be connected. 2. V H (Max) AC = See vershoot and Undershoot Timings. 3. V L (Min) AC = See vershoot and Undershoot Timings. 4. V N-CL specifies the maximum allowable DC excursions of each clock (,, C, and C). 5. Peak-to-peak AC component superimposed on V REF may not exceed 5% of V REF. vershoot and Undershoot Timings 2% Min Cycle Time V DDQ +.6V V L (Min) AC Undershoot Timing V DDQ GND V H (Max) AC Overshoot Timing GND-.6V 2% Min Cycle Time PBGA Thermal Characteristics tem Symbol Rating Units Thermal resistance junction to ambient (airflow = m/s) RΘJA TBD C/W Thermal resistance junction to case RΘJC TBD C/W Thermal resistance junction to pins RΘJB TBD C/W 2 ntegrated Silicon Solution, nc

13 SS Capacitance (T A = to + 7 o C, V DD =.8V -5%, +5%, f = MHz) Parameter Symbol Test Condition Maximum Units nput capacitance C N V N = V 4 pf Data-in/Out capacitance (DQ DQ35) CDQ V DN = V 4 pf Clocks Capacitance (,, C, C) CCL V CL = V 4 pf DC Electrical Characteristics (T A = to + 7 o C, V DD =.8V -5%, +5%) Parameter Symbol Minimum Maximum Units Notes x36 average power supply operating current ( OUT =, V N = V H or V L ) DD3 DD4 DD ma x8 average power supply operating current ( OUT =, V N = V H or V L ) DD3 DD4 DD ma Power supply standby current (R = V H, W = V H. All other inputs = V H or V H, H = ) SBSS 2 ma nput leakage current, any input (except JTAG) (V N = V SS or V DD ) L ua Output leakage current (V OUT = V SS or V DDQ, Q in High-Z) LO ua Output high level voltage ( OH = -6mA) V OH V DDQ -.4 V DDQ V 2, 3 Output low level voltage ( OL = +6mA) V OL V SS V SS +.4 V 2, 3 JTAG leakage current (V N = V SS or V DD ) LJTAG - + ua 4. OUT = chip output current. 2. Minimum impedance output driver. 3. JEDEC Standard JESD8-6 Class compatible. 4. For JTAG inputs only. 5. Currents are estimates only and need to be verified. ntegrated Silicon Solution, nc

14 Typical AC nput Characteristics tem Symbol Minimum Maximum Notes AC input logic high V H (ac) V REF +.4, 2, 3, 4 AC input logic low V L (ac) V REF -.4, 2, 3, 4 Clock input logic high (,, C, C) V H-CL (ac) V REF +.4, 2, 3 Clock input logic low (,, C, C) V L-CL (ac) V REF -.4, 2, 3. The peak-to-peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF. 2. Performance is a function of V H and V L levels to clock inputs. 3. See the AC nput Definition diagram. 4. See the AC nput Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past VH (AC) and VL (AC) during the input setup and input hold window. VH (AC) and VL (AC) are used for timing purposes only. AC nput Definition V REF V RAL V H (AC) V REF V L (AC) Setup Time Hold Time V -RAL Programmable mpedance Output Driver DC Electrical Characteristics (T A = to +7 C, V DD =.8V -5%, +5%, V DDQ =.5,.8V) Parameter Symbol Minimum Maximum Units Notes Output high level voltage V OH V DDQ / 2 V DDQ V, 3 Output low level voltage V OL V SS V DDQ / 2 V 2, 3 VDDQ. OH = RQ ± V OH = V DDQ / 2 For: 75Ω RQ 35Ω. VDDQ 2. OL = RQ ± V OL = V DDQ / 2 For: 75Ω RQ 35Ω. 3. Parameter tested with RQ = 25Ω and V DDQ =.5V. 4 ntegrated Silicon Solution, nc

15 AC Test Conditions (T A = to +7 C, V DD =.8V -5%, +5%, V DDQ =.5,.8V) Parameter Symbol Conditions Units Notes Output driver supply voltage V DDQ.5,.8 V nput high level V H V REF +.5 V nput Low Level V L V REF -.5 V nput reference voltage V REF.75,.9 V nput rise time T R.35 ns nput fall time T F.35 ns Output timing reference level V REF V Clocks reference level V REF V Output load conditions, 2. See AC Test Loading. 2. Parameter tested with RQ = 25Ω and V DDQ =.5V. AC Test Loading Q 5 Ω 5 Ω.75,.9V 5pF Test Comparator.75,.9V ntegrated Silicon Solution, nc

16 SS AC Characteristics (T A = to + 7 o C, V DD =.8V -5%, +5%) Parameter Symbol 3 (333MHz) Units Notes Min Max Clock Cycle time (,, C, C) t HH ns Clock phase jitter (,, C, C) t C-VAR.2 ns Clock high pulse (,, C, C) t HL.2 ns Clock low pulse (,, C, C) t LH.2 ns Clock to clock ( H > H, C H >C H ) t HH.3 ns Clock to data clock ( H >C H, H >C H ) t HCH..3 ns DLL lock (, C) t C-lock 24 cycle static to DLL reset t C-reset 3 cycle Output Times C, C high to output valid t CHQV.27 ns, 3 C, C high to output hold t CHQX -.27 ns, 3 C, C high to echo clock valid t CHCQV.25 ns 3 C, C high to echo clock hold t CHCQX -.25 ns 3 CQ, CQ high to output valid t CQHQV.27 ns, 3 CQ, CQ high to output hold t CQHQX -.27 ns, 3 C high to output high-z t CHQZ.27 ns, 3 C high to output low-z t CHQX -.27 ns, 3 Setup Times Address valid to, rising edge t AVH.33 ns 2 Control inputs valid to rising edge t VH.33 ns 2 Data-in valid to, rising edge t DVH.3 ns 2 Hold Times rising edge to address hold t HAX.33 ns 2 rising edge to control inputs hold t HX.33 ns 2, rising edge to data-in hold t HDX.3 ns 2. See AC Test Loading on page During normal operation, V H, V L, T RSE, and T FALL of inputs must be within 2% of V H, V L, T RSE, and T FALL of clock. 3. f C, C are tied high, then, become the references for C, C timing parameters. 6 ntegrated Silicon Solution, nc

17 AC Characteristics (T A = to + 7 o C, V DD =.8V -5%, +5%) Parameter Symbol 4 (25MHz) 5 (2MHz) Units Notes Min Max Min Max Clock Cycle time (,, C, C) t HH ns Clock phase jitter (,, C, C) t C-VAR.2.2 ns Clock high pulse (,, C, C) t HL.6 2. ns Clock low pulse (,, C, C) t LH.6 2. ns Clock to clock ( H > H, C H >C H ) t HH ns Clock to data clock ( H >C H, H >C H ) t HCH ns DLL lock (, C) t C-lock cycle static to DLL reset t C-reset 3 3 cycle Output Times C, C high to output valid t CHQV ns, 3 C, C high to output hold t CHQX ns, 3 C, C high to echo clock valid t CHCQV ns 3 C, C high to echo clock hold t CHCQX ns 3 CQ, CQ High to output valid t CQHQV ns, 3 CQ, CQ high to output hold t CQHQX ns, 3 C High to output high-z t CHQZ ns, 3 C High to output low-z t CHQX ns, 3 Setup Times Address valid to, rising edge t AVH.4.5 ns 2 Control inputs valid to rising edge t VH.4.5 ns 2 Data-in valid to, rising edge t DVH.35.4 ns 2 Hold Times rising edge to address hold t HAX.4.5 ns 2 rising edge to Control nputs Hold t HX.4.5 ns 2, rising edge to data-in hold t HDX.35.4 ns 2. See AC Test Loading on page During normal operation, V H, V L, T RSE, and T FALL of inputs must be within 2% of V H, V L, T RSE, and T FALL of clock. 3. f C, C are tied high, then, become the references for C, C timing parameters. ntegrated Silicon Solution, nc

18 Read, Write, and NOP Timing Diagram NOP Read (burst of 4) Read (burst of 4) NOP NOP (Note 3) Write (burst of 4) Read (burst of 4) t HH t HL t LH t HH LD R/W SA DQ t VH t HX t HAX t AVH A A A2 A3 t HDX t DVH Q Q2 Q3 Q4 Q Q2 Q3 Q4 D2 D22 D23 D24 Q3 Q32 Q33 C t HCH t CHQV t CHQX t CHQX C t CHQV t CHQZ CQ t HH t HL t LH t HH t CHCQH CQ t CQHQV t CQHQX t CQHQZ Don t Care Undefined Notes:. Q refers to the output from address A. Q2 refers to the output from the next internal burst address following A. 2. Outputs are disabled (high impedance) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation, however, at high clock frequencies, it might be required to prevent bus contention. 8 ntegrated Silicon Solution, nc

19 EEE 49. TAP and Boundary Scan The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM /Os and printed circuit board traces or other components. There is no multiplexer in the path from /O pins to the RAM core. n conformance with EEE Standard 49., the SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and D register. The TAP controller has a standard 6-state machine that resets internally on power-up. Therefore, a TRST signal is not required. Signal List TC: test clock TMS: test mode select TD: test data-in TDO: test data-out JTAG DC Operating Characteristics (T A = to +7 C) Operates with JEDEC Standard 8-5 (.8V) logic signal levels Parameter Symbol Minimum Typical Maximum Units Notes JTAG input high voltage V H.3 V DD +.3 V JTAG input low voltage V L V JTAG output high level V OH V DD -.4 V DD V, 2 JTAG output low level V OL V SS.4 V, 3. All JTAG inputs and outputs are LVTTL-compatible. 2. OH - 2mA 3. OL + 2mA. JTAG AC Test Conditions (T A = to +7 C, V DD =.8V -5%, +5%) Parameter Symbol Conditions Units nput pulse high level V H.3 V nput pulse low level V L.5 V nput rise time T R. ns nput fall time T F. ns nput and output timing reference level.9 V ntegrated Silicon Solution, nc

20 JTAG AC Characteristics (T A = to +7 C, V DD =.8V -5%, +5%) Parameter Symbol Minimum Maximum Units Notes TC cycle time t THTH 2 ns TC high pulse width t THTL 7 ns TCk low pulse width t TLTH 7 ns TMS setup t MVTH 4 ns TMS hold t THMX 4 ns TD setup t DVTH 4 ns TD hold t THDX 4 ns TC low to valid data t TLOV 7 ns. See AC Test Loading on page 5. JTAG Timing Diagram t THTL t TLTH t THTH TC t THMX TMS t THDX t MVTH TD t DVTH TDO t TLOV 2 ntegrated Silicon Solution, nc

21 Scan Register Definition Register Name Bit Size x8 or x36 nstruction 3 Bypass D 32 Boundary Scan 9 D Register Definition Field Bit Number and Description Part Revision Number (3:29) Part Configuration (28:2) JEDEC Code (:) Start Bit () 2M x 8 defwxtqbs M x 36 defwxtqbs Part Configuration Definition: def = for 36Mb wx = for x36, for x8 t = for DLL, for non-dll q = for QUADB4, for DDR- b = for burst of 4, for burst of 2 s = for separate /, for common /O ntegrated Silicon Solution, nc

22 nstruction Set Code nstruction TDO Output Notes EXTEST Boundary Scan Register 2,6 DCODE 32-bit dentification Register SAMPLE-Z Boundary Scan Register, 2 PRVATE Do not use 5 SAMPLE Boundary Scan Register 4 PRVATE Do not use 5 PRVATE Do not use 5 BYPASS Bypass Register 3. Places Qs in high-z in order to sample all input data, regardless of other SRAM inputs. 2. TD is sampled as an input to the first D register to allow for the serial shift of the external TD data. 3. BYPASS register is initiated to V SS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TD when exiting the shift-dr state. 4. SAMPLE instruction does not place DQs in high-z. 5. This instruction is reserved. nvoking this instruction will cause improper SRAM functionality. 6. This EXTEST is not EEE 49.-compliant. By default, it places Q in high-z. f the internal register on the scan chain is set high, Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update R state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only. List of EEE 49. Standard Violations 7.2..b, e 7.7..a-f...b, e.7..a-d 6...d JTAG Block Diagram TD Bypass Register ( bit) dentification Register (32 bits) TDO nstruction Register (3 bits) Control Signals TMS TC TAP Controller 22 ntegrated Silicon Solution, nc /9/6

23 TAP Controller State Machine Test Logic Reset Run Test dle Select DR Select R Capture DR Shift DR Capture R Shift R Exit DR Exit R Pause DR Pause R Exit2 DR Exit2 R Update DR Update R ntegrated Silicon Solution, nc

24 Boundary Scan Exit Order The same length is used for x8 and x36 /O configuration. Order Pin D Order Pin D Order Pin D 6R 37 D 73 2C 2 6P 37 9E 74 3E 3 6N 39 C 75 2D 4 7P 4 D 76 2E 5 7N 4 9C 77 E 6 7R 42 9D 78 2F 7 8R 43 B 79 3F 8 8P 44 C 8 G 9 9R 45 9B 8 F P 46 B 82 3G P 47 A 83 2G 2 N 48 A 84 H 3 9P 49 9A 85 J 4 M 5 8B 86 2J 5 N 5 7C M 52 6C 88 3J 7 9N 53 8A L 54 7A 9 9 M 55 7B 9 2L 2 9L 56 6B 92 3L 2 L 57 6A 93 M B 94 L A 95 3N 24 9J 6 4A 96 3M C 97 N 26 J 62 4B 98 2M 27 J 63 3A 99 3P 28 H 64 2A 2N 29 G 65 A 2P 3 9G 66 2B 2 P 3 F 67 3B 3 3R 32 G 68 C 4 4R 33 9F 69 B 5 4P 34 F 7 3D 6 5P 35 E 7 3C 7 5N 36 E 72 D 8 5R ) NC pins as defined on FBGA pinouts on page 2 are read as don t cares. 2) State of nternal pin (#9) is loaded via JTAG. 9 nternal 24 ntegrated Silicon Solution, nc

25 x 5 FBGA Dimensions ntegrated Silicon Solution, nc

26 ORDERNG NFORMATON Commercial Range: C to +7 C Speed Order Part No. Organization Package 25 MHz S6DDB4M36-25M3 Mx36 65 BGA S6DDB42M8-25M3 2Mx8 65 BGA S6DDB42M8-25M3L 2Mx8 65 BGA, Lead-free 26 ntegrated Silicon Solution, nc