IBM B IBM P 8M x 8 12/11 EDO DRAM

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1 8M x 812/11, 3.3V, EDO. 8M x 812/11, 3.3V, LP, SR, EDO. Features 8,388,608 word by 8 bit organization Single 3.3 ±0.3V power supply Extended Data Out before Refresh cycles/retention Time only Refresh cycles/retention Time 64ms Standard Power (SP) Retention Time 128ms Low Power (LP) Retention Time Hidden Refresh Self Refresh (400µA) - LP Version Only Description The /P is a dynamic RAM organized 8,388,608 words by 8 bits. This device is fabricated in IBM s most advanced CMOS silicon gate process technology. The circuit and process design allow this DRAM to achieve high performance and low power dissipation. The /P operates with a single 3.3 ±0.3V power supply, and interfaces directly with either TTL or CMOS levels. The 23 addresses required to access any bit of data are Pin Assignments (Top View) V CC I/O0 I/O1 I/O2 I/O3 NC V CC A0 A1 A2 A3 A4 A5 V CC V SS 31 I/O7 30 I/O6 29 I/O5 28 I/O4 27 V SS OE 24 NC 23 A11 22 A10 21 A9 20 A8 19 A7 18 A6 17 V SS Read-Modify-Write Performance: Max. Power Dissipation (-50) - Active: 504mW - Standby (SP version): 2.0 ma - Standby (LP version): 0.2 ma t RAC Access Time 50ns 60ns Access Time 13ns 15ns t AA Column Address Access Time 25ns 30ns t RC Cycle Time 84ns 104ns t HPC Hyper Page Mode Cycle Time 20ns 25ns Package: SOJ-32 (400mil), TSOP-32 (400mil) multiplexed (12 are strobed with, 11 are strobed with ). They are packaged in a 32 pin plastic SOJ (400mil 825mil), and a 32pin plastic TSOP type II (400mil 825mil).The parts are low power devices supporting Self Refresh and a 128ms retention time. Pin Description A0 - A11 OE I/O0 - I/O7 V CC V SS Row Address Strobe Column Address Strobe Read/write Input Address Inputs Output Enable Data Input/output Power (+3.3V) Ground Page 1 of 29

2 Ordering Information Part Number Power Self Refresh Power Supply Speed Package Notes J3D-50 SP No 3.3V 50ns 400mil SOJ 32 1 J3D-60 SP No 3.3V 60ns 400mil SOJ 32 1 T3D-50 SP No 3.3V 50ns 400mil TSOP 32 1 T3D-60 SP No 3.3V 60ns 400mil TSOP 32 1 T3D-50 LP Yes 3.3V 50ns 400mil TSOP 32 1 T3D-60 LP Yes 3.3V 60ns 400mil TSOP SP = Standard Power version (); LP = Low Power version () Block Diagram I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Vcc Vss 8 8 Data In Buffer Data Out Buffer OE & No. 2 Clock Generator 8 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A Column Address Buffer (11) Refresh Controller Refresh Counter (12) Row Address Buffer (12) 12 Row Decoder Column Decoder Sense Amp and I/O Gate 2048x8 Memory Array 4096 x 2048 x 8 8 No. 1 Clock Generator Page 2 of 29

3 Truth Table Function OE Row Address Column Address I/O0 - I/O7 Standby H H X X X X X High Impedance Read L L H L Row Col. Data Out Early-Write L L L X Row Col. Data In Delayed-Write L L H L H Row Col. Data In Read-Modify-Write L L H L L H Row Col. Data Out, Data In EDO (Hyper Page) Mode Read EDO (Hyper Page) Mode Write EDO (Hyper Page) Mode Read-Modify-Write 1st Cycle L H L H L Row Col. Data Out 2nd Cycle L H L H L N/A Col. Data Out 1st Cycle L H L L X Row Col. Data In 2nd Cycle L H L L X N/A Col. Data In 1st Cycle L H L H L L H Row Col. Data Out, Data In 2nd Cycle L H L H L L H N/A Col. Data Out, Data In -Only Refresh L H X X Row N/A High Impedance -Before- Refresh H L L H X X N/A High Impedance Hidden Refresh Read L H L L H L Row Col. Data Out Write L H L L L H X Row Col. Data In Self Refresh (LP version only) H L L H X X X High Impedance Page 3 of 29

4 Absolute Maximum Ratings Symbol Parameter Rating Units Notes V CC Power Supply Voltage -0.5 to 4.6 V 1 V IN Input Voltage -0.5 to min (V CC +0.5, 4.6) V 1 V OUT Output Voltage -0.5 to min (V CC +0.5, 4.6) V 1 T OPR Operating Temperature 0 to +70 C 1 T STG Storage Temperature -55 to +150 C 1 P D Power Dissipation 1.0 W 1 I OUT Short Circuit Output Current 50 ma 1 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (T A =0 to 70 C) Symbol Parameter Min. Typ. Max. Units Notes V CC Supply Voltage V 1 Input High Voltage 2.0 V CC V 1, 2 Input Low Voltage V 1, 2 1. All voltages referenced to V SS. 2. may overshoot to V CC +2.0V for pulse widths of 4.0ns with 3.3 Volt. may undershoot to -2.0V for pulse widths 4.0ns with 3.3 Volt. Pulse widths measured at 50% points with amplitude measured peak to DC reference Capacitance (T A =0 to +70 C, V CC =3.3 ±0.3V, f=1mhz) Symbol Parameter Min. Max. Units Notes C I1 Input Capacitance (A0 - A11) 5 pf C I2 Input Capacitance (,,, OE) 7 pf C I3 Data I/O Capacitance (I/O0 - I/O7) 7 pf Page 4 of 29

5 DC Electrical Characteristics (T A = 0 to +70 C, V CC = 3.3 ±0.3V) Symbol Parameter Min. Max. Units Notes I CC1 I CC2 I CC3 I CC4 I CC5 I CC6 I CC7 I I(L) I O(L) V OH V OL Operating Current Average Power Supply Operating Current (,, Address Cycling: t RC = t RC min) Standby Current (TTL) Power Supply Standby Current ( = = ) Only Refresh Current Average Power Supply Current, Only Mode ( Cycling, = : t RC = t RC min) EDO Mode Current Average Power Supply Current, Hyper Page Mode ( =,, Address Cycling: t PC = t PC min) Standby Current (CMOS) Power Supply Standby Current ( = = V CC - 0.2V) Before Refresh Current Average Power Supply Current, Before Mode (,, Cycling: t RC = t RC min) Self Refresh Current (LP version only) Average Power Supply Current during Self Refresh CBR cycle with t S (min); held low; = V CC - 0.2V; Addresses and D IN = V CC - 0.2V or 0.2V. Input Leakage Current Input Leakage Current, any input (0.0 V IN V CC ), All Other Pins Not Under Test = 0V Output Leakage Current ( is disabled, 0.0 V OUT V CC ) Output High Level (TTL) Output H Level Voltage (I OUT = -2mA) Output Low Level (TTL) Output L Level Voltage (I OUT = +2mA) 1. I CC1, I CC3, I CC4, I CC6 depend on cycle rate. 2. I CC1, I CC4 depend on output loading. Specified values are obtained with the output open. 3. Column address can be changed once or less while = and = ma ma 1, 2, 3 ma 1, ma 1, 2, LP version 200 µa SP version 1 ma µa µa µa 2.4 V 0.4 V ma 1, 2 Page 5 of 29

6 AC Characteristics (T A =0 to +70 C, V CC =3.3 ±0.3V) 1. An initial pause of 100µs is required after power-up followed by 8 only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 before refresh cycles instead of 8 only refresh cycles is required. 2. AC measurements assume t T =2ns. 3. (min.) and (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between and. 4. Valid column addresses are only A0 through A10. Read, Write, Read-Modify-Write and Refresh Cycle (Common Parameters) Symbol Parameter Min. Max. Min. Max. Units Notes t RC Random Read or Write Cycle Time ns 1 Precharge Time ns t CP Precharge Time 8 10 ns t Pulse Width k k ns 1 t Pulse Width 8 100k k ns 1 t ASR Row Address Setup Time 0 0 ns t RAH Row Address Hold Time 7 10 ns t ASC Column Address Setup Time 0 0 ns t CAH Column Address Hold Time 7 10 ns t RCD to Delay Time ns 2 t RAD to Col. Address Delay Time ns 3 t RSH Hold Time 8 10 ns t CSH Hold Time ns 1 to Precharge Time 5 5 ns 1 t DZO OE Delay Time From D IN 0 0 ns 4 t DZC Delay Time From D IN 0 0 ns 4 t T Transition Time (Rise and Fall) ns 5 1. In a Test Mode Read cycle, the value of t RAC, t AA, and t CPA are delayed by 5ns from the specified value. These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must also be adjusted by 5ns. 2. Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference point only. If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled by. 3. Operation within the t RAD (max.) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled by t AA. 4. Either t DZC or t DZO must be satisfied. 5. AC measurements assume t T = 2ns Page 6 of 29

7 Write Cycle Symbol Parameter Min. Max. Min. Max. Units Notes t WCS Write Command Set Up Time 0 0 ns 1 t WCH Write Command Hold Time 7 10 ns t WP Write Command Pulse Width 7 10 ns t RWL Write Command to Lead Time 8 10 ns t CWL Write Command to Lead Time 8 10 ns t OED OE to D IN Delay Time ns 2 t DS D IN Setup Time 0 0 ns 3 t DH D IN Hold Time 7 10 ns 3 1. t WCS, t RWD, t CWD, t AWD and t CPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (min.), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. If t RWD t RWD (min.), t CWD t CWD (min.), t AWD t AWD (min.), and t CPWD t CPWD (min.)(fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 2. Either t CDD or t OED must be satisfied. 3. These parameters are referenced to leading edge in early write cycles and to leading edge in Read-Modify-Write cycles. Page 7 of 29

8 Read Cycle Symbol Parameter Min. Max. Min. Max. t RAC Access Time from ns 1, 2, 3, 5 Access Time from ns 1, 2, 5 t AA Access Time from Address ns 1, 2, 5 t OEA Access Time From OE ns 1, 5 t RCS Read Command Setup Time 0 0 ns t RCH Read Command Hold Time to 0 0 ns 6 t RRH Read Command Hold Time to 0 0 ns t RAL Column Address to Lead Time ns 1 t CLZ to Output in Low-Z 0 0 ns 5 t OEZ Output Buffer Turn-Off Delay From OE ns 7 t CDD to D IN Delay Time ns 4 t OFF Output Buffer Turn-Off Delay ns 7 t OES OE Setup Time Prior to 5 5 ns t ORD OE Setup Time Prior to (Hidden Refresh) 0 0 ns 1. In a Test Mode Read cycle, the value of t RAC, t AA, and t CPA are delayed by 5ns from the specified value. These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must also be adjusted by 5ns. 2. Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference point only. If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled by. 3. Operation within the t RAD (max.) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled by t AA. 4. Either t CDD or t OED must be satisfied. 5. Measured with the specified current load and 100pF. 6. Either t RCH or t RRH must be satisfied for a read cycle. 7. t OFF (max.) and t OEZ (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. Units Notes Page 8 of 29

9 Read-Modify-Write Cycle Symbol Parameter Min. Max. Min. Max. Units Notes t RWC Read-Modify-Write Cycle Time ns t RWD to Delay Time ns 1 t CWD to Delay Time ns 1 t AWD Column Address to Delay Time ns 1 t OEH OE Command Hold Time 7 10 ns 1. t WCS, t RWD, t CWD, t AWD and t CPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (min.), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. If t RWD t RWD (min.), t CWD t CWD (min.), t AWD t AWD (min.), and t CPWD t CPWD (min.)(fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. Extended Data Out (Hyper Page) Mode Cycle Symbol Parameter Min. Max. Min. Max. Units Notes t H Pulse Width (Hyper Page Mode) 8 100K 10 10K ns t HPC Hyper Page Mode Cycle Time (Read/Write) ns t HPRWC Hyper Page Mode Read Modify Write Cycle Time ns t DOH Data-out Hold Time from 5 5 ns t WHZ Output buffer Turn-Off Delay from ns t WPZ Pulse Width to Output Disable at High 7 10 ns t CPRH Hold Time from Precharge ns t CPA Access Time from Precharge ns 1 t P Hyper Page Mode Pulse Width K K ns t OEP OE High Pulse Width 5 10 ns t OEHC OE High Hold Time from High 5 10 ns 1. Measured with the specified current load and 100pF at V OL = 0.8V and V OH = 2.0V. Page 9 of 29

10 Self Refresh Cycle - Low Power Version Only Symbol t S S t CHS Pulse Width During Self Refresh Cycle Precharge Time During Self Refresh Cycle Hold Time During Self Refresh Cycle Parameter Units Notes Min. Max. Min. Max µs ns ns 1 1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed in an EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR- Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. Refresh Cycle Symbol Parameter Min. Max. Min. Max. Units Notes t CSR Setup Time ( before Refresh Cycle) 5 5 ns t CHR Hold Time ( before Refresh Cycle) 5 10 ns t WRP Setup Time ( before Refresh Cycle) 5 10 ns t WRH Hold Time ( before Refresh Cycle) 5 10 ns C Precharge to Hold Time 5 5 ns t REF Refresh Period SP version LP version ms cycles for Only Refresh; 4096 cycles for CBR Refresh. Page 10 of 29

11 Read Cycle t RC t t CSH t RCD t RSH t t RAD t RAL t ASR t RAH t ASC t CAH Address Row Column t RCS t RCH t RRH t AA t OES OE t OEA t DZC t CDD t DZO t OED D IN t CLZ t OEZ t OFF V OH V OL Valid Data Out t RAC : H : or L Page 11 of 29

12 Write Cycle (Early Write) t RC t t RCD t CSH t RSH t t RAD t ASR t ASC t RAH t CAH Address Row Column t WCS t WCH t WP OE t DS t DH D IN Valid Data In V OH V OL : H or L Page 12 of 29

13 Write Cycle (Delayed Write) t RC t t CSH t RCD t RSH t t RAD t ASR t ASC t RAH t CAH Address Row Column t RCS t CWL t WP t RWL OE t OEH t OED t DH t DZO t WRP t DS D IN t DZC Valid Data In t OEZ t CLZ V OH V OL t OEA * : H or L * t OEH greater than or equal to t CWL Page 13 of 29

14 Read-Modify-Write Cycle t RWC t t CSH t RCD t t ASR t ASC t RAH tcah t CWD t RWL t CWL t WP t RCS t OEH t OEA t DZC t DH t DS D IN t CLZ t OED t OEZ Discontinued (12/98 - last order; 3/99 last ship) t RSH t RAD Address Row Column t RWD t AWD t AA OE t DZO D IN V OH V OL * t RAC * t OEH greater than or equal to t CWL : H or L Page 14 of 29

15 EDO (Hyper Page) Mode Read Cycle t P t CPRH t HPC t RCD t CP t CP t RSH t H t H t H t CSH t RAL t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 Column 2 Column N t RAD t RCH t RRH t RCS t WP t OES t CPA t AA t CPA taa t OFF t OEA OE t RAC t AA t DOH t DOH t OEZ t CLZ V OH V OL Data Out 1 Data Out 2 Data Out N : H or L Page 15 of 29

16 EDO (Hyper Page) Mode Read Cycle (OE Control) t P t CPRH t HPC t RCD t CP t CP t RSH t H t H t H t CSH t ASR t RAH t ASC t ASC t CAH t ASC t CAH t CAH t RAL Address Row Column 1 Column 2 Column N t RAD t RCH t RCS t RRH t OES t CPA t CPA t OFF t AA t AA t OEA t OEHC t OES t OEHC t OES OE t OEP t OEP t RAC t AA t OEA t OEA t OEZ t CLZ t OEZ t OEZ V OH V OL Data Out 1 Data Out 2 Data Out N : H or L Page 16 of 29

17 EDO (Hyper Page) Mode Read Cycle ( Control) t P t CPRH t HPC t RCD t CP t CP t RSH t H t H t H t CSH t ASR t RAH t ASC t ASC t ASC t CAH t CAH t CAH t RAL Address Row Column 1 Column 2 Column N t RAD t AA t AA t RCS t RCH t RCS t RCH t RCS t RCH t RRH t WPZ t WPZ t OFF t OES t CPA t CPA OE t OEA t RAC t OEZ t AA t WHZ t WHZ t CLZ V OH V OL Data Out 1 Data Out 2 Data Out N : H or L Page 17 of 29

18 EDO (Hyper Page) Mode Early Write Cycle t P t HPC t RCD t CP t CP t RSH t H t H t H t RAD t CSH t ASR t RAH t CAH t ASC t ASC t RAL t CAH t ASC t CAH Address Row Column 1 Column 2 Column N t CWL t RWL t WCH t WCS t WCS t WCH t WCS t WCH t WP t WP t WP t DS t DH t DS t DH t DS t DH D IN Data In 1 Data In 2 Data In N : H or L OE = Don t care Page 18 of 29

19 EDO (Hyper Page) Mode Late Write Cycle t P t HPC t RCD t CP t CP t RSH t H t H t H t RAD t CSH t RAL t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 Column 2 Column N t CWL t CWL t CWL t RCS t RCS t RCS t RWL t WP t WP t WP t OEH t OEH t OEH OE t OED t DS t DH t OED t DS t DH t OED t DS t DH D IN Data In 1 Data In 2 Data In N : H or L Page 19 of 29

20 EDO (Hyper Page) Mode Read Modify Write Cycle t P t HPRWC t RCD t CP t CP t t t t CSH t ASC t ASC t RAD t RAL t ASR t RAH tcah t ASC t CAH t CAH Address Row Column 1 Column 2 Column N t CWL t CPA t AA t CPA t AA t CWL t RWL t RWD t RCS t AWD t CWD t WP t RCS t AWD t CWD t RCS t WP t AWD t CWD t WP t RAC t AA t OEH t OEH t OEH OE t OEA t OED t OEA t OED t OEA t OED t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ V OH V OL t DS t DS t DS t DH t DH t DH D IN D IN D IN D IN : H or L Page 20 of 29

21 Only Refresh Cycle t RC t C t ASR t RAH Address Row V OH V OL : H or L NOTE:, OE and D IN are H or L Page 21 of 29

22 Before Refresh Cycle t RC t C t CP t CSR t CHR C t WRH t WRP OE t OED t CDD D IN t OEZ t OFF V OH V OL : H or L NOTE: Address is H or L Page 22 of 29

23 Hidden Refresh Cycle (Read) t RC t RC t t t RCD t RSH t CHR t RAD t RAL t WRH t ASR t ASC t WRP t RAH t CAH Address Row Column t RCS t RRH t AA t ORD OE t OEA t DZC t CDD D IN t DZO t OED t CLZ t OEZ t OFF V OH V OL Valid Data Out t RAC : H or L Page 23 of 29

24 Hidden Refresh Cycle (Write) t RC t RC t t t RCD t RSH t CHR t ASR t RAH t ASC t CAH Address Row Column t WRP t WCS t WCH t WRH t WP OE t DS t DH D IN Valid Data V OH V OL : H or L Page 24 of 29

25 Self Refresh Cycle (Sleep Mode) - Low Power version only t S S t RPC t CP t CSR t CHS t WRP t WRH t OFF V OH V OL : H or L NOTE: Address and OE are H or L Once t S (min) is provided and remains low, the DRAM will be in Self Refresh, commonly known as Sleep Mode. Page 25 of 29

26 Package Dimensions (400 mil; 32 lead; Small Outline J-Lead) 3.76 max 20.95± min 0.64 min Lead # ± Basic Lead #1 Identifier Lead # Seating Plane Basic NOTE: All dimensions are in millimeters. Reference JEDEC Standard MS-027 Page 26 of 29

27 Package Dimensions (400mil; 32 lead; Thin Small Outline Package) Lead # ±0.13 Detail A ± ± Lead #1 Identifier Lead #1 Seating Plane Basic Detail A 1.20 MAX 1.00± Basic Gage Plane ±0.1 NOTE: All dimensions are in millimeters. Reference JEDEC Standard MS-024 Page 27 of 29

28 Revision Log Revision 1/2/97 Initial specification release. 03/19/97 Contents of Modification 1. for the Hidden Refresh Write cycle in the Truth Table was changed from H to L H. 2. t OED was moved from the Common Parameters table to the Write Cycle Parameters Table. 3. The note Implementing at time during a Read or Write cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. was removed from all of the Read and Write timing diagrams. 4. t ODD was changed to t OED in notes in the Write Cycle and Read Cycle Parameters tables. 5. Hyper Page Mode was changed to EDO (Hyper Page) Mode in the timing diagram titles. 6. Removed the Test Mode parameters and timing diagrams. 7. LVTTL/LVCMOS changed to TTL/CMOS. 8. LVCMOS currents were removed. 9. Power numbers on the spec cover were recalculated. 11/97 1. Changed RetentionTime from 256ms to 128ms on Low Power DRAMs. Page 28 of 29

29 Discontinued (8/98 - last order; 12/98 last ship) International Business Machines Corp.1997 Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at IBM Microelectronics manufacturing is ISO 9000 compliant.

IBM IBM M IBM B IBM P 4M x 4 11/11 EDO DRAM

IBM IBM M IBM B IBM P 4M x 4 11/11 EDO DRAM IBM01174054M x 411/11, 5.0V, EDOMMDD64DSU-001012331. IBM0117405P4M x 411/11, 3.3V, EDO, LP, SRMMDD64DSU-001012331. IBM0117405M4M x 411/11, 5.0V, EDO, LP, SRMMDD64DSU-001012331. IBM0117405B4M x 411/11,