5V 1M 16 CMOS DRAM (fast-page mode) DQ16 DQ15 DQ14 DQ13 RAS DQ12 DQ11 DQ10 DQ9 OE WE UCAS LCAS LCAS UCAS OE A9 A8 A7 A6 A5 A4

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1 August 2001 AS4C1M16F5 5V 1M 16 CMOS DRAM (fast-page mode) Features Organization: 1,048,576 words 16 bits High speed - 45/50/60 ns access time - 20/20/25 ns fast page cycle time - 10/12/15 ns CAS access time Low power consumption - Active: 880 mw max (AS4C1M16F5-60) - Standby: 11 mw max, CMOS DQ Fast page mode 1024 refresh cycles, 16 ms refresh interval - -only or CAS-before- refresh Read-modify-write TTL-compatible, three-state DQ JEDEC standard package and pinout mil, 42-pin SOJ mil, 44/50-pin TSOP 2 5V power supply Industrial and commercial temperature available Pin arrangement Vcc DQ1 DQ2 DQ3 Vcc DQ5 DQ6 DQ7 DQ8 A0 A1 A2 A3 Vcc SOJ V SS DQ16 DQ15 DQ14 DQ13 V SS DQ12 DQ11 DQ10 DQ9 A9 A8 A7 A6 A5 A4 V SS V CC DQ1 DQ2 DQ 3 DQ4 V CC DQ5 DQ6 DQ7 DQ8 A0 A1 A2 A3 V CC TSOP V SS DQ16 DQ15 DQ14 DQ13 V SS DQ12 DQ11 DQ10 DQ9 A9 A8 A7 A6 A5 A4 V SS Pin designation Pin(s) A0 to A9 DQ1 to DQ16 V CC V SS Description inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Power Ground Selection guide Symbol Unit Maximum access time t RAC ns Maximum column address access time t AA ns Maximum CAS access time ns Maximum output enable () access time t A ns Minimum read or write cycle time ns Minimum fast page mode cycle time t PC ns Maximum operating current I CC ma Maximum CMOS standby current I CC ma 3/22/02; v Alliance Semiconductor P. 1 of 22 Copyright Alliance Semiconductor. All rights reserved.

2 Functional description The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low-power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia and router switch applications. The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page) can be executed at very high speed (15 ns from XCAS) by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of and xcas inputs respectively. Also, is used to make the column address latch transparent, enabling application of column addresses prior to xcas assertion. The AS4C1M16F5 provides dual and for independent byte control of read and write access. Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using: -only refresh: is asserted while xcas is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence. Hidden refresh: xcas is held low while is toggled. Outputs remain low impedence with previous valid data. CAS-before- refresh (CBR): At least one xcas is asserted prior to. Refresh address is generated internally. Outputs are high-impedence ( and are don't care). Normal read or write cycles refresh the row being accessed. The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP 2 packages, respectively. It operates with a single power supply of 5V ± 0.5V. The device provides TTL compatible inputs and outputs. Logic block diagram V CC GND Refresh controller Column decoder Sense amp Data DQ buffers DQ1 to DQ16 clock generator CAS clock generator clock generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 buffers Row decoder Array (16,777,216) Substrate bias generator Recommended operating conditions Parameter Symbol Min Nominal Max Unit Supply voltage Input voltage Ambient operating temperature VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified. V CC V GND V V IH 2.4 V CC V V IL V Commercial 0 70 T A Industrial /22/02; v Alliance Semiconductor P. 2 of 22 C

3 Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage V in V Input voltage (DQs) V DQ -1.0 V CC V Power supply voltage V CC V Storage temperature (plastic) T STG C Soldering temperature time T SOLDER o C sec Power dissipation P D 1 W Short circuit output current I out 50 ma es Operation t R t C DQ0 to DQ15 Standby H H to X H to X X X X X High-Z Word read L L L H L ROW COL Data out Lower byte read Upper byte read Word (early) write Lower byte (early) write Upper byte (early) write L L H H L ROW COL L H L H L ROW COL Lower byte, Upper byte, Data out Lower byte, Data out, Upper byte L L L L X ROW COL Data in L L H L X ROW COL L H L L X ROW COL Lower byte, Data in, Upper byte, High-Z Lower byte, High-Z, Upper byte, Data in Read write L L L H to L L to H ROW COL Data out, Data in 1st cycle L H to L H to L H L ROW COL Data out EDO read 2nd cycle L H to L H to L H L n/a COL Data out Any cycle L L to H L to H H L n/a n/a Data out 1st cycle L H to L H to L L X ROW COL Data in EDO write 2nd cycle L H to L H to L L X n/a COL Data in EDO 1st cycle L H to L H to L H to L L to H ROW COL Data out, Data in read write 2nd cycle L H to L H to L H to L L to H n/a COL Data out, Data in only refresh L H H X X ROW n/a High Z CBR refresh H to L L L H X X X High Z Notes 3/22/02; v Alliance Semiconductor P. 3 of 22

4 DC electrical characteristics Parameter Symbol Test conditions 0V V Input leakage current I in V CC (max) IL Pins not under test = 0V Min Max Min Max Min Max Unit µa Notes Output leakage current I OL D OUT disabled, 0V V out V CC (max) Operating power supply current TTL standby power supply current Average power supply current, refresh mode or CBR EDO page mode average power supply current CMOS standby power supply current Output voltage CAS before refresh current I CC1,,, cycling; =min µa ma 1,2 I CC2 = = V IH, all other inputs at V IH or V IL ma cycling, = V IH, I CC3 = min of low after XCAS low. I CC4 I CC5 = V IL, or, address cycling: t HPC = min = = = V CC - 0.2V, F = ma ma 1, ma V OH I OUT = -5.0 ma V V OL I OUT = 4.2 ma V I CC6, or cycling, = min ma 3/22/02; v Alliance Semiconductor P. 4 of 22

5 AC parameters common to all waveforms Symbol Parameter Min Max Min Max Min Max Unit Notes Random read or write cycle time ns precharge time ns t pulse width 45 10K 50 10K 60 10K ns CAS pulse width 8 10K 8 10K 10 10K ns D to CAS delay time ns 6 to column address delay time ns 7 CAS to hold time ns to CAS hold time ns CAS to precharge time ns Row address setup time ns Row address hold time ns t T Transition time (rise and fall) ns 4,5 t REF Refresh period ms 3 t CP CAS precharge time ns Column address to lead time ns Column address setup time ns Column address hold time ns Read cycle Symbol Parameter Min Max Min Max Min Max Unit Notes t RAC Access time from ns 6 Access time from CAS ns 6,13 t AA Access time from address ns 7,13 S Read command setup time ns H Read command hold time to CAS ns 9 t RRH Read command hold time to ns 9 3/22/02; v Alliance Semiconductor P. 5 of 22

6 Write cycle Symbol Parameter Min Max Min Max Min Max Unit Notes t WCS Write command setup time ns 11 t WCH Write command hold time ns 11 Write command pulse width ns Write command to lead time ns Write command to CAS lead time ns Data-in setup time ns 12 Data-in hold time ns 12 Read-modify-write cycle Refresh cycle Symbol Parameter Min Max Min Max Min Max Unit Notes t RWC Read-write cycle time ns t RWD to delay time ns 11 t CWD CAS to delay time ns 11 t AWD Column address to delay time ns Symbol Parameter Min Max Min Max Min Max Unit Notes t CSR CAS setup time (CAS-before-) ns 3 t CHR CAS hold time (CAS-before-) ns 3 C precharge to CAS hold time ns t CPT CAS precharge time (CBR counter test) ns 3/22/02; v Alliance Semiconductor P. 6 of 22

7 Fast page mode cycle Symbol Parameter Min Max Min Max Min Max Unit Notes t CPA Access time from CAS precharge ns 13 t P pulse width K K K ns t PC Read-write cycle time ns t CP CAS precharge time (fast page) ns t PCM Fast page mode RMW cycle ns t CRW Page mode CAS pulse width (RMW) ns Output enable Symbol Parameter Min Max Min Max Min Max Unit Notes CAS to output in Low Z ns 8 t ROH hold time referenced to ns t A access time ns t D to data delay ns t Z Output buffer turnoff delay from ns 8 t H command hold time ns t OLZ to output in Low Z ns t OFF Output buffer turn-off time ns 8, 10 3/22/02; v Alliance Semiconductor P. 7 of 22

8 Notes 1 I CC1, I CC3, and I CC4 are dependent on frequency. 2 I CC1 and I CC4 depend on output loading. Specified values are obtained with the output open. 3 An initial pause of 200 µs is required after power-up followed by any 8 cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before- initialization cycles instead of 8 cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). 4 AC Characteristics assume t T = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pf, V IL (min) GND and V IH (max) V CC. 5 V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH and V IL. 6 Operation within the D (max) limit insures that t RAC (max) can be met. D (max) is specified as a reference point only. If D is greater than the specified D (max) limit, then access time is controlled exclusively by. 7 Operation within the (max) limit insures that t RAC (max) can be met. (max) is specified as a reference point only. If is greater than the specified (max) limit, then access time is controlled exclusively by t AA. 8 Assumes three state test load (5 pf and a 380 Ω Thevenin equivalent). 9 Either H or t RRH must be satisfied for a read cycle. 10 t OFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t OFF is referenced from rising edge of or CAS, whichever occurs last. 11 t WCS, t WCH, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t WS t WS (min) and t WH t WH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t RWD t RWD (min), t CWD t CWD (min) and t AWD t AWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12 These parameters are referenced to CAS leading edge in early write cycles and to leading edge in read-write cycles. 13 Access time is determined by the longest of t CAA or or t CPA 14 t CP to achieve t PC (min) and t CPA (max) values. 15 These parameters are sampled and not 100% tested. 16 These characteristics apply to AS4C1M16F5 5V devices. AC test conditions - Access times are measured with output reference levels of V OH = 2.4V and V OL = 0.4V, V IH = 2.4V and V IL = 0.8V - Input rise and fall times: 2 ns +5V R1 = 828Ω D out 100 pf* R2 = 295Ω GND Figure A: Equivalent output load *including scope and jig capacitance Key to switching waveforms Rising input Falling input Undefined output/don t care 3/22/02; v Alliance Semiconductor P. 8 of 22

9 Read waveform t D, S Row address Column address t RRH t ROH t ROH H t Z t RAC t Z t AA t t OFF (see note 11) A t REZ DQ t OLZ Data out Upper byte read waveform t D trsh Row S Column t ROH C H t RRH t Z t RAC t AA t OLZ t A t Z t REZ Upper DQ Lower DQ t OFF Data out 3/22/02; v Alliance Semiconductor P. 9 of 22

10 Lower byte read waveform t D Upper DQ Lower DQ Row S t RAC Column t AA t OLZ t ROH t A t Z Data out t REZ H t RRH t OFF Early write waveform t, D Row address Column address t WCS t WCH DQ Data in 3/22/02; v Alliance Semiconductor P. 10 of 22

11 Upper byte early write waveform Upper DQ Lower DQ Row address D t WCS t Column address Data in t WCH tdh C Lower byte early write waveform t Upper DQ Row address D Column address t WCS t WCH t WP C Lower DQ Data in 3/22/02; v Alliance Semiconductor P. 11 of 22

12 Write waveform controlled t, D Row address Column address DQ t D Data in tdh t H Upper byte write waveform controlled t Row address Column address D C t H Upper DQ Lower DQ t D Data in 3/22/02; v Alliance Semiconductor P. 12 of 22

13 Lower byte write waveform controlled t Row address Column address D t ACS C Upper DQ Lower DQ Data in t H Read-modify-write waveform t t RWC D, t AR Row address Column address t RWD t AWD DQ S t A t RAC t AA t OLZ t CWD t D t Z Data out Data in 3/22/02; v Alliance Semiconductor P. 13 of 22

14 Upper byte read-modify-write waveform t t RWC Upper input Upper output Lower input Lower output D Row S t RAC t AA t ACS Column address t RWD t OLZ Data out t AWD t D t CWD t A Data in t Z t D C Lower byte read-modify-write waveform Upper input Upper output Lower input Lower output Row t C t AWD t RCS t CWD t A t t OLZ D t RWC D t RAC t ACS Column address t RWD t AA t D t Z Data out Data in 3/22/02; v Alliance Semiconductor P. 14 of 22

15 Fast page mode read waveform t P CAS D t CP t PC t AR I/O Row tcah t RAC Column Column Column S t H t RRH RCS H t A t AA t Z t OFF t CAP t A Data out Data out Data out Fast page mode byte write waveform CAS I/O t RCS t CAH t P D t CP trah Row Column Column Column t A t PCM t RWD t CWD t CWD t CWD t AWD t AWD t Z t RAC t AA t CAP Data in Data out t D Data in Data out t A Data out Data in 3/22/02; v Alliance Semiconductor P. 15 of 22

16 Fast page mode early write waveform t P CAS D t PC t WCS t CP t AR Row Column Column Column t WCH t H I/O t HDR t D Data In Data in Data in CAS before refresh waveform = V IH t C t CHR, t CP t CSR DQ OPEN only refresh waveform = = V IH or V IL t, C Row address 3/22/02; v Alliance Semiconductor P. 16 of 22

17 Hidden refresh waveform (read) t t CAS t CHR D t AR Row Col address S t RRH t A t RAC t OFF t AA DQ Data out t Z Hidden refresh waveform (write) t D, t AR Row address Col address t WCR t CHR t WCS t WCH DQ R Data in 3/22/02; v Alliance Semiconductor P. 17 of 22

18 t AS4C1M16F5 CAS before refresh counter test waveform, t CSR t CHR t CPT Col address t AA t Z t OFF DQ Data out Read cycle S t RRH H t ROH t A Write cycle DQ t WCS Data in S t WCH t CWD t AWD Read-Write cycle t A t AA t D t Z DQ Data out Data in 3/22/02; v Alliance Semiconductor P. 18 of 22

19 Package dimensions SOJ Seating Plane 42-pin SOJ 400 mil Min Max A A A B b c D E NOM E E e NOM TSOP E H e d A A 2 A b e c l 50-pin TSOP 2 Min (mm) Max (mm) A 1.2 A A b c d E H e e 0.80 (typical) l /22/02; v Alliance Semiconductor P. 19 of 22

20 Typical DC and AC characteristics 1.5 Normalized access time t RAC vs. supply voltage V CC 1.5 Normalized access time t RAC vs. ambient temperature T a 100 Typical access time t RAC vs. load capacitance C L Normalized access time T a = 25 C Normalized access time Typical access time Supply voltage (V) Ambient temperature ( C) Load capacitance (pf) 170 Typical supply current I CC vs. supply voltage V CC 170 Typical supply current I CC vs. ambient temperature T a 35 Typical power-on current I PO vs. cycle rate 1/ Supply current (ma) Supply current (ma) Power-on current (ma) Supply voltage (V) Ambient temperature ( C) Cycle rate (MHz) 160 Typical refresh current I CC3 vs. supply voltage V CC 160 Typical refresh current I CC3 vs. Ambient temperature Ta 3.5 Typical TTL stand-by current I CC2 vs. supply voltage V CC Refresh current (ma) Refresh current (ma) Stand-by current (ma) Supply voltage (V) Ambient temperature ( C) Supply voltage (V) 3/22/02; v Alliance Semiconductor P. 20 of 22

21 3.5 Typical TTL stand-by current I CC2 vs. ambient temperature T a 70 Typical output sink current I OL vs. output voltage V OL 70 Typical output source current I OH vs. output voltage V OH Stand-by current (ma) Output sink current (ma) Output source current (ma) Ambient temperature ( C) Output voltage (V) Output voltage (V) Hyper page mode current (ma) Typical hyper page mode current I CC4 vs. ambient temperature T a Ambient temperature ( C) Hyper page mode current (ma) Typical hyper page mode current I CC4 vs. supply voltage V CC Supply voltage (V) Capacitance 15 ƒ = 1 MHz, T a = Room temperature Parameter Symbol Signals Test conditions Max Unit C IN1 A0 to A9 V in = 0V 5 pf Input capacitance C IN2,,,, V in = 0V 7 pf DQ capacitance C DQ DQ0 to DQ15 V in = V out = 0V 7 pf 3/22/02; v Alliance Semiconductor P. 21 of 22

22 Ordering information Package \ access time 45 ns 50 ns 60 ns Plastic SOJ, 400 mil, 42-pin TSOP 2, 400 mil, 44/50-pin Part numbering system AS4C1M16F5-45JC AS4C1M16F5-45TC AS4C1M16F5-50JC AS4C1M16F5-50JI AS4C1M16F5-50TC AS4C1M16F5-50TI AS4C1M16F5-60JC AS4C1M16F5-60JI AS4C1M16F5-60TC AS4C1M16F5-60TI AS4 C 1M16F5 XX X X DRAM prefix C = 5V CMOS Device number access time Package: J = 42-pin SOJ 400 mil T=44/50-pin TSOP mil Temperature range C=Commercial, 0 C to 70 C I=Industrial, -40 C to 85 C 3/22/02; v Alliance Semiconductor P. 22 of 22 Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

3.3 V 256 K 16 CMOS SRAM

August 2004 AS7C34098A 3.3 V 256 K 16 CMOS SRAM Features Pin compatible with AS7C34098 Industrial and commercial temperature Organization: 262,144 words 16 bits Center power and ground pins High speed