VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NC NC NC WE# RAS# NC NC A0 A1 A2 A3

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1 OBSOLETE MT4CM6E5 Meg x 6, 5 MT4LCM6E5 Meg x 6, 3.3 For the latest data sheet, please refer to the Micron Web site: FEATURES JEDEC- and industry-standard x6 timing, functions, pinouts, and packages High-performance CMOS silicon-gate process Single power supply (+3.3 ±.3 or 5 ±%) All inputs, outputs and clocks are TTL-compatible Refresh modes: -ONLY, CAS#-BEFORE- (CBR), HIDDEN; optional self refresh (S) BYTE WRITE access cycles,24-cycle refresh ( row, column addresses) Extended Data-Out (EDO) PAGE MODE access 5-tolerant inputs and I/Os on 3.3 devices OPTIONS KEY TIMING PARAMETERS MARKING oltages 3.3 LC 5 C Refresh Addressing,24 (K) rows E5 Packages Plastic SOJ (4 mil) DJ Plastic TSOP (4 mil) TG Timing 5ns access -5 6ns access -6 Refresh Rates Standard Refresh (6ms period) None Self Refresh (28ms period) S 2 Operating Temperature Range Commercial ( o C to +7 o C) Extended (-2 o C to +8 o C) NOTE: Part Number Example: MT4LCM6E5TG-6 None ET. The third field distinguishes the low voltage offering: LC designates cc = 3.3 and C designates cc = Available only on MT4LCM6E5 (3.3) SPEED t RC t RAC t PC t AA t CAC t CAS -5 84ns 5ns 2ns 25ns 5ns 8ns -6 4ns 6ns 25ns 3ns 7ns ns CC DQ DQ DQ2 DQ3 CC DQ4 DQ5 DQ6 DQ7 NC NC NC NC NC A A A2 A3 CC PIN ASSIGNMENT (Top iew) 44/5-Pin TSOP SS DQ5 DQ4 DQ3 DQ2 SS DQ DQ DQ9 DQ8 NC NC CASL# CASH# A9 A8 A7 A6 A5 A4 SS 42-Pin SOJ NOTE: The "#" symbol indicates signal is active LOW. MEG x 6 PART NUMBERS PART NUMBER cc REFRESH PACKAGE REFRESH MT4LCM6E5DJ-x 3.3 K 4-SOJ Standard MT4LCM6E5DJ-x S 3.3 K 4-SOJ Self MT4LCM6E5TG-x 3.3 K 4-TSOP Standard MT4LCM6E5TG-x S 3.3 K 4-TSOP Self MT4CM6E5DJ-x 5 K 4-SOJ Standard MT4CM6E5TG-x 5 K 4-TSOP Standard NOTE: -x indicates speed grade marking under timing options. CC DQ DQ DQ2 DQ3 CC DQ4 DQ5 DQ6 DQ7 NC NC NC NC A A A2 A3 CC SS DQ5 DQ4 DQ3 DQ2 SS DQ DQ DQ9 DQ8 NC CASL# CASH# A9 A8 A7 A6 A5 A4 SS GENERAL DESCRIPTION The Meg x 6 is a randomly accessed, solid-state memory containing 6,777,26 bits organized in a x6 configuration. The Meg x 6 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function like a single CAS# found on other DRAMs in that either CASL# or CASH# will generate an internal CAS#. The CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and the last CAS# to transition back HIGH. Using only one Meg x 6 D52_B.p65 Rev. B; Pub. 3/ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2, Micron Technology, Inc

2 GENERAL DESCRIPTION (continued) of the two signals results in a BYTE WRITE cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ5). Each bit is uniquely addressed through the 2 address bits during READ or WRITE cycles. These are entered bits (A-A9) at a time. is used to latch the first bits and CAS#, the latter bits. The CAS# function also determines whether the cycle will be a refresh cycle ( ONLY) or an active cycle (READ, WRITE or READ-WRITE) once goes LOW. The CASL# and CASH# inputs internally generate a CAS# signal that functions like the single CAS# input on other DRAMs. The key difference is each CAS# input (CASL# and CASH#) controls its corresponding eight DQ inputs during WRITE accesses. CASL# controls DQ-DQ7, and CASH# controls DQ8-DQ5. The two CAS# controls give the Meg x 6 both BYTE READ and BYTE WRITE cycle capabilities. A logic HIGH on dictates read mode, while a logic LOW on dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READ-MODIFY- WRITE occurs when WE falls after CAS# (CASL# or CASH#) was taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of. During LATE WRITE or READ- MODIFY-WRITE cycles, must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location. The 6 data inputs and 6 data outputs are routed through 6 pins using common I/O. Pin direction is controlled by and. The Meg x 6 DRAM must be refreshed periodically in order to retain stored data. IH IH ADDR IH COLUMN (A) COLUMN (B) COLUMN (C) COLUMN (D) DQ IOH IOL ALID DATA (A) t OD ALID DATA (A) ALID DATA (B) t OD ALID DATA (C) t OD ALID DATA (D) t OES t OEHC IH t OE t OEP The DQs go back to Low-Z if t OES is met. The DQs remain High-Z until the next CAS# cycle if t OEHC is met. The DQs remain High-Z until the next CAS# cycle if t OEP is met. DON T CARE Figure Control of DQs 2 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

3 PAGE ACCESS Page operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a rowaddress-defined page boundary. The page cycle is always initiated with a row address strobed in by, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding LOW, thus executing faster memory cycles. Returning HIGH terminates the page mode of operation, i.e., closes the page. EDO PAGE MODE The Meg x 6 provides EDO PAGE MODE, which is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# returns HIGH. EDO provides for CAS# precharge time ( ) to occur without the output data going invalid. This elimination of CAS# output control provides for pipelined READs. FAST-PAGE-MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO-PAGE-MODE DRAMs operate like FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, provided and are held LOW. If is pulsed while and CAS# are LOW, data will toggle from valid data to High-Z and back to the same valid data. If is toggled or pulsed after CAS# goes HIGH while remains LOW, data will transition to and remain High-Z (refer to Figure ). can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 2. During an application, if the DQ outputs are wire OR d, must be used to disable idle banks of DRAMs. Alternatively, pulsing to the idle banks during CAS# HIGH time will also High-Z the outputs. Independent of control, the outputs will disable after t OFF, which is referenced from the rising edge of or CAS#, whichever occurs last. BYTE ACCESS CYCLE The BYTE WRITEs and BYTE READs are determined by the use of CASL# and CASH#. Enabling CASL# selects a lower BYTE access (DQ-DQ7). Enabling CASH# selects an upper BYTE access (DQ8-DQ5). Enabling both CASL# and CASH# selects a WORD WRITE cycle. The Meg x 6 may be viewed as two Meg x 8 DRAMs that have common input controls, with the exception of the CAS# inputs. Figure 3 illustrates the BYTE WRITE and WORD WRITE cycles. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. IH IH ADDR IH COLUMN (A) COLUMN (B) COLUMN (C) COLUMN (D) DQ IOH IOL ALID DATA (A) ALID DATA (B) INPUT DATA (C) t WHZ t WHZ IH t WPZ IH The DQs go to High-Z if falls, and if t WPZ is met, will remain High-Z until CAS# goes LOW with HIGH (i.e., until a READ cycle is initiated). may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with HIGH (i.e., until a READ cycle is initiated). DON T CARE Figure 2 Control of DQs 3 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

4 However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. DRAM REFRESH Preserve correct memory cell data by maintaining power and executing any cycle (READ, WRITE) or REFRESH cycle (-ONLY, CBR or HIDDEN) so that all,24 combinations of addresses are executed within t REF (MA), regardless of sequence. The CBR, ETENDED and SELF REFRESH cycles will invoke the internal refresh counter for automatic addressing. An optional self refresh mode is available on the S version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding LOW for the specified t RASS. The S option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 28ms, or 25µs per row, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving HIGH for a minimum time of t RPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the LOW-to- HIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a -ONLY or burst refresh sequence, all,24 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation. STANDBY Returning and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the HIGH time. WORD WRITE LOWER BYTE WRITE CASL# CASH# LOWER BYTE (DQ-DQ7) OF WORD STORED DATA INPUT DATA INPUT DATA STORED DATA STORED DATA INPUT DATA INPUT DATA STORED DATA UPPER BYTE (DQ8-DQ5) OF WORD ADDRESS ADDRESS = NOT EFFECTIE (DON'T CARE) Figure 3 WORD and BYTE WRITE Example 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

5 FUNCTIONAL BLOCK DIAGRAM CASL# CASH# CAS# DATA-IN BUFFER DQ NO. 2 CLOCK GENERATOR 6 DQ5 A A A2 A3 A4 A5 A6 A7 A8 A9 COLUMN- ADDRESS BUFFER REFRESH CONTROLLER REFRESH COUNTER - ADDRESS BUFFERS () DECODER,24 COLUMN DECODER,24 SENSE AMPLIFIERS I/O GATING,24 x 6 6,24 x,24 x 6 MEMORY ARRAY DATA-OUT BUFFER 6 NO. CLOCK GENERATOR DD SS 5 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

6 ABSOLUTE MAIMUM RATINGS* oltage on CC Pin Relative to SS to to +7 oltage on NC, Inputs or I/O Pins Relative to ss: to to +7 Operating Temperature T A (commercial)... ºC to +7ºC T A (extended)... -2ºC to +8ºC Storage Temperature (plastic) ºC to +5ºC Power Dissipation... W Short Circuit Output Current... 5mA *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: ; notes appear on pages -) PARAMETER/CONDITION SYMBOL MIN MA MIN MA UNITS NOTES SUPPLY OLTAGE CC INPUT HIGH OLTAGE: alid Logic ; All inputs, I/Os and any NC IH CC + INPUT LOW OLTAGE: alid Logic ; All inputs, I/Os and any NC INPUT LEAKAGE CURRENT: Any input at IN ( IN IH[MA]); II µa 4 All other pins not under test = OUTPUT HIGH OLTAGE: IOUT = -2mA(3.3), -5mA(5) OH OUTPUT LOW OLTAGE: IOUT = 2mA(3.3), 4.2mA(5) OL.4.4 OUTPUT LEAKAGE CURRENT: Any output at OUT ( OUT 5.5); IOZ µa DQ is disabled and in High-Z state 6 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

7 ICC OPERATING CONDITIONS AND MAIMUM LIMITS (Notes:, 2, 3, 5, 8; notes appear on pages -); (CC[MIN] CC CC[MA]) PARAMETER/CONDITION SYMBOL SPEED UNITS NOTES STANDBY CURRENT: TTL ICC ALL 2 ma ( = CAS# = IH) STANDBY CURRENT: CMOS (non- S version only) ICC2 ALL 5 5 µa ( = CAS# = other inputs = DD -.2) STANDBY CURRENT: CMOS ( S version only) ICC2 ALL 5 5 µa ( = CAS# = other inputs = DD -.2) OPERATING CURRENT: Random READ/WRITE ICC ma 6 Average power supply current (, CAS#, address cycling: t RC = t RC [MIN]) OPERATING CURRENT: EDO PAGE MODE ICC ma 6 Average power supply current ( =, CAS#, address cycling: t PC = t PC [MIN]) REFRESH CURRENT: -ONLY ICC ma Average power supply current ( cycling, CAS# = IH: t RC = t RC [MIN]) REFRESH CURRENT: CBR ICC ma 7, 9 Average power supply current (, CAS#, address cycling: t RC = t RC [MIN]) REFRESH CURRENT: Extended ( S version only) ICC7 ALL 3 3 µa 7, 9 Average power supply current: CAS# =.2 or CBR cycling; = t RAS (MIN); = DD -.2; A-A, and DIN = DD -.2 or.2 (DIN may be left open); t RC = 25µs REFRESH CURRENT: Self ( S version only) ICC8 ALL 3 3 µa 7, 9 Average power supply current: CBR with t RASS (MIN) and CAS# held LOW; = DD -.2; A-A, and DIN = DD -.2 or.2 (DIN may be left open) 7 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

8 CAPACITANCE (Notes:, 2, 3, 5, 8; notes appear on pages -) PARAMETER SYMBOL MA UNITS NOTES Input Capacitance: Addresses CI 5 pf Input Capacitance:, CASL#,CASH#,, CI2 7 pf Input/Output Capacitance: DQ CIO 7 pf AC ELECTRICAL CHARACTERISTICS (Notes: 2, 3, 9,,, 2; notes appear on pages -); (CC[MIN] CC CC[MA]) AC CHARACTERISTICS PARAMETER SYMBOL MIN MA MIN MA UNITS NOTES Access time from column address t AA 25 3 ns Column-address setup to CAS# precharge t ACH 2 5 ns Column-address hold time (referenced to ) t AR ns Column-address setup time ns 25 Row-address setup time t ASR ns 25 Column address to delay time t AWD ns 3 Access time from CAS# t CAC 3 5 ns 4, 25 Column-address hold time t CAH 8 ns 25 CAS# pulse width t CAS 8,, ns 27 CAS# LOW to Don t Care during Self Refresh t CHD 5 5 ns CAS# hold time (CBR Refresh) t CHR 8 ns 7, 26 Last CAS# going LOW to first CAS# to return HIGH t CLCH 5 5 ns 28 CAS# to output in Low-Z t CLZ ns 26 Data output hold after next CAS# LOW t COH 3 3 ns CAS# precharge time 8 ns 5, 3 Access time from CAS# precharge A ns 26 CAS# to precharge time t CRP 5 5 ns 26 CAS# hold time t CSH ns 26 CAS# setup time (CBR Refresh) t CSR 5 5 ns 7, 25 CAS# to delay time t CWD ns 3, 25 WRITE command to CAS# lead time t CWL 8 ns 26 Data-in hold time t DH 8 ns 6, 25 Data-in setup time t DS ns 6, 25 Output disable t OD 2 5 ns Output enable t OE 2 5 ns 7 hold time from during t OEH 8 ns 8 READ-MODIFY-WRITE cycle HIGH hold from CAS# HIGH t OEHC 5 ns 8 HIGH pulse width t OEP 5 5 ns LOW to CAS# HIGH setup time t OES 4 5 ns Output buffer turn-off delay t OFF 2 5 ns 2, 26 8 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

9 AC ELECTRICAL CHARACTERISTICS (continued) (Notes: 2, 3, 9,,, 2; notes appear on pages -); (CC[MIN] CC CC[MA]) AC CHARACTERISTICS PARAMETER SYMBOL MIN MA MIN MA UNITS NOTES setup prior to t ORD ns during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time t PC 2 25 ns 3 EDO-PAGE-MODE READ-WRITE cycle time t PRWC ns 3 Access time from t RAC 5 6 ns 9 to column-address delay time t RAD 9 2 ns 2 Row address hold time t RAH 9 ns pulse width t RAS 5, 6, ns pulse width (EDO PAGE MODE) t RASP 5 25, 6 25, ns pulse width during Self Refresh t RASS µs Random READ or WRITE cycle time t RC 84 4 ns to CAS# delay time t RCD 4 ns 22, 25 READ command hold time (referenced to CAS#) t RCH ns 23, 27 READ command setup time t RCS ns 25 Refresh period (,24 cycles) t REF 6 6 ms Refresh period (,24 cycles) S version t REF ms precharge time t RP 3 4 ns to CAS# precharge time t RPC 5 5 ns precharge time exiting Self Refresh t RPS 9 5 ns READ command hold time (referenced to ) t RRH ns 23 hold time t RSH 3 5 ns 32 READ-WRITE cycle time t RWC 6 4 ns to delay time t RWD ns 3 WRITE command to lead time t RWL 3 5 ns Transition time (rise or fall) t T ns WRITE command hold time t WCH 8 ns 32 WRITE command hold time (referenced to ) t WCR ns command setup time t WCS ns 3, 25 Output disable delay from t WHZ 2 5 ns WRITE command pulse width t WP 5 5 ns pulse to disable at CAS# HIGH t WPZ ns hold time (CBR Refresh) t WRH 8 ns setup time (CBR Refresh) t WRP 8 ns 9 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

10 NOTES. All voltages referenced to SS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (ºC T A 7ºC for commercial) and (-2ºC T A 8ºC for extended) is ensured. 3. An initial pause of µs is required after powerup, followed by eight refresh cycles (- ONLY or CBR with HIGH), before proper device operation is ensured. The eight cycle wake-ups should be repeated any time the t REF refresh requirement is exceeded. 4. NC pins are assumed to be left floating and are not tested for leakage. 5. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. Column address changed once each cycle. 7. Enables on-chip refresh and address counters. 8. This parameter is sampled. DD = +3.3; f = MHz. 9. AC characteristics assume t T = 2.5ns..IH (MIN) and (MA) are reference levels for measuring timing of input signals. Transition times are measured between IH and (or between and IH)..In addition to meeting the transition rate specification, all input signals must transit between IH and (or between and IH) in a monotonic manner. 2.Measured with a load equivalent to two TTL gates and pf; and OL =.8 and OH = t WCS, t RWD, t AWD, and t CWD are not restrictive operating parameters. t WCS applies to EARLY WRITE cycles. t RWD, t AWD and t CWD apply to READ-MODIFY-WRITE cycles. If t WCS t WCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If t WCS < t WCS (MIN) and t RWD t RWD (MIN), t AWD t AWD (MIN) and t CWD t CWD (MIN), the cycle is a READ- MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. held HIGH and taken LOW after CAS# goes LOW results in a LATE WRITE (-controlled) cycle. t WCS, t RWD, t CWD and t AWD are not applicable in a LATE WRITE cycle. 4.Assumes that t RCD t RCD (MA). 5.If CAS# is LOW at the falling edge of, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for. 6.These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 7.If is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, must be pulsed during CAS# HIGH time in order to place I/O buffers in High-Z. 8.LATE WRITE and READ-MODIFY-WRITE cycles must have both t OD and t OEH met ( HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and is taken back LOW after t OEH is met. If CAS# goes HIGH prior to going back LOW, the DQs will remain open. 9.Assumes that t RCD < t RCD (MA). If t RCD is greater than the maximum recommended value shown in this table, t RAC will increase by the amount that t RCD exceeds the value shown. 2. t OFF (MA) defines the time at which the output achieves the open circuit condition and is not referenced to OH or OL. It is referenced from the rising edge of or CAS#, whichever occurs last. 2.The t RAD (MA) limit is no longer specified. t RAD (MA) was specified as a reference point only. If t RAD was greater than the specified t RAD (MA) limit, then access time was controlled exclusively by t AA ( t RAC and t CAC no longer applied). With or without the t RAD (MA) limit, t AA, t RAC, and t CAC must always be met. 22.The t RCD (MA) limit is no longer specified. t RCD (MA) was specified as a reference point only. If t RCD was greater than the specified t RCD (MA) limit, then access time was controlled exclusively by t CAC ( t RAC [MIN] no longer applied). With or without the t RCD limit, t AA and t CAC must always be met. 23.Either t RCH or t RRH must be satisfied for a READ cycle. 24.The first CAS#x edge to transition LOW. 25.Output parameter (DQx) is referenced to corresponding CAS# input; DQ-DQ7 by CASL# and DQ8-DQ5 by CASH#. Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

11 NOTES (continued) 26.Each CAS#x must meet minimum pulse width. 27.The last CAS#x edge to transition HIGH. 28.Last falling CAS#x edge to first rising CAS#x edge. 29.Last rising CAS#x edge to first falling CAS#x edge. 3.Last rising CAS#x edge to next cycle s last rising CAS#x edge. 3.Last CAS#x to go LOW. 32.A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, is LOW and is HIGH. Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

12 READ CYCLE t RC t RAS t RP IH t CSH t RSH t RRH t CRP t RCD t CAS t CLCH IH t RAD t AR tcah t ASR t RAH t ACH ADDR IH COLUMN t RCS t RCH IH t AA t RAC t CAC t OFF NOTE t CLZ DQ OH OL ALID DATA toe tod IH DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t AA 25 3 ns t ACH 2 5 ns t AR ns ns t ASR ns t CAC 3 5 ns t CAH 8 ns t CAS 8,, ns t CLCH 5 5 ns t CLZ ns t CRP 5 5 ns t CSH ns t OD 2 5 ns SYMBOL MIN MA MIN MA UNITS t OE 2 5 ns t OFF 2 5 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RAS 5, 6, ns t RC 84 4 ns t RCD 4 ns t RCH ns t RCS ns t RP 3 4 ns t RRH ns t RSH 3 5 ns NOTE:. t OFF is referenced from rising edge of or CAS#, whichever occurs last. 2 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

13 EARLY WRITE CYCLE t RC t RAS trp IH t CSH t RSH t CRP t RCD t CAS t CLCH IH t AR t RAD t CAH t ASR t RAH t ACH ADDR IH COLUMN t CWL t RWL t WCR t WCS t WCH t WP IH t DS t DH DQ IOH IOL ALID DATA IH DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t ACH 2 5 ns t AR ns ns t ASR ns t CAH 8 ns t CAS 8,, ns t CLCH 5 5 ns t CRP 5 5 ns t CSH ns t CWL 8 ns t DH 8 ns t DS ns SYMBOL MIN MA MIN MA UNITS t RAD 9 2 ns t RAH 9 ns t RAS 5, 6, ns t RC 84 4 ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns t RWL 3 5 ns t WCH 8 ns t WCR ns t WCS ns t WP 5 5 ns 3 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

14 READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RWC t RAS trp IH t CSH t RSH t CRP t RCD t CAS, t CLCH IH t AR t RAD t ASR t RAH t CAH t ACH ADDR IH COLUMN t RWD t CWL t RCS t CWD t AWD t RWL t WP IH t AA t RAC t CAC t DS t DH t CLZ DQ IOH IOL ALID D OUT ALID D IN t OE t OD t OEH IH DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t AA 25 3 ns t ACH 2 5 ns t AR ns ns t AWD ns t ASR ns t CAC 3 5 ns t CAH 8 ns t CAS 8,, ns t CLCH 5 5 ns t CLZ ns t CRP 5 5 ns t CSH ns t CWD ns t CWL 8 ns t DH 8 ns SYMBOL MIN MA MIN MA UNITS t DS ns t OD 2 5 ns t OE 2 5 ns t OEH 8 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RAS 5, 6, ns t RCD 4 ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t RWC 6 4 ns t RWD ns t RWL 3 5 ns t WP 5 5 ns 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

15 EDO-PAGE-MODE READ CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD t CAS, t CLCH t CAS, t CLCH t CAS, t CLCH IH tar tach tach tach t RAD t ASR t RAH t CAH t CAH t CAH ADDR IH COLUMN COLUMN COLUMN t RCS t RCH IH t AA t RRH t AA t AA A t RAC A t CAC t CLZ t CAC t CAC t COH t CLZ t OEHC t OFF DQ OH OL ALID DATA ALID DATA t OD ALID DATA t OE tod t OE tod IH t OES t OEP t OES DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t AA 25 3 ns t ACH 2 5 ns t AR ns ns t ASR ns t CAC 3 5 ns t CAH 8 ns t CAS 8,, ns t CLCH 5 5 ns t CLZ ns t COH 3 3 ns 8 ns A ns t CRP 5 5 ns t CSH ns t OD 2 5 ns SYMBOL MIN MA MIN MA UNITS t OE 2 5 ns t OEHC 5 ns t OEP 5 5 ns t OES 4 5 ns t OFF 2 5 ns t PC 2 25 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCH ns t RCS ns t RP 3 4 ns t RRH ns t RSH 3 5 ns 5 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

16 EDO-PAGE-MODE EARLY WRITE CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD t CAS, t CLCH t CAS, t CLCH t CAS, t CLCH IH t RAD t AR t ACH t ACH t ACH t ASR t RAH t CAH t CAH t CAH ADDR IH COLUMN COLUMN COLUMN t CWL t CWL t CWL t WCS t WCH t WCS t WCH t WCS t WCH t WP t WP t WP IH t WCR t RWL t DS t DH t DS t DH t DS t DH DQ IOH IOL ALID DATA ALID DATA ALID DATA IH DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t ACH 2 5 ns t AR ns ns t ASR ns t CAH 8 ns t CAS 8,, ns t CLCH 5 5 ns 8 ns t CRP 5 5 ns t CSH ns t CWL 8 ns t DH 8 ns SYMBOL MIN MA MIN MA UNITS t PC 2 25 ns t RAD 9 2 ns t RAH 9 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns t RWL 3 5 ns t WCH 8 ns t WCR ns t WCS ns t WP 5 5 ns t DS ns 6 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

17 EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RASP t RP IH t CRP t CSH t PC t PRWC NOTE t RCD t CAS, t CLCH t CAS, t CLCH t RSH t CAS, t CLCH IH t AR t RAD t ASR t RAH t CAH t CAH t CAH ADDR IH COLUMN COLUMN COLUMN t RWD t RWL t RCS t CWL t CWL t CWL t WP t AWD t WP t AWD t AWD t WP t CWD t CWD t CWD IH t AA t AA t AA t RAC t DS t DH A t DS t DH A t DS t DH t CAC t CLZ t CAC t CLZ t CAC t CLZ DQ IOH IOL ALID D OUT ALID D IN ALID D OUT ALID D IN ALID D OUT ALID D IN t OE t OD t OE t OD t OE tod toeh IH DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t AA 25 3 ns t AR ns ns t ASR ns t AWD ns t CAC 3 5 ns t CAH 8 ns t CAS 8,, ns t CLCH 5 5 ns t CLZ ns 8 ns A ns t CRP 5 5 ns t CSH ns t CWD ns t CWL 8 ns t DH 8 ns SYMBOL MIN MA MIN MA UNITS t DS ns t OD 2 5 ns t OE 2 5 ns t OEH 8 ns t PC 2 25 ns t PRWC ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t RWD ns t RWL 3 5 ns t WP 5 5 ns NOTE:. t PC is for LATE WRITE cycles only. 7 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

18 EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP t RP IH t CSH t PC t PC t RSH t CRP t RCD t CAS, t CLCH t CAS, t CLCH t CAS, t CLCH IH t AR t ACH t ASR t RAH t RAD t CAH t CAH t CAH ADDR IH COLUMN (A) COLUMN (B) COLUMN (N) t RCS t RCH t WCS t WCH IH t AA t AA t RAC A t CAC t CAC t DS t DH t COH t WHZ DQ IOH IOL ALID DOUT ALID DOUT ALID DIN t OE IH DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t AA 25 3 ns t ACH 2 5 ns t AR ns ns t ASR ns t CAC 3 5 ns t CAH 8 ns t CAS 8,, ns t CLCH 5 5 ns t COH 3 3 ns 8 ns A ns t CRP 5 5 ns t CSH ns t DH 8 ns SYMBOL MIN MA MIN MA UNITS t DS ns t OE 2 5 ns t PC 2 25 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCH ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t WCH 8 ns t WCS ns t WHZ 2 5 ns 8 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

19 READ CYCLE (with -controlled disable) IH t CSH t CRP t RCD t CAS, t CLCH IH t ASR t RAD t AR tcah t RAH ADDR IH COLUMN COLUMN t RCS t RCH t WPZ t RCS IH t AA t RAC t CAC t CLZ t WHZ t CLZ DQ OH OL ALID DATA toe tod IH DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t AA 25 3 ns t AR ns ns t ASR ns t CAC 3 5 ns t CAH 8 ns t CAS 8,, ns t CLCH 5 5 ns t CLZ ns 8 ns t CRP 5 5 ns SYMBOL MIN MA MIN MA UNITS t CSH ns t OD 2 5 ns t OE 2 5 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RCD 4 ns t RCH ns t RCS ns t WHZ 2 5 ns t WPZ ns 9 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

20 -ONLY REFRESH CYCLE ( and = DON T CARE) t RC t RAS t RP IH t CRP t RPC IH t ASR t RAH ADDR IH Q OH OL CBR REFRESH CYCLE (Addresses and = DON T CARE) t RP t RAS NOTE t RP t RAS IH t RPC t CSR t CHR t RPC t CSR tchr IH DQ OH OL t WRP t WRH t WRP t WRH IH DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t ASR ns t CHR 8 ns 8 ns t CRP 5 5 ns t CSR 5 5 ns t RAH 9 ns SYMBOL MIN MA MIN MA UNITS t RAS 5, 6, ns t RC 84 4 ns t RP 3 4 ns t RPC 5 5 ns t WRH 8 ns t WRP 8 ns NOTE:. End of first CBR REFRESH cycle. 2 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

21 HIDDEN REFRESH CYCLE ( = HIGH; = LOW) t RC t RAS t RP t RAS IH t CRP t RCD t RSH t CHR IH t AR t RAD t ASR t RAH t CAH ADDR IH COLUMN t AA t RAC t CAC t CLZ t OFF DQx IOH IOL ALID DATA t OE t OD IH t ORD DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t AA 25 3 ns t AR ns ns t ASR ns t CAC 3 5 ns t CAH 8 ns t CHR 8 ns t CLZ ns t CRP 5 5 ns t OD 2 5 ns SYMBOL MIN MA MIN MA UNITS t OE 2 5 ns t OFF 2 5 ns t ORD ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RAS 5, 6, ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns 2 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

22 SELF REFRESH CYCLE (Addresses and = DON T CARE) t RP t RASS ( ) ( ) NOTE t RPS NOTE 2 IH t RPC ( ( t RPC ( ( ) ) ) ) t CSR t CHD CASL#/ CASH# IH ( ) ( ) ( ) ( ) DQ OH OL t WRP t WRH ( ) ( ) t WRP t WRH IH ( ) ( ) ( ) ( ) DON T CARE TIMING PARAMETERS SYMBOL MIN MA MIN MA UNITS t CHD 5 5 ns t CLCH 5 5 ns 8 ns t CSR 5 5 ns t RASS µs SYMBOL MIN MA MIN MA UNITS t RP 3 4 ns t RPC 5 5 ns t RPS 9 5 ns t WRH 8 ns t WRP 8 ns NOTE:. Once t RASS (MIN) is met and remains LOW, the DRAM will enter self refresh mode. 2. Once t RPS is satisfied, a complete burst of all rows should be executed. 22 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

23 44/5-PIN PLASTIC TSOP (4 mil) (2.4).822 (2.88).29 (.75) TYP SEE DETA A.467 (.86).459 (.66).42 (.2).398 (.) PIN # INDE.3 (.8) TYP.8 (.45).2 (.3) 25.7 (.8).5 (.3).47 (.2) MA.4 (.) SEATING PLANE.8 (.2).2 (.5) DETA A.32 (.8) TYP. (.25).24 (.6).6 (.4) NOTE:. All dimensions in inches (millimeters) MA or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is." per side. 23 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc

24 42-PIN PLASTIC SOJ (4 mil).79 (27.4).73 (27.25).45 (.29).399 (.3).445 (.3).435 (.5) PIN # INDE.5 (.27) TYP. (25.4).32 (.8).26 (.66).48 (3.76).38 (3.5).95 (2.4).8 (2.2) SEATING PLANE.37 (.94) MA DAMBAR PROTRUSION.2 (.5).5 (.38).38 (9.65).36 (9.4).3 (.76) MIN NOTE:. All dimensions in inches (millimeters) MA or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is." per side. 8 S. Federal Way, P.O. Box 6, Boise, ID , Tel: prodmktg@micron.com, Internet: Customer Comment Line: Micron is a registered trademark and the Micron logo and the M logos are trademarks of Micron Technology, Inc. 24 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 Rev. B; Pub. 3/ 2, Micron Technology, Inc