DRAM MT4LC4M16R6, MT4LC4M16N3. 4 MEG x 16 EDO DRAM

Transcription

1 DRAM 4 MEG x 6 MT4LC4M6R6, MT4LC4M6N3 For the latest data sheet, please refer to the Micron Web site: FEATURES Single +3.3 ±.3 power supply Industry-standard x6 pinout, timing, functions, and package 2 row, column addresses (R6) 3 row, 9 column addresses (N3) High-performance CMOS silicon-gate process All inputs, outputs and clocks are LTTL-compatible Extended Data-Out (EDO) PAGE MODE access 4,96-cycle CAS#-BEFORE- (CBR) REFRESH distributed across 64ms Optional self refresh (S) for low-power data retention OPTIONS Plastic Package 5-pin TSOP (4 mil) MARKING TG Timing 5ns access -5 6ns access -6 Refresh Rates 4K R6 8K N3 Standard Refresh None Self Refresh S* Operating Temperature Range Commercial ( C to +7 C) NOTE: None. The # symbol indicates signal is active LOW. PIN ASSIGNMENT (Top iew) 5-Pin TSOP CC DQ DQ DQ2 DQ3 CC DQ4 DQ5 DQ6 DQ7 NC CC NC NC NC NC A A A2 A3 A4 A5 CC A2 for N3 version, NC for R6 version. SS DQ5 DQ4 DQ3 DQ2 SS DQ DQ DQ9 DQ8 NC SS CASL# CASH# NC NC NC/A2 A A A9 A8 A7 A6 SS MT4LC4M6R6 MT4LC4M6N3 Configuration 4 Meg x 6 4 Meg x 6 Refresh 4K 8K Row Address 4K (A-A) 8K (A-A2) Column Addressing K (A-A9) 52 (A-A8) *Contact factory for availability. Part Number Example: MT4LC4M6R6TG-5 KEY TIMING PARAMETERS SPEED t RC t RAC t PC t AA t CAC -5 84ns 5ns 2ns 25ns 3ns 8ns -6 4ns 6ns 25ns 3ns 5ns ns 4 MEG x 6 PART NUMBERS REFRESH PART NUMBER ADDRESSING PACKAGE REFRESH MT4LC4M6R6TG-x 4K 4-TSOP Standard MT4LC4M6R6TG-x S 4K 4-TSOP Self MT4LC4M6N3TG-x 8K 4-TSOP Standard MT4LC4M6N3TG-x S 8K 4-TSOP Self x = speed 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

2 4 MEG x 6 FUNCTIONAL BLOCK DIAGRAM MT4LC4M6R6 (2 row addresses) CASL# CASH# CAS# -IN BUFFER 6 DQ- DQ5 NO. 2 CLOCK GENERATOR -OUT BUFFER 6 A- A - ADDRESS BUFFER() REFRESH CONTROLLER REFRESH COUNTER DECODER,24,24 x 6 6 SENSE AMPLIFIERS I/O GATING ADDRESS BUFFERS (2) 2 DECODER 4,96 COMPLEMENT SELECT 4,96 x 6 SELECT 4,96 x,24 x 6 MEMORY ARRAY NO. CLOCK GENERATOR DD SS FUNCTIONAL BLOCK DIAGRAM MT4LC4M6N3 (3 row addresses) CASL# CASH# CAS# -IN BUFFER 6 DQ- DQ5 NO. 2 CLOCK GENERATOR -OUT BUFFER 6 A- A2 9 - ADDRESS BUFFER(9) REFRESH CONTROLLER REFRESH COUNTER 9 DECODER SENSE AMPLIFIERS I/O GATING 52 x ADDRESS BUFFERS (3) 3 DECODER 892 COMPLEMENT SELECT 892 x 6 SELECT 892 x 52 x 6 MEMORY ARRAY NO. CLOCK GENERATOR cc ss 2 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

3 4 MEG x 6 GENERAL DESCRIPTION The 4 Meg x 6 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,8,864 bits and designed to operate from 3 to 3.6. The device is functionally organized as 4,94,34 locations containing 6 bits each. The 4,94,34 memory locations are arranged in 4,96 rows by,24 columns on the MT4LC4M6R6 or 8,92 rows by 52 columns on the MT4LC4M6N3. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 2 row-address bits (A-A) and column-address bits (A-A9) on the MT4LC4M6R6 or 3 row-address bits (A-A2) and 9 column-address bits (A-A8) on the MT4LC4M6N3 version. In addition, both byte and word accesses are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) is such that the internal CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and the last to transition back HIGH. The CAS# functionality and timing related to driving or latching data is such that each CAS# signal independently controls the associated eight DQ pins. The row address is latched by the signal, then the column address is latched by CAS#. This device provides EDO-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE or READ- MODIFY-WRITE) within a given row. The 4 Meg x 6 DRAM must be refreshed periodically in order to retain stored data. DRAM ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 6 I/O pins (DQ-DQ5). Using only one of the two signals results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ-DQ7), and CASH# transitioning LOW selects an access cycle for WORD WRITE LOWER BYTE WRITE CASL# CASH# LOWER BYTE (DQ-DQ7) OF WORD STORED INPUT INPUT STORED STORED INPUT INPUT STORED UPPER BYTE (DQ8-DQ5) OF WORD ADDRESS ADDRESS = NOT EFFECTIE (DON'T CARE) Figure WORD and BYTE WRITE Example 3 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

4 4 MEG x 6 DRAM ACCESS (continued) the upper byte (DQ8-DQ5). General byte and word access timing is shown in Figures and 2. A logic HIGH on dictates read mode, while a logic LOW on dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READ- MODIFY-WRITE occurs when WE falls after CAS# (CASL# or CASH#) is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-, regardless of the state of. During LATE WRITE or READ-MODIFY- WRITE cycles, must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping LOW, no write will occur, and the data outputs will drive read data from the accessed location. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. EDO PAGE MODE DRAM READ cycles have traditionally turned the output buffers off (High-) with the rising edge of CAS#. If CAS# went HIGH and was LOW (active), the output buffers would be disabled. The 64Mb EDO DRAM offers an accelerated page mode cycle by eliminating output disable from CAS# HIGH. This option is called EDO, and it allows CAS# precharge time ( ) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms). EDO operates like any DRAM READ or FAST-PAGE- MODE READ, except data is held valid after CAS# goes HIGH, as long as and are held LOW and is held HIGH. can be brought LOW or HIGH while CAS# and are LOW, and the DQs will transition between valid data and High-. Using, there are WORD READ LOWER BYTE READ CASL# CASH# LOWER BYTE (DQ-DQ7) OF WORD STORED OUTPUT OUTPUT STORED STORED OUTPUT OUTPUT STORED UPPER BYTE (DQ8-DQ5) OF WORD ADDRESS ADDRESS = High- Figure 2 WORD and BYTE READ Example 4 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

5 4 MEG x 6 IH CAS# IH ADDR IH (A) (B) (C) (D) DQ IOH IOL ALID (A) t OD ALID (A) ALID (B) t OD ALID (C) t OD ALID (D) t OES t OEHC IH t OE t OEP The DQs go back to Low- if t OES is met. Figure 3 Control of DQs The DQs remain High- until the nex# cycle if t OEHC is met. The DQs remain High- until the nex# cycle if t OEP is met. IH CAS# IH ADDR IH (A) (B) (C) (D) DQ IOH IOL ALID (A) ALID (B) INPUT (C) t WH t WH IH t WP IH The DQs go to High- if falls and, if t WP is met, will remain High- until CAS# goes LOW with HIGH (i.e., until a READ cycle is initiated). may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High- until CAS# goes LOW with HIGH (i.e., until a READ cycle is initiated). DON T CARE UNDEFINED Figure 4 Control of DQs 5 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

6 4 MEG x 6 EDO PAGE MODE (continued) two methods to disable the outputs and keep them disabled during the CAS# HIGH time. The first method is to have HIGH when CAS# transitions HIGH and keep HIGH for t OEHC thereafter. This will disable the DQs, and they will remain disabled (regardless of the state of after that point) until CAS# falls again. The second method is to have LOW when CAS# transitions HIGH and then bring HIGH for a minimum of t OEP anytime during the CAS# HIGH period. This will disable the DQs, and they will remain disabled (regardless of the state of after that point) until CAS# falls again (see Figure 3). During other cycles, the outputs are disabled at t OFF time after and CAS# are HIGH or at t WH after transitions LOW. The t OFF time is referenced from the rising edge of or CAS#, whichever occurs last. can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 4. EDO-PAGE-MODE operations are always initiated with a row address strobed in by the signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding LOW and entering new column addresses with each CAS# cycle. Returning HIGH terminates the EDO-PAGE-MODE operation. DRAM REFRESH The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the 4 Meg x 6 DRAM array at least once every 64ms (8,92 rows for N3 or 4,96 rows for R6). The recommended procedure is to execute 4,96 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC4M6N3 internally refreshes two rows for each CBR cycle, whereas the MT4LC4M6R6 refreshes one row for every CBR cycle. For either device, executing 4,96 CBR cycles will refresh the entire device. The CBR REFRESH will invoke the internal refresh counter for automatic addressing. Alternatively, -ONLY REFRESH capability is inherently provided. However, with this method, only one row is refreshed on each cycle. Thus, 8,92 RAS-only REFRESH cycles are needed every 64ms on the MT4LC4M6N3 in order to refresh the entire device. JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the S version. The self refresh feature is initiated by performing a CBR Refresh cycle and holding low for the specified t RASS. The S option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 28ms, or 3.25µs per cycle, when using a distributed CBR refresh. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving HIGH for a minimum time of t RPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh, however, if the controller is using only or burst CBR refresh then a burst refresh using t RC (MIN) is required. 6 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

7 4 MEG x 6 ABSOLUTE MAIMUM RATINGS* oltage on CC Relative to SS... - to +4.6 oltage on NC, Inputs or I/O Pins Relative to SS... - to +4.6 Operating Temperature, T A (ambient) Commercial... C to +7 C Storage Temperature (plastic) C to +5 C Power Dissipation... W *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Note: ) (CC = +3.3 ±.3) PARAMETER/CONDITION SYMBOL MIN MA UNITS NOTES SUPPLY OLTAGE CC INPUT HIGH OLTAGE: alid Logic ; All inputs, I/Os and any NC IH 2 CC INPUT LOW OLTAGE: alid Logic ; All inputs, I/Os and any NC INPUT LEAKAGE CURRENT: Any input at IN ( IN CC +.3); II -2 2 µa 36 All other pins not under test = OUTPUT HIGH OLTAGE: IOUT = -2mA OH 2.4 OUTPUT LOW OLTAGE: IOUT = 2mA OL.4 OUTPUT LEAKAGE CURRENT: Any output at OUT ( OUT CC +.3); IO -5 5 µa DQ is disabled and in High- state 7 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

8 Icc OPERATING CONDITIONS AND MAIMUM LIMITS (Notes:, 2, 3, 5, 6; notes appear on page ) (CC = +3.3 ±.3) 4 MEG x 6 MA PARAMETER/CONDITION SYMBOL SPEED 4K 8K UNITS NOTES STANDBY CURRENT: TTL ICC ALL ma ( = CAS# = IH) STANDBY CURRENT: CMOS ( = CAS# CC -.2; DQs may be left open; ICC2 ALL 5 5 µa Other inputs: IN CC -.2 or IN.2) OPERATING CURRENT: Random READ/WRITE ICC ma 26 Average power supply current (, CAS#, address cycling: t RC = t RC [MIN]) OPERATING CURRENT: EDO PAGE MODE ICC ma 26 Average power supply current ( =, CAS#, address cycling: t PC = t PC [MIN]) REFRESH CURRENT: -ONLY ICC ma 22 Average power supply current ( cycling, CAS# = IH: t RC = t RC [MIN]) REFRESH CURRENT: CBR ICC ma 4, 7, Average power supply current (, CAS#, address cycling: t RC = t RC [MIN]) REFRESH CURRENT: Extended ( S version only) ICC7 ALL 4 4 µa 4, 7, Average power supply current: CAS# =.2 or CBR cycling; 23, 37 = t RAS (MIN); = CC -.2; A-A, and DIN = CC -.2 or.2 (DIN may be left open); t RC = 25µs REFRESH CURRENT: Self ( S version only) ICC8 ALL µa 4, 7, Average power supply current: CBR with t RASS (MIN) 37 and CAS# held LOW; = CC -.2; A-A, and DIN = CC -.2 or.2 (DIN may be left open) 8 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

9 4 MEG x 6 CAPACITANCE (Note: 2; notes appear on page ) PARAMETER SYMBOL MA UNITS Input Capacitance: Address pins CI 5 pf Input Capacitance:, CAS#,, CI2 7 pf Input/Output Capacitance: DQ CIO 7 pf AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9,,, 2; notes appear on page ) (CC = +3.3 ±.3) AC CHARACTERISTICS PARAMETER NOTES Access time from column address t AA 25 3 ns Column-address setup to CAS# precharge t ACH 2 5 ns Column-address hold time (referenced to ) t AR ns Column-address setup time t ASC ns 28 Row-address setup time t ASR ns 28 Column address to delay time t AWD ns 8 Access time from CAS# t CAC 3 5 ns 29 Column-address hold time t CAH 8 ns 28 CAS# pulse width 8,, ns 3, 32 CAS# LOW to Don t Care during Self Refresh t CHD 5 5 ns CAS# hold time (CBR Refresh) t CHR 8 ns 4, 3 Las# going LOW to firs# to return HIGH t CLCH 5 5 ns 3 CAS# to output in Low- t CL ns 29 Data output hold after CAS# LOW t COH 3 3 ns CAS# precharge time 8 ns 3, 33 Access time from CAS# precharge A ns 29 CAS# to precharge time t CRP 5 5 ns 3 CAS# hold time t CSH ns 3 CAS# setup time (CBR Refresh) t CSR 5 5 ns 4, 28 CAS# to delay time t CWD ns 8, 28 WRITE command to CAS# lead time t CWL 8 ns 3 Data-in hold time t DH 8 ns 9, 29 Data-in setup time t DS ns 9, 29 Output disable t OD 2 5 ns 24, 25 Output enable time t OE 2 5 ns 2 hold time from during t OEH 8 ns 25 READ-MODIFY-WRITE cycle HIGH hold time from CAS# HIGH t OEHC 5 ns HIGH pulse width t OEP 5 5 ns LOW to CAS# HIGH setup time t OES 4 5 ns Output buffer turn-off delay t OFF 2 5 ns 7, 24, 29 setup prior to during HIDDEN REFRESH cycle t ORD ns 9 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

10 4 MEG x 6 AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9,,, 2; notes appear on page ) (CC = +3.3 ±.3) AC CHARACTERISTICS PARAMETER NOTES EDO-PAGE-MODE READ or WRITE cycle time t PC 2 25 ns 34 EDO-PAGE-MODE READ-WRITE cycle time t PRWC ns 34 Access time from t RAC 5 6 ns to column-address delay time t RAD 9 2 ns 5 Row address hold time t RAH 7 ns pulse width t RAS 5, 6, ns pulse width (EDO PAGE MODE) t RASP 5 25, 6 25, ns pulse width during Self Refresh t RASS µs Random READ or WRITE cycle time t RC 84 4 ns to CAS# delay time t RCD 4 ns 4, 28 READ command hold time (referenced to CAS#) t RCH ns 6, 3 READ command setup time t RCS ns 28 Refresh period t REF ms 22, 23 Refresh period ( S version) t REF ms 23 precharge time t RP 3 4 ns to CAS# precharge time t RPC 5 5 ns precharge time exiting Self Refresh t RPS 9 5 ns READ command hold time (referenced to ) t RRH ns 6 hold time t RSH 3 5 ns 35 READ-WRITE cycle time t RWC 6 4 ns to delay time t RWD ns 8 WRITE command to lead time t RWL 3 5 ns Transition time (rise or fall) t T ns WRITE command hold time t WCH 8 ns 35 WRITE command hold time (referenced to ) t WCR ns command setup time t WCS ns 8, 28 to outputs in High- t WH 2 5 ns WRITE command pulse width t WP 5 5 ns pulse widths to disable outputs t WP ns hold time (CBR Refresh) t WRH 8 ns setup time (CBR Refresh) t WRP 8 ns 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

11 4 MEG x 6 NOTES. All voltages referenced to SS. 2. This parameter is sampled. CC = +3.3; f = MHz; T A = 25 C. 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of µs is required after powerup, followed by eight refresh cycles (- ONLY or CBR with HIGH), before proper device operation is ensured. The eight cycle wake-ups should be repeated any time the t REF refresh requirement is exceeded. 7. AC characteristics assume t T = 2.5ns. 8. IH (MIN) and (MA) are reference levels for measuring timing of input signals. Transition times are measured between IH and (or between and IH). 9. In addition to meeting the transition rate specification, all input signals must transit between IH and (or between and IH) in a monotonic manner.. If CAS# and = IH, data output is High-.. If CAS# =, data output may contain data from the last valid READ cycle. 2. Measured with a load equivalent to two TTL gates and pf; and OL =.8 and OH = If CAS# is LOW at the falling edge of, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for. 4. The t RCD (MA) limit is no longer specified. t RCD (MA) was specified as a reference point only. If t RCD was greater than the specified t RCD (MA) limit, then access time was controlled exclusively by t CAC ( t RAC [MIN] no longer applied). With or without the t RCD limit, t AA and t CAC must always be met. 5. The t RAD (MA) limit is no longer specified. t RAD (MA) was specified as a reference point only. If t RAD was greater than the specified t RAD (MA) limit, then access time was controlled exclusively by t AA ( t RAC and t CAC no longer applied). With or without the t RAD (MA) limit, t AA, t RAC, and t CAC must always be met. 6. Either t RCH or t RRH must be satisfied for a READ cycle. 7. t OFF (MA) defines the time at which the output achieves the open circuit condition and is not referenced to OH or OL. 8. t WCS, t RWD, t AWD, and t CWD are not restrictive operating parameters. t WCS applies to EARLY WRITE cycles. If t WCS > t WCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. t RWD, t AWD, and t CWD define READ- MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. held HIGH and taken LOW after CAS# goes LOW results in a LATE WRITE (-controlled) cycle. t WCS, t RWD, t CWD, and t AWD are not applicable in a LATE WRITE cycle. 9. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 2. If is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible. 2. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, is LOW and is HIGH ONLY REFRESH requires that all 8,92 rows of the MT4LC4M6N3 or all 4,96 rows of the MT4LC4M6R6 be refreshed at least once every 64ms. 23. CBR REFRESH for either device requires that at least 4,96 cycles be completed every 64ms. 24. The DQs go High- during READ cycles once t OD or t OFF occur. If CAS# stays LOW while is brought HIGH, the DQs will go High-. If is brought back LOW (CAS# still LOW), the DQs will provide the previously read data. 25. LATE WRITE and READ-MODIFY-WRITE cycles must have both t OD and t OEH met ( HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If is taken back LOW while CAS# remains LOW, the DQs will remain open. 26. Column address changed once each cycle. 27. The firsx# edge to transition LOW. 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

12 4 MEG x 6 NOTES (continued) 28. Output parameter (DQx) is referenced to corresponding CAS# input; DQ-DQ7 by CASL# and DQ8-DQ5 by CASH#. 29. Each CASx# must meet minimum pulse width. 3. The lasx# edge to transition HIGH. 3. Last falling CASx# edge to first rising CASx# edge. 32. Last rising CASx# edge to first falling CASx# edge. 33. Last rising CASx# edge to next cycle s last rising CASx# edge. 34. Lasx# to go LOW. 35. IH overshoot: IH (MA) = CC + 2 for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. undershoot: (MIN) = -2 for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. 36. NC pins are assumed to be left floating and are not tested for leakage. 37. Self refresh and extended refresh for either device requires that at least 4,96 cycles be completed every 28ms. 2 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

13 4 MEG x 6 READ CYCLE t RC t RAS t RP IH t CSH t RSH t RRH t CRP t RCD CAS# IH t RAD t AR tcah t ASR t RAH t ASC t ACH ADDR IH t RCS t RCH IH t AA t RAC t CAC t OFF NOTE t CL DQ OH OL ALID toe tod IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t ACH 2 5 ns t AR ns t ASC ns t ASR ns t CAC 3 5 ns t CAH 8 ns 8,, ns t CLCH 5 5 ns t CL ns t CRP 5 5 ns t CSH ns t OD 2 5 ns t OE 2 5 ns t OFF 2 5 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 7 ns t RAS 5, 6, ns t RC 84 4 ns t RCD 4 ns t RCH ns t RCS ns t RP 3 4 ns t RRH ns t RSH 3 5 ns NOTE:. t OFF is referenced from rising edge of or CAS#, whichever occurs last. 3 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

14 4 MEG x 6 EARLY WRITE CYCLE t RC t RAS trp IH t CSH t RSH t CRP t RCD CAS# IH t AR t RAD t ASR t RAH t ASC t CAH t ACH ADDR IH t CWL t RWL t WCR t WCS t WCH t WP IH t DS t DH DQ IOH IOL ALID IH DON T CARE UNDEFINED TIMING PARAMETERS t ACH 2 5 ns t AR ns t ASC ns t ASR ns t CAH 8 ns 8,, ns t CLCH 5 5 ns t CRP 5 5 ns t CSH ns t CWL 8 ns t DH 8 ns t DS ns t RAD 9 2 ns t RAH 7 ns t RAS 5, 6, ns t RC 84 4 ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns t RWL 3 5 ns t WCH 8 ns t WCR ns t WCS ns t WP 5 5 ns 4 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

15 4 MEG x 6 READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RWC t RAS trp IH t CSH t RSH t CRP t RCD CAS# IH t AR t RAD t ASR t RAH t ASC t CAH t ACH ADDR IH t RWD t CWL t RCS t CWD t AWD t RWL t WP IH t AA t RAC t CAC t DS t DH t CL DQ IOH IOL ALID D OUT ALID D IN t OE t OD t OEH IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t ACH 2 5 ns t AR ns t ASC ns t ASR ns t AWD ns t CAC 3 5 ns t CAH 8 ns 8,, ns t CLCH 5 5 ns t CL ns t CRP 5 5 ns t CSH ns t CWD ns t CWL 8 ns t DH 8 ns t DS ns t OD 2 5 ns t OE 2 5 ns t OEH 8 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 7 ns t RAS 5, 6, ns t RCD 4 ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t RWC 6 4 ns t RWD ns t RWL 3 5 ns t WP 5 5 ns 5 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

16 4 MEG x 6 EDO-PAGE-MODE READ CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD CAS# IH t AR t RAD t ACH t ACH t ACH t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDR IH t RCS t RCH IH t AA t RRH t AA t AA A t RAC A t CAC t CL t CAC t CAC t COH t CL t OEHC t OFF DQ OH OL ALID ALID t OD ALID t OE tod t OE tod IH t OES t OEP t OES DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t ACH 2 5 ns t AR ns t ASC ns t ASR ns t CAC 3 5 ns t CAH 8 ns 8,, ns t CLCH 5 5 ns t CL ns t COH 3 3 ns 8 ns A ns t CRP 5 5 ns t CSH ns t OD 2 5 ns t OE 2 5 ns t OEHC 5 ns t OEP 5 5 ns t OES 4 5 ns t OFF 2 5 ns t PC 2 25 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 7 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCH ns t RCS ns t RP 3 4 ns t RRH ns t RSH 3 5 ns 6 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

17 4 MEG x 6 EDO-PAGE-MODE EARLY WRITE CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD CAS# IH t AR t RAD t ACH t ACH t ACH t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDR IH t CWL t CWL t CWL t WCS t WCH t WCS t WCH t WCS t WCH t WP t WP t WP IH t WCR t RWL t DS t DH t DS t DH t DS t DH DQ IOH IOL ALID ALID ALID DON T CARE UNDEFINED TIMING PARAMETERS t ACH 2 5 ns t AR ns t ASC ns t ASR ns t CAH 8 ns 8,, ns t CLCH 5 5 ns 8 ns t CRP 5 5 ns t CSH ns t CWL 8 ns t DH 8 ns t DS ns t PC 2 25 ns t RAD 9 2 ns t RAH 7 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns t RWL 3 5 ns t WCH 8 ns t WCR ns t WCS ns t WP 5 5 ns 7 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

18 4 MEG x 6 EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RASP t RP IH t CRP t CSH t PC t PRWC t RCD NOTE t RSH CASL#/CASH# IH t AR t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDR IH t RWD t RWL t RCS t CWL t CWL t CWL t WP t AWD t WP t AWD t AWD t WP t CWD t CWD t CWD IH t AA t AA t AA t RAC t DS t DH A t DS t DH A t DS t DH t CAC t CL t CAC t CL t CAC t CL DQ IOH IOL ALID D OUT ALID D IN ALID D OUT ALID D IN ALID D OUT ALID D IN t OE t OD t OE t OD t OE tod toeh IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t AWD ns t CAC 3 5 ns t CAH 8 ns 8,, ns t CLCH 5 5 ns t CL ns 8 ns A ns t CRP 5 5 ns t CSH ns t CWD ns t CWL 8 ns t DH 8 ns t DS ns t OD 2 5 ns t OE 2 5 ns t OEH 8 ns t PC 2 25 ns t PRWC ns t RAC 5 6 ns t RAD 9 2 ns t RAH 7 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t RWD ns t RWL 3 5 ns t WP 5 5 ns NOTE:. t PC is for LATE WRITE cycles only. 8 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

19 4 MEG x 6 EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP t RP IH t CSH t PC t PC t RSH t CRP t RCD CAS# IH t AR t ACH t ASR t RAH t RAD t ASC t CAH t ASC t CAH t ASC t CAH ADDR IH (A) (B) (N) t RCS t RCH t WCS t WCH IH t AA t AA t RAC A t CAC t CAC t DS t DH t COH t WH DQ IOH IOL ALID (A) ALID (B) ALID IN t OE IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t ACH 2 5 ns t AR ns t ASC ns t ASR ns t CAC 3 5 ns t CAH 8 ns 8,, ns t COH 3 3 ns 8 ns A ns t CRP 5 5 ns t CSH ns t DH 8 ns t OE 2 5 ns t PC 2 25 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 7 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCH ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t WCH 8 ns t WCS ns t WH 2 5 ns t DS ns 9 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

20 4 MEG x 6 READ CYCLE (with -controlled disable) IH t CSH t CRP t RCD CASL#/CASH# IH t ASR t RAD t AR tcah t RAH t ASC t ASC ADDR IH t RCS t RCH t WP t RCS IH t AA t RAC t CAC t CL t WH t CL DQ OH OL ALID toe tod IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t CAC 3 5 ns t CAH 8 ns 8,, ns t CL ns 8 ns t CRP 5 5 ns t OD 2 5 ns t OE 2 5 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 7 ns t RCD 4 ns t RCH ns t RCS ns t WH 2 5 ns t WP ns t CSH ns 2 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

21 4 MEG x 6 -ONLY REFRESH CYCLE ( and = DON T CARE) t RC t RAS t RP IH t CRP t RPC CASL#/CASH# IH t ASR t RAH ADDR IH Q OH OL CBR REFRESH CYCLE (Addresses and = DON T CARE) t RP t RAS NOTE t RP t RAS IH t RPC t CSR t CHR t RPC t CSR tchr CASL#/CASH# IH DQ OH OL t WRP t WRH t WRP t WRH IH DON T CARE UNDEFINED TIMING PARAMETERS t ASR ns t CHR 8 ns 8 ns t CRP 5 5 ns t CSR 5 5 ns t RAH 7 ns t RAS 5, 6, ns t RC 84 4 ns t RP 3 4 ns t RPC 5 5 ns t WRH 8 ns t WRP 8 ns NOTE:. End of first CBR REFRESH cycle. 2 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

22 4 MEG x 6 HIDDEN REFRESH CYCLE ( = HIGH; = LOW) t RC t RAS t RP t RAS IH t CRP t RCD t RSH t CHR CASL#/CASH# IH t AR t RAD t ASR t RAH t ASC t CAH ADDR IH t AA t RAC t CAC t CL t OFF DQx IOH IOL ALID t OE t OD IH t ORD DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t CAC 3 5 ns t CAH 8 ns t CHR 8 ns t CL ns t CRP 5 5 ns t OD 2 5 ns t OE 2 5 ns t OFF 2 5 ns t ORD ns t RAC 5 6 ns t RAD 9 2 ns t RAH 7 ns t RAS 5, 6, ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns NOTE:. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, is LOW and is HIGH Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

23 4 MEG x 6 SELF REFRESH CYCLE (Addresses and = DON T CARE) t RP t RASS ( ) ( ) NOTE t RPS NOTE 2 IH t RPC ( ( t RPC ( ( ) ) ) ) t CSR t CHD CASL#/ CASH# IH ( ) ( ) ( ) ( ) DQ OH OL t WRP t WRH ( ) ( ) t WRP t WRH IH ( ) ( ) ( ) ( ) DON T CARE UNDEFINED TIMING PARAMETERS t CHD 5 5 ns t CLCH 5 5 ns 8 ns t CSR 5 5 ns t RASS ns t RP 3 4 ns t RPC 5 5 ns t RPS 9 5 ns t WRH 8 ns t WRP 8 ns NOTE:. Once t RASS (MIN) is met and remains LOW, the DRAM will enter self refresh mode. 2. Once t RPS is satisfied, a complete burst of all rows should be executed if -only or burst CBR refresh is used Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.

24 4 MEG x 6 5-PIN PLASTIC TSOP (4 mil) TYP SEE DETA A 25 PIN # ID.8 TYP GAGE PLANE MA..6.4 DETA A.8 TYP NOTE:. All dimensions in millimeters MA or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is.25mm per side. 8 S. Federal Way, P.O. Box 6, Boise, ID , Tel: prodmktg@micron.com, Internet: Customer Comment Line: Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D29_C.p65 Rev. 2/ 2, Micron Technology, Inc.