IBM IBM M IBM B IBM P 4M x 4 12/10 DRAM

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1 IBM M x 412/10, 5.0VMMDD31DSU IBM P 4M x 412/10, 3.3V, LP, SRMMDD31DSU IBM M 4M x 412/10, 5.0V, LP, SRMMDD31DSU IBM B4M x 412/10, 3.3VMMDD31DSU IBM IBM M Features 4,194,304 word by 4 bit organization Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply Standard Power (SP) and Low Power (LP) 4096 Refresh Cycles - 64 ms Refresh Rate (SP version) ms Refresh Rate (LP version) High Performance: Units t RAC Access Time ns t CAC Access Time ns t AA Column Address Access Time ns t RC Cycle Time ns t PC Fast Page Mode Cycle Time ns Low Power Dissipation - Active (max) - 50 ma / 45 ma - Standby: TTL Inputs (max) ma - Standby: CMOS Inputs (max) ma (SP version) ma (LP version) - Self Refresh (LP version only) - 200µA (3.3 Volt) - 300µA (5.0 Volt) Read-Modify-Write Only and before Refresh Hidden Refresh Package: SOJ-28/24 (400mil x 725mil) SOJ-26/24 (300mil x 675mil) TSOP-26/24 (300mil x 675mil) Description The IBM is a dynamic RAM organized 4,194,304 words by 4 bits, which has a very low sleep mode power consumption option. These devices are fabricated in IBM s advanced 0.5µm CMOS silicon gate process technology. The circuit and process have been carefully designed to provide high performance, low power dissipation, and high reliability. The devices operate with a single 3.3V ± 0.3V or 5.0V ± 0.5V power supply. The 22 addresses required to access any bit of data are multiplexed (12 are strobed with, 10 are strobed with ). Pin Assignments (Top View) Pin Description 28/24 26/24 Row Address Strobe Column Address Strobe Vcc I/O0 I/O1 A Vss I/O3 I/O2 OE A9 Vcc I/O0 I/O1 A Vss I/O3 I/O2 OE A9 A0 - A11 OE I/O0 - I/O3 V CC Read/Write Input Address Inputs Output Enable Data Input/Output Power (+3.3V or +5.0V) A10 A0 A1 A2 A3 Vcc A8 A7 A6 A5 A4 Vss A10 A0 A1 A2 A3 Vcc A8 A7 A6 A5 A4 Vss V SS Ground Page 1 of 28

2 Ordering Information Part Number SP / LP Self Refresh Power Supply Speed Package Notes IBM J3-50 SP No 5.0V 50ns 400mil SOJ 28/24 1 IBM J3-60 SP No 5.0V 60ns 400mil SOJ 28/24 1 IBM J1-50 SP No 5.0V 50ns 300mil SOJ 26/24 1 IBM J1-60 SP No 5.0V 60ns 300mil SOJ 26/24 1 IBM T1-50 SP No 5.0V 50ns 300mil TSOP 26/24 1 IBM T1-60 SP No 5.0V 60ns 300mil TSOP 26/24 1 IBM BJ3-50 SP No 3.3V 50ns 400mil SOJ 28/24 1 IBM BJ3-60 SP No 3.3V 60ns 400mil SOJ 28/24 1 IBM BJ1-50 SP No 3.3V 50ns 300mil SOJ 26/24 1 IBM BJ1-60 SP No 3.3V 60ns 300mil SOJ 26/24 1 IBM BT1-50 SP No 3.3V 50ns 300mil TSOP 26/24 1 IBM BT1-60 SP No 3.3V 60ns 300mil TSOP 26/24 1 IBM MJ1-50 LP Yes 5.0V 50ns 300mil SOJ 26/24 1 IBM MJ1-60 LP Yes 5.0V 60ns 300mil SOJ 26/24 1 IBM MT1-50 LP Yes 5.0V 50ns 300mil TSOP 26/24 1 IBM MT1-60 LP Yes 5.0V 60ns 300mil TSOP 26/24 1 IBM PJ1-50 LP Yes 3.3V 50ns 300mil SOJ 26/24 1 IBM PJ1-60 LP Yes 3.3V 60ns 300mil SOJ 26/24 1 IBM PT1-50 LP Yes 3.3V 50ns 300mil TSOP 26/24 1 IBM PT1-60 LP Yes 3.3V 60ns 300mil TSOP 26/ SP = Standard Power version (IBM and IBM B); LP = Low Power version (IBM M and IBM P) Page 2 of 28

3 Block Diagram Vss Vcc (5.0 Volt version) I/O0 I/O1 I/O2 I/O3 (to OCDs) Regulator 4 4 V DD (internal) Data In Buffer Data Out Buffer OE & 4 4 Clock Generator A0 A1 A2 A3 A4 A5 A6 A7 A8 10 Column Address Buffer (10) Refresh Controller Refresh Counter (12) A Row Address A10 Buffer (12) 12 A11 12 Row Decoder 10 Column Decoder and I/O Gate Sense Amplifiers 1024 x 4 Memory Array 4096 x 1024 x 4 4 Clock Generator Page 3 of 28

4 Truth Table Function OE Row Address Col Address I/O0 - I/O3 Standby H H X X X X X High Impedance Read L L H L Row Col Data Out Early-Write L L L X Row Col Data In Delayed-Write L L H L H Row Col Data In Read-Modify-Write L L H L L H Row Col Data Out, Data In Fast Page Mode Read Fast Page Mode Write Fast Page Mode Read-Modify-Write 1st Cycle L H L H L Row Col Data Out 2nd Cycle L H L H L N/A Col Data Out 1st Cycle L H L L X Row Col Data In 2nd Cycle L H L L X N/A Col Data In 1st Cycle L H L H L L H Row Col Data Out, Data In 2nd Cycle L H L H L L H N/A Col Data Out, Data In -Only Refresh L H X X Row N/A High Impedance -Before- Refresh H L L H X X N/A High Impedance Hidden Refresh Read L H L L H L Row Col Data Out Write L H L L L H X Row Col Data In Self Refresh (LP version Only) H L L H X X X High Impedance Page 4 of 28

5 Absolute Maximum Ratings Symbol Parameter Rating 3.3 Volt Device 5.0 Volt Device Units Notes V CC Power Supply Voltage -0.5 to to +7.0 V 1 V IN Input Voltage -0.5 to min (V CC +0.5, 4.6) -0.5 to min (V CC +0.5, 7.0) V 1 V OUT Output Voltage -0.5 to min (V CC +0.5, 4.6) -0.5 to min (V CC +0.5, 7.0) V 1 T OPR Operating Temperature 0 to to +70 C 1 T STG Storage Temperature -55 to to +150 C 1 P D Power Dissipation W 1 I OUT Short Circuit Output Current ma 1 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (T A = 0 to 70 C) Symbol Parameter 3.3 Volt Device 5.0 Volt Device Min. Typ. Max. Min. Typ. Max. Units Notes V CC Supply Voltage V 1 Input High Voltage 2.0 V CC V CC V 1, 2 Input Low Voltage V 1, 2 1. All voltages referenced to V SS. 2. may overshoot to V CC + 1.2V for pulse widths of 4.0ns with 3.3 Volt, or V CC + 2.0V for pulse widths of 4.0ns (or V CC + 1.0V for 8.0ns) with 5.0 Volt. Additionally, may undershoot to -2.0V for pulse widths 4.0ns with 3.3 Volt, or to -2.0V for pulse widths 4.0ns (or -1.0V for 8.0ns) with 5.0 Volt. Pulse widths measured at 50% points with amplitude measured peak to DC reference. Capacitance (T A = 25 C, V CC = 3.3V ± 0.3V or V CC = 5.0V ± 0.5V) Symbol Parameter Min. Max. Units Notes C I1 Input Capacitance (A0 - A11) 5 pf 1 C I2 Input Capacitance (,,, OE) 7 pf 1 C O Output Capacitance (I/O0 - I/O3) 7 pf 1 1. Input capacitance measurements made with rise time shift method with = to disable output. Page 5 of 28

6 DC Electrical Characteristics (T A = 0 to +70 C, V CC = 3.3V ± 0.3V or V CC = 5.0V ± 0.5V) Symbol Parameter Min. Max. Units Notes I CC1 Operating Current Average Power Supply Operating Current (,, Address Cycling: t RC = t RC min.) ma 1, 2, 3 I CC2 Standby Current (TTL) Power Supply Standby Current ( = = ) 1 ma I CC3 Only Refresh Current Average Power Supply Current, Only Mode ( Cycling, = : t RC = t RC min) ma 1, 3 I CC4 Fast Page Mode Current Average Power Supply Current ( =,, Address Cycling: t PC = t PC min) ma 1, 2, 3 I CC5 Standby Current (CMOS) Power Supply Standby Current ( = = V CC - 0.2V) SP version 1 LP version 0.1 ma I CC6 Before Refresh Current Average Power Supply Current, Before Mode (,, Cycling: t RC = t RC min) ma 1, 3 I CC7 Self Refresh Current, LP version only Average Power Supply Current during Self Refresh CBR cycle with t S (min); held low; = V CC - 0.2V; Addresses and D IN = V CC - 0.2V or 0.2V. 3.3V V 300 µa I I(L) I O(L) V OH V OL Input Leakage Current Input Leakage Current, any input (0.0 V IN (V CC + 0.3V)), All Other Pins Not Under Test = 0V Output Leakage Current (D OUT is disabled, 0.0 V OUT V CC ) Output Level (TTL) Output H Level Voltage (I OUT = -2.0mA for 3.3V, or I OUT = -5mA for 5.0V) Output Level (TTL) Output L Level Voltage (I OUT = +2.0mA for 3.3V, or I OUT = +4.2mA for 5.0V) µa µa 2.4 V CC V V 1. I CC1, I CC3, I CC4 and I CC6 depend on cycle rate. 2. I CC1 and I CC4 depend on output loading. Specified values are obtained with the output open. 3. Address can be changed once or less while =. In the case of I CC4, it can be changed once or less when =. Page 6 of 28

7 AC Characteristics (T A = 0 to +70 C, V CC = 3.3V ± 0.3V or V CC = 5.0V ± 0.5V) 1. An initial pause of 200µs is required after power-up followed by 8 only refresh cycles before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 before refresh cycles instead of 8 only refresh cycles is required. 2. AC measurements assume t T =5ns. 3. (min.) and (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between and. 4. Valid column addresses are A0 through A9. Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter Units Min. Max. Min. Max. t RC Random Read or Write Cycle Time ns Notes t RP Precharge Time ns t CP Precharge Time ns t Pulse Width 50 10K 60 10K ns t Pulse Width 13 10K 15 10K ns t ASR Row Address Setup Time 0 0 ns t RAH Row Address Hold Time ns t ASC Column Address Setup Time 0 0 ns t CAH Column Address Hold Time ns t RCD to Delay Time ns 1 t RAD to Column Address Delay Time ns 2 t RSH Hold Time ns t CSH Hold Time ns t CRP to Precharge Time 5 5 ns t DZO OE Delay Time from D IN 0 0 ns 3 t DZC Delay Time from D IN 0 0 ns 3 t T Transition Time (Rise and Fall) ns 4 1. Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference point only. If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled by t CAC. 2. Operation within the t RAD (max.) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled by t AA. 3. Either t DZC or t DZO must be satisfied. 4. AC measurements assume t T =5ns. Page 7 of 28

8 Write Cycle Symbol Parameter Min. Max. Min. Max. t WCS Write Command Set Up Time 0 0 ns 1 t WCH Write Command Hold Time ns t WP Write Command Pulse Width ns t RWL Write Command to Lead Time ns t CWL Write Command to Lead Time ns t OED OE to D IN Delay Time ns 2 t DS D IN Setup Time 0 0 ns 3 t DH D IN Hold Time ns 3 1. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. If t RWD t RWD (min), t CWD t CWD (min), t AWD t AWD (min), and t CPW t CPW (min)(fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. 2. Either t CDD or t OED must be satisfied. 3. These parameters are referenced to leading edge in early write cycles and to leading edge in Read-Modify-Write cycles. Units Notes Page 8 of 28

9 Read Cycle Symbol Parameter Units Notes Min. Max. Min. Max. t RAC Access Time from ns 1, 2, 3 t CAC Access Time from ns 1, 3 t AA Access Time from Address ns 2, 3 t OEA Access Time from OE ns 3 t RCS Read Command Setup Time 0 0 ns t RCH Read Command Hold Time to 0 0 ns 4 t RRH Read Command Hold Time to 0 0 ns 4 t RAL Column Address to Lead Time ns t CAL Column Address to Lead Time ns t CLZ to Output in Low-Z 0 0 ns 3 t OH Output Data Hold Time 3 3 ns t OHO Output Data Hold from OE 3 3 ns t OFF Output Buffer Turn-Off Delay ns 5 t OEZ Output Buffer Turn-Off Delay from OE ns 5 t CDD to D IN Delay Time ns 6 1. Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference point only. If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled by t CAC. 2. Operation within the t RAD (max.) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled by t AA. 3. Measured with the specified current load and 100pF. 4. Either t RCH or t RRH must be satisfied for a read cycle. 5. t OFF (max) and t OEZ (max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 6. Either t CDD or t OED must be satisfied. Page 9 of 28

10 Read-Modify-Write Cycle Symbol Parameter Units Min. Max. Min. Max. t RWC Read-Modify-Write Cycle Time ns Notes t RWD to Delay Time ns 1 t CWD to Delay Time ns 1 t AWD Column Address to Delay Time ns 1 t OEH OE Command Hold Time ns 1. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. If t RWD t RWD (min), t CWD t CWD (min), t AWD t AWD (min), and t CPW t CPW (min)(fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. Fast Page Mode Cycle Symbol Parameter Units Min. Max. Min. Max. t PC Fast Page Mode Cycle Time ns Notes t P Fast Page Mode Pulse Width K K ns t CPA Access Time from Precharge ns 1 t CPRH Hold Time from Precharge ns 1. Measured with the specified current load and 100pF. Fast Page Mode Read-Modify-Write Cycle Symbol Parameter Units Notes Min. Max. Min. Max. t Fast Page Mode Read-Modify-Write PRWC Cycle Time ns t CPW Delay Time from Precharge ns 1 1. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. If t RWD t RWD (min), t CWD t CWD (min), t AWD t AWD (min), and t CPW t CPW (min)(fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. Page 10 of 28

11 Refresh Cycle Symbol Parameter Units Min. Max. Min. Max. t Setup Time CSR ( before Refresh Cycle) 5 5 ns t Hold Time CHR ( before Refresh Cycle) ns t Setup Time WRP ( before Refresh Cycle) ns t Hold Time WRH ( before Cycle) ns t RPC Precharge to Hold Time 5 5 ns Notes Self Refresh Cycle - Low Power Version Only Symbol t S t RPS t CHS t CHD Parameter Pulse Width During Self Refresh Cycle Precharge Time During Self Refresh Cycle Hold Time From Rising During Self Refresh Cycle Hold Time From Falling During Self Refresh Cycle Units Notes Min. Max. Min. Max µs ns ns 1, µs 1, 2 1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed in an EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR- Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. 2. If t S >t CHD (min) then t CHD applies. If t S t CHD (min) then t CHS applies. Refresh Symbol Parameter Min. Max. Min. Max. Units Notes t REF Refresh Period SP version LP version ms cycles. Page 11 of 28

12 Read Cycle t RC t t RP t CSH t RCD t RSH t CRP t t RAD t RAL t CAL t ASR t RAH t ASC t CAH Address Row Column t RCS t RRH t RCH t AA OE t OEA t DZC t CDD D IN t DZO t OED t CAC t OFF t CLZ t OEZ D OUT V OH V OL Valid Data Out t RAC t OH : H : or L t OHO Page 12 of 28

13 Write Cycle (Early Write) t RC t t RP t RCD t CSH t CRP t RSH t t RAD t ASR t RAH t ASC t CAH Address Row Column t WCS t WP t WCH OE t DS t DH D IN Valid Data In D OUT V OH V OL : H or L Page 13 of 28

14 Write Cycle (Delayed Write) t RC t t RP t CSH t RCD t RSH t CRP t t RAD t ASR t RAH t ASC t CAH Address Row Column t RCS t CWL t WP t RWL OE t OEH t OED t DH t DZO t DS D IN t DZC Valid Data In t OEZ t CLZ D OUT V OH V OL t OEA * : H or L * t OEH greater than or equal to t CWL Page 14 of 28

15 Read-Modify-Write Cycle t RWC t t RP t CSH t RCD t RSH t CRP t RAD t t ASR t RAH t ASC t CAH Address Row Column t CWD t RWL t AWD t CWL t RWD t AA t WP t RCS t OEH OE t OEA t DZC tdzo t DH t DS D IN D IN t CLZ t CAC t OED t OEZ D OUT V OH V OL D OUT * t RAC : H or L t OHO *t OEH greater than or equal to t CWL Page 15 of 28

16 Fast Page Mode Read Cycle t P t RP t CPRH t PC t RCD t CP t CP t RSH t CRP t t t t CSH t CAL t RAL t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 Column 2 Column n t RAD t RCS t RCH t RCS t RCH t RCS trch t RRH t AA t AA t AA t OEA t CPA t CPA OE t OEA t OEA t DZC t OHO t OH t DZO t DZC t OHO t OH t DZO t DZC t OHO t OH t CDD t DZO t OED t OED t OED D IN t CAC t CAC t CAC D OUT V OH t RAC t CLZ t OFF t OFF t OFF t OEZ t OEZ t OEZ t CLZ t CLZ D OUT 1 D OUT 2 D OUT N V OL : H or L Page 16 of 28

17 Fast Page Mode Write Cycle t P t RP t PC t RCD t CP t CP t RSH t CRP t t t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH t CSH Address Row Column 1 Column 2 Column n t RAD t CWL t CWL t CWL t RWL t WCH t WCH t WCH t WCS t WCS t WCS t WP t WP t WP OE t DS t DH t DS t DH t DS t DH D IN D IN 1 D IN 2 D IN N D OUT V OH V OL : H or L Page 17 of 28

18 Fast Page Mode Read-Modify-Write Cycle t P t RP t PRWC t RCD t CP t CP t RSH t CRP t t t t ASR t RAH t CSH t CWL t CWL t CWL t ASC t CAH t ASC tcah t ASC t CAH t RWL Address Row Column 1 Column 2 Column n t RCS t RWD t AWD t CWD t RCS t WP t CPW t AWD t CWD t RCS t WP t CPW t AWD t CWD t WP t CAC t CAC t CAC t RAD t AA t AA t CPA t AA t CPA OE t OEH t OEH t OEH t DZC t DZO t OEA toea t DH t DH t DS t DS t OED t OED t OED t OEA t DH t DS D IN D IN 1 D IN 2 D IN N t CLZ t OEZ t OHO t CLZ t OEZ t OHO t CLZ t OEZ t OHO D OUT V OH V OL * t RAC D OUT 1 D OUT 2 D OUT N : H or L *t OEH greater than or equal to t CWL Page 18 of 28

19 Only Refresh Cycle t RC t t RP t RPC t CRP t ASR t RAH Address Row D OUT V OH V OL : H or L NOTE:, OE and D IN are H or L Page 19 of 28

20 Before Refresh Cycle t RC t t RP t RPC t CP t CSR t CHR t RPC t CSR t WRH t WRH t WRP t WRP OE t OED t CDD D IN V OH V OL t OEZ t OFF D OUT V OH V OL : H or L NOTE: Address is H or L Page 20 of 28

21 Hidden Refresh Cycle (Read) t RC t RC t RP t RP t t t RCD t RSH t CHR t CRP t RAD t RAL t WRH t ASR t ASC t WRP t RAH t CAH Address Row Column t RCS t RRH t AA OE t OEA t DZC t CDD D IN t DZO t CAC t OFF t OED t CLZ t OEZ D OUT V OH V OL Valid Data Out t RAC t OH : H or L t OHO Page 21 of 28

22 Hidden Refresh Cycle (Write) t RC t RC t RP t RP t t t RCD t RSH t CHR t CRP t ASR t RAH t ASC t CAH Address Row Column t WRP t WCS t WCH t WRH t WP OE t DS t DH D IN Valid Data D OUT V OH V OL : H or L Page 22 of 28

23 Self Refresh Cycle (Sleep Mode) - Low Power version only t S t RPS t RPC t CP t CSR t CHD t CHS t CRP t WRP t WRH t OFF D OUT V OH V OL : H or L NOTES: 1. Address and OE are H or L 2. Once (min) is provided and remains low, the DRAM will be in Self Refresh, commonly known as Sleep Mode. 3. If t S > t CHD (min) then t CHD applies. If t S t CHD (min) then t CHS applies. Page 23 of 28

24 Package Dimensions (300 mil; 26/24 lead; Small Outline J-Lead) 3.50 ± Min ± Min ± Basic Basic Pin #1 ID Lead # Seating Plane Basic NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale. Page 24 of 28

25 Package Dimensions (400 mil; 28/24 lead; Small Outline J-Lead) ± ± ± ± Min 0.76 Min Pin #1 ID Lead # Basic Seating Plane Basic NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale. Page 25 of 28

26 Package Dimensions (300 mil; 26/24 lead; Thin Small Outline Package) ± 0.10 Detail A 7.62 ± ± 0.20 Lead # Seating Plane Basic 0.40 ± REF Detail A 1.20 Max 1.00 ± Basic Gage Plane ± 0.1 NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale. Page 26 of 28

27 Revision Log Revision Contents Of Modification 03/15/94 Initial Release 1. Combine the 3.3V and the 5.0V specifications 09/06/94 2. Remove Test Address Compression 1. Iout changed to +2.0 ma and -2.0 ma in DC Electrical Characteristics table. 2. Packaging diagrams modified to clarify lead thickness and standoff height. 3. t RPC min changed from 0 to 5ns. 4. t CHR min changed from 20 to 10ns. 5. Currents in DC Electrical Characteristics table revised. 6. Test Modes and Test Circuit Diagram removed. 7. Rename t 11/15/95 ODD to t OED. 8. t OED, t CDD, t OEZ, and t OFF min changed from 20 to 15ns, for the 70ns part. 9. t RRH min changed from 5 to 0ns for all speed sorts. 10. t OEH min changed from 20 to 15ns for the 70ns part. 11. t CSR min changed from 10 to 5ns for all speed sorts. 12. t CAH min changed from 15 to 10ns on 60 and 70ns parts. 13. t OFF max changed from 20 to 15ns for 70ns parts. 12/10/95 09/01/96 03/19/97 1. The Low Power and Standard Power Specifications were combined. ES# 43G9611 and ES# were combined into ES#. 2. Added Die Rev E part numbers. 3. t DH was reduced from 15ns to 12ns for the -60 speed sort. 4. t CHD was added to the Self Refresh Cycle with a value of 350µs for all speed sorts. 5. The Self Refresh diagram was changed to allow to go high t CHD after falls entering a Self Refresh. 6. The CBR timing diagram was changed to allow to remain low for back-to-back CBR cycles. 7. for the Hidden Refresh Write cycle in the Truth Table was changed from L to H. 1. I CC2 was changed from 2mA to 1mA. 2. I I(L) and I O(L) were altered from +/- 10uA to +/- 5uA. 3. t T was initially at a max of 30ns. It has been modified to 50ns for all speed sorts. 4. t CPA was decreased from 30ns to 28ns for the -50 speed sort. 5. t P max of 125K was raised to 200K for all speed sorts. 6. t RP was changed from 35ns to 30ns for the -50 speed sort. 1. for the Hidden Refresh Write cycle in the Truth Table was changed from H to L H. 2. t OED was moved from the Common Parameters table to the Write Cycle Parameters Table. 3. t ODD in the before timing diagram was renamed t OED. 4. The -70 speed sort and timings were removed. 5. I cc1, I cc3, I cc6 for the -50 speed sort were reduced from 85mA to 50mA. 6. I cc4 for the -50 speed sort was reduced from 75mA to 25mA. 7. I cc1, I cc3, I cc6 for the -60 speed sort were reduced from 75mA to 45mA. 8. I cc4 for the -60 speed sort was reduced from 65mA to 25mA. 04/23/97 1. I cc5 was changed from 200µA to 100µA for the Low Power Die Rev F Parts. Page 27 of 28

28 International Business Machines Corp.1997 Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at IBM Microelectronics manufacturing is ISO 9000 compliant.

IBM IBM M IBM B IBM P 4M x 4 11/11 EDO DRAM

IBM IBM M IBM B IBM P 4M x 4 11/11 EDO DRAM IBM01174054M x 411/11, 5.0V, EDOMMDD64DSU-001012331. IBM0117405P4M x 411/11, 3.3V, EDO, LP, SRMMDD64DSU-001012331. IBM0117405M4M x 411/11, 5.0V, EDO, LP, SRMMDD64DSU-001012331. IBM0117405B4M x 411/11,