HM514400B/BL Series HM514400C/CL Series

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1 ADE A (Z) HM514400B/BL Series HM514400C/CL Series 1,048,576-word 4-bit Dynamic Random Access Memory Rev. 1.0 Nov. 29, 1994 The Hitachi HM514400B/BL, HM514400C/CL are CMOS dynamic RAM organized 1,048,576- word 4-bit. HM514400B/BL, HM514400C/CL have realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM514400B/BL, HM514400C/CL offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514400B/BL, HM514400C/CL to be packaged in standard 300-mil 26-pin plastic SOJ, standard 400-mil 20-pin plastic ZIP and 26- pin plastic TSOP II. Test function Battery back up operation HM514400BL Series (L-version) HM514400CL Series (L-version) Features Single 5 V (±10%) High speed Access time 60 ns/70 ns/80 ns (max) Low power dissipation Active mode 605 mw/550 mw/495 mw (max) Standby mode 11 mw (max) 0.55 mw (max) (L-version) Fast page mode capability 1024 refresh cycles : 16 ms 1024 refresh cycles : 128 ms (L-version) 3 variations of refresh -only refresh -before- refresh Hidden refresh

2 Ordering Information Access Type No. time Package HM514400BS-6 60 ns 300-mil 26-pin HM514400BS-7 70 ns plastic SOJ HM514400BS-8 80 ns (CP-26/20D) HM514400BLS-6 60 ns HM514400BLS-7 70 ns HM514400BLS-8 80 ns HM514400CS-6 60 ns HM514400CS-7 70 ns HM514400CS-8 80 ns HM514400CLS-6 60 ns HM514400CLS-7 70 ns HM514400CLS-8 80 ns HM514400BZ-6 60 ns 400-mil 20-pin HM514400BZ-7 70 ns plastic ZIP HM514400BZ-8 80 ns (ZP-20) HM514400BLZ-6 60 ns HM514400BLZ-7 70 ns HM514400BLZ-8 80 ns Access Type No. time Package HM514400CZ-6 60 ns 400-mil 20-pin HM514400CZ-7 70 ns plastic ZIP HM514400CZ-8 80 ns (ZP-20) HM514400CLZ-6 60 ns HM514400CLZ-7 70 ns HM514400CLZ-8 80 ns HM514400BTT-6 60 ns 26-pin HM514400BTT-7 70 ns plastic TSOPII HM514400BTT-8 80 ns (TTP-26/20D) HM514400BLTT-6 60 ns HM514400BLTT-7 70 ns HM514400BLTT-8 80 ns HM514400CTT-6 60 ns HM514400CTT-7 70 ns HM514400CTT-8 80 ns HM514400CLTT-6 60 ns HM514400CLTT-7 70 ns HM514400CLTT-8 80 ns 2

3 Pin Arrangement 3 HM514400B/BL, HM514400C/CL Series I/O1 I/O2 A9 A0 A1 A2 A3 V CC V I/O4 I/O3 A8 A7 A6 A5 A4 SS HM514400BS/BLS Series HM514400CS/CLS Series (Top view) HM514400BZ/BLZ Series HM514400CZ/CLZ Series (Bottom view) HM514400BTT/BLTT Series HM514400CTT/CLTT Series (Top view) I/O1 I/O2 A9 A0 A1 A2 A3 V CC V I/O4 I/O3 A8 A7 A6 A5 A4 SS CC I/O3 V I/O2 A0 A2 V A5 A7 I/O4 I/O1 A9 A1 A3 A4 A6 A8 SS

4 Pin Description Pin name Function A0 to A9 input A0 to A9 Refresh address input I/O1 to I/O4 Data-in/Data-out address strobe address strobe Read/Write enable Output enable V CC Power (+5 V) V SS Ground 4

5 Block Diagram Control Circuit Control Circuit Control Circuit Control Circuit I/O1 I/O2 I/O3 I/O4 I/O1 Buffer I/O2 Buffer I/O3 Buffer I/O4 Buffer I/O Bus & Decoder I/O Bus & Decoder I/O Bus & Decoder I/O Bus & Decoder I/O Bus & Decoder I/O Bus & Decoder I/O Bus & Decoder I/O Bus & Decoder Decoder & Peripheral Circuit Buffer Buffer A0 A9 5

6 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS V T 1.0 to +7.0 V Supply voltage relative to V SS V CC 1.0 to +7.0 V Short circuit output current Iout 50 ma Power dissipation P T 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg 55 to +125 C Recommended DC Operating Conditions (Ta = 0 to +70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage V SS V V CC V 1 Input high voltage V IH V 1 Input low voltage V IL V 1 Note: 1. All voltage referred to V SS. 6

7 DC Characteristics (Ta = 0 to +70 C, V CC = 5 V ± 10%, V SS = 0 V) HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating current I CC ma, cycling 1, 2 t RC = min Standby current I CC ma TTL interface, = V IH = ma CMOS interface, V CC 0.2 V = Standby current I CC µa CMOS interface 4 (L-version), =V IH,, and = V IH or V IL = -only I CC ma t RC = min 2 refresh current Standby current I CC ma = V IH, = V IL 1 = enable -before- I CC ma t RC = min refresh current Fast page mode I CC ma t PC = min 1, 3 current Battery back up I CC µa t RC = 125 µs 4 current t 1 µs (Standby with = V IH, = V IL CBR refresh), and (L-version) = V IH or V IL = Input leakage current I LI µa 0 V Vin 7 V Output leakage I LO µa 0 V Vout 7 V current = disable Output high voltage V OH 2.4 V CC 2.4 V CC 2.4 V CC V High Iout = 5 ma Output low voltage V OL V Low Iout = 4.2 ma Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. can be changed twice or less while = V IL. 3. can be changed once or less while = V IH. 4. V CC 0.2 V V IH 6.5 V and 0 V V IL 0.2 V. 7

8 Capacitance (Ta = 25 C, V CC = 5 V ± 10%) Parameter Symbol Typ Max Unit Notes Input capacitance () C I1 5 pf 1 Input capacitance (Clocks) C I2 7 pf 1 Output capacitance C I/O 7 pf 1, 2 (Data-in, Data-out) Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. = V IH to disable. AC Characteristics (Ta = 0 to +70 C, V CC = 5 V ± 10%, V SS = 0 V) Test Conditions Input rise and fall times : 5 ns Input timing reference levels : 0.8 V, 2.4 V Output load : 2 TTL gate + C L (100 pf) (Including scope and jig) *1, *14, *15, *16 8

9 Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC ns precharge time ns pulse width t ns 19 pulse width t ns 20 address setup time t ASR ns address hold time t RAH ns address setup time t ASC ns address hold time t CAH ns to delay time t RCD ns 8 to column address delay time t RAD ns 9 hold time t RSH ns hold time t CSH ns to precharge time t CRP ns to delay time t ODD ns delay time from t DZO ns setup time from t DZC ns Transition time (rise and fall) t T ns 7 Refresh period t REF ms Refresh period (L-version) t REF ms 9

10 Read Cycle HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from t RAC ns 2, 3, 17 Access time from t CAC ns 3, 4, 13, 17 Access time from address t AA ns 3, 5, 13, 17 Access time from t OAC ns 3, 17 Read command setup time t RCS ns Read command hold time to t RCH ns 18 Read command hold time to t RRH ns 18 address to lead time t RAL ns Output buffer turn-off time t OFF ns 6 Output buffer turn-off time to t OFF ns 6 to delay time t CDD ns pulse width t P ns Write Cycle HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS ns 10 Write command hold time t WCH ns Write command pulse width t WP ns Write command to lead time t RWL ns Write command to lead time t CWL ns Data-in setup time t DS ns 11 Data-in hold time t DH ns 11 10

11 Read-Modify-Write Cycle HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC ns to delay time t RWD ns 10 to delay time t CWD ns 10 address to delay time t AWD ns 10 hold time from t H ns Refresh Cycle HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes setup time (CBR refresh cycle) t CSR ns hold time (CBR refresh cycle) t CHR ns precharge to hold time C ns precharge time in normal mode t CPN ns Fast Page Mode Cycle HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC ns Fast page mode precharge time t CP ns Fast page mode pulse width t C ns 12 Access time from precharge t ACP ns 3, 13, 17 hold time from precharge t RHCP ns 11

12 Fast Page Mode Read-Modify-Write Cycle HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode read-modify-write t PCM ns cycle time Fast page mode read-modify-write t CPW ns 10 cycle precharge to delay time Test Mode Cycle HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes Test mode setup time t WS ns Test mode hold time t WH ns Counter Test Cycle HM514400B/BL, HM514400C/CL Parameter Symbol Min Max Min Max Min Max Unit Notes precharge time in counter test t CPT ns cycle 12

13 Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD t RCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pf. 4. Assumes that t RCD t RCD (max) and t RAD t RAD (max). 5. Assumes that t RCD t RCD (max) and t RAD t RAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and V IL. 8. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only, if t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by t CAC. 9. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only, if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA. 10. t WCS, t RWD, t CWD, t CPW and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD t RWD (min), t CWD t CWD (min), t CPW t CPW (min) and t AWD t AWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to leading edge in an early write cycle and to leading edge in a delayed write or read-modify-write cycle. 12. t C defines pulse width in fast page mode cycles. 13. Access time is determined by the longest among t AA, t CAC and t ACP. 14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization cycles (-only refresh cycle or -before- refresh cycle). If the internal refresh counter is used, a minimum of eight -before- refresh cycles is required. 15. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 2-bit test function controlled by control address bits CA0. This test mode operation can be performed by -and--before- (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. In order to end this test mode operation, perform a -only refresh cycle or a -before- refresh cycle. 17. In a test mode read cycle, the value of t RAC, t AA, t CAC, t OAC and t ACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. Either t RCH or t RRH must be satisfied 19. t (min) = t RWD (min) + t RWL (min) + t T in read-modify-write cycle. 20. t (min) = t CWD (min) + t CWL (min) + t T in read-modify-write cycle. 13

14 Timing Waveforms *21 Read Cycle t RC t t T t RCD t RSH t t CRP t CSH t RAD t RAL t ASR t RAH t ASC t CAH t RCS t RCH t CAC t AA t OFF1 t RRH t RAC t DZC t OAC t CDD t OFF2 t DZO t ODD t À@ À@ À@ À@ À Notes: 21. H or L (H: V IH (min) V IN V IH (max), L: V IL (min) V IN V IL (max)) Invalid 14

15 Early Write Cycle t RC t t T t RCD t RSH t t CRP t CSH t ASR t RAH t ASC t CAH t WCS t WCH t DS t DH * * ** t WCS t WCS (min) : H or L 15

16 Delayed Write Cycle t RC t t T t RCD t CSH t t RSH t CRP t ASR trah t ASC t CAH t CWL t RWL t RCS t WP t DS t DH t DZC t DZO t ODD t H Invalid * t OFF2 * * Invalid comes out, when is low level. 16

17 Read-Modify-Write Cycle t RWC t t T t RCD t t CRP t RAD t ASR trah t ASC t CAH t RCS t CWD t CWL t AWD t RWL t WP t RWD t AA t RAC t DZC t CAC t DS t DH t OAC t OFF2 t H t DZO t ODD t P 17

18 Hidden Refresh Cycle t t RC t RC t RC t t (Read) (Refresh) (Refresh) t T t RCD t RSH t CHR t CRP t t ASR t RAD t ASC t RAH t RAL t CAH t RCH t RRH t RCS t RAC t CAC t AA t OFF1 t DZC t OFF2 t CDD tdzo t OAC todd 18

19 Fast Page Mode Read Cycle t C t RHCP t T t CSH t PC t RCD t t CP t t RSH t CP t t CRP t ASR t RAL trah t RAD t ASC tcah t ASC t CAH t ASC t CAH trcs trcs t RRH trcs t RCH t RCH trch tdzc t CDD t DZC t CDD t DZC t CDD t RAC t ODD t CAC t AA AA t CAC t CAC t AA tt ACP t ACP t ODD t OFF1 t DZO t OAC t OFF2 t OFF1 t DZO t OFF1 t DZO t ODD t OFF2 t OAC t OFF2 t P t P t P t OAC 19

20 Fast Page Mode Early Write Cycle t C t T t CSH t PC t RSH t RCD t t CP t tcp t t CRP t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH t WCS t WCH t WCS t WCH t WCH t WCS t DS t DH t DS t DH t DS t DH * : H or L 20

21 t T t CSH t PC t RSH HM514400B/BL, HM514400C/CL Series Fast Page Mode Delayed Write Cycle t C t RCD t t CP t t CP t t CRP t ASR t CAH t ASC t ASC t RAH tcah t ASC t CAH t CWL tcwl t CWL t RCS twp t WP t WP t RWL tdh tds t RCS t DS tdh t RCS t DS t DH t H t ODD 21

22 Fast Page Mode Read-Modify-Write Cycle t C t RCD t PCM t T t CP t CP t CRP t t t t RAD t RAH t ACP t t t CAH ASR CAH t CAH t t t ASC ASC ASC t RCS t AWD t CWD t RWD t CWL t WP t RCS t AWD tcwd t CPW t CWL twp trcs t CPW t AWD t CWD t CWL t RWL t WP t DZC t CAC t DS t DH t DZC tcac t DS t DH tacp t DZC t DS t DH taa t RAC t OAC t AA t CAC t DZO t AA toac t H t H t OAC t H t DZO t OFF2 t OFF2 t DZO t OFF2 t P t ODD t P t ODD t P t ODD 22

23 Test Mode Cycle Set Cycle** Test Mode Cycle *,** Reset Cycle Normal Mode * ** CBR or -only refresh,, : H or L Test Mode Set Cycle -and--before -Refresh Cycle t RC t C t CSR t CHR C t CRP t T t CPN@ t WS t WH t CPN t OFF1 23

24 -Before- Refresh Cycle t RC t t T t CPN t CSR t CHR t CPN C tcrp C t WS t WH t OFF1 24

25 -Only Refresh Cycle t RC t t T t CRP C t CRP t ASR t RAH * ** Refresh address : A0 A9 (AX0 AX9) : H or L 25

26 -Before- Refresh Counter Check Cycle (Read) t t T t CSR t CHR t CPT t RSH t t CRP t ASC t CAH t RCH t RRH t WS t WH t RCS tdzc t CDD t CAC t AA t OFF1 t DZO t OAC t P t OFF2 t ODD 26

27 -Before- Refresh Counter Check Cycle (Write) HM514400B/BL, HM514400C/CL Series t t T t CSR t CHR t CPT t RSH t CRP t t ASC t CAH t WS twh t WCS t WCH t DS t DH 27

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