STK20C x 8 nvsram QuantumTrap CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Designs

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Roberta Blake
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1 512 x 8 nvsram QuantumTrap CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Designs FATURS 25ns, 35ns and 45ns Access Times STOR to Nonvolatile lements Initiated by Hardware RCALL to SRAM Initiated by Hardware or Power Restore Automatic STOR Timing 10mA Typical I CC at 200ns Cycle Time Unlimited RAD, RIT and RCALL Cycles 1,000,000 STOR Cycles to Nonvolatile lements 100-Year Data Retention over Full Industrial Temperature Range Commercial and Industrial Temperatures DSCRIPTION The Simtek is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in nonvolatile elements. Data may easily be transferred from the SRAM to the Nonvolatile lements (the STOR operation), or from the Nonvolatile lements to the SRAM (the RCALL operation), using the pin. Transfers from the Nonvolatile lements to the SRAM (the RCALL operation) also take place automatically on restoration of power. The combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. The features industry-standard pinout for nonvolatile RAMs in a 28-pin 600 mil plastic DIP. BLOCK DIARAM A 5 A 6 A 7 A 8 RO DCODR STATIC RAM ARRAY 16 x 256 Quantum Trap 16 x 256 STOR RCALL PIN CONFIURATIONS NC A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 DQ 0 DQ 1 DQ 2 V SS V CC NC A 8 NC NC NC DQ 7 DQ 6 DQ 5 DQ 4 DQ PDIP DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 INPUT BUFFRS COLUMN I/O COLUMN DC A 3 A 0 A 1 A 2 A 4 STOR/ RCALL CONTROL PIN NAMS A 0 - A 8 Address Inputs rite nable DQ 0 - DQ 7 Data In/Out Chip nable Output nable Nonvolatile nable V CC Power (+ 5V) V SS round March Document Control # ML0001 rev 0.2

2 ABSOLUT MAXIMUM RATINS a Voltage on Input Relative to round V to 7.0V Voltage on Input Relative to V SS V to (V CC + 0.5V) Voltage on DQ V to (V CC + 0.5V) Temperature under Bias C to 125 C Storage Temperature C to 150 C Power Dissipation DC Output Current (1 output at a time, 1s duration) mA Note a: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. xposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTRISTICS (V CC = 5.0V ± 10%) SYMBOL PARAMTR COMMRCIAL INDUSTRIAL MIN MAX MIN MAX UNITS NOTS I CC 1 b Average V CC Current ma ma ma t AVAV = 25ns t AVAV = 35ns t AVAV = 45ns I CC 2 c Average V CC Current during STOR 3 3 ma All Inputs Don t Care, V CC = max I CC 3 b Average V CC Current at t AVAV = 200ns 5V, 25 C, Typical ma (V CC 0.2V) All Others Cycling, CMOS Levels I SB 1 d Average V CC Current (Standby, Cycling TTL Input Levels) ma ma ma t AVAV = 25ns, V IH t AVAV = 35ns, V IH t AVAV = 45ns, V IH I SB 2 d V CC Standby Current (Standby, Stable CMOS Input Levels) μa (V CC 0.2V) All Others V IN 0.2V or (V CC 0.2V) I ILK Input Leakage Current ±1 ±1 μa V CC = max V IN = V SS to V CC I OLK Off-State Output Leakage Current ±5 ±5 μa V CC = max V IN = V SS to V CC, or V IH V IH Input Logic 1 Voltage 2.2 V CC V CC +.5 V All Inputs V IL Input Logic 0 Voltage V SS V SS V All Inputs V OH Output Logic 1 Voltage V I OUT = 4mA V OL Output Logic 0 Voltage V I OUT = 8mA T A Operating Temperature C Note b: I CC 1 and I are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. CC3 Note c: I CC 2 is the average current required for the duration of the STOR cycle (t STOR ). Note d: V IH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TST CONDITIONS Input Pulse Levels V to 3V Input Rise and Fall Times ns Input and Output Timing Reference Levels V Output Load See Figure 1 5.0V CAPACITANC e (T A = 25 C, f = 1.0MHz) 480 Ohms SYMBOL PARAMTR MAX UNITS CONDITIONS C IN Input Capacitance 8 pf ΔV = 0 to 3V C OUT Output Capacitance 7 pf ΔV = 0 to 3V Note e: These parameters are guaranteed but not tested. OUTPUT 255 Ohms 30 pf INCLUDIN SCOP AND FIXTUR Figure 1: AC Output Loading March Document Control # ML0001 rev 0.2

3 SRAM RAD CYCLS #1 & #2 (V CC = 5.0V ± 10%) NO. SYMBOLS PARAMTR UNITS #1, #2 Alt. MIN MAX MIN MAX MIN MAX 1 t LQV t ACS Chip nable Access Time ns 2 t f AVAV t RC Read Cycle Time ns 3 t g AVQV t AA Address Access Time ns 4 t LQV t O Output nable to Data Valid ns 5 t AXQX g t OH Output Hold after Address Change ns 6 t LQX t LZ Chip nable to Output Active ns 7 t HQZ h t HZ Chip Disable to Output Inactive ns 8 t LQX t OLZ Output nable to Output Active ns 9 t HQZ h 10 t LICCH e t OHZ Output Disable to Output Inactive ns t PA Chip nable to Power Active ns 11 t d, e HICCL t PS Chip Disable to Power Standby ns Note f: must be high during SRAM RAD cycles and low during SRAM RIT cycles. must be high during entire cycle. Note g: I/O state assumes, < V IL, > V IH, and V IH ; device is continuously selected. Note h: Measured + 200mV from steady state output voltage. SRAM RAD CYCL #1: Address Controlled f, g 2 t AVAV ADDRSS 5 t AXQX 3 t AVQV DATA VALID SRAM RAD CYCL #2: Controlled f 2 t AVAV ADDRSS 6 t LQX 1 t LQV 11 t HICCL 7 t HQZ 8 t LQX 4 t LQV 9 t HQZ DATA VALID I CC STANDBY 10 t LICCH ACTIV March Document Control # ML0001 rev 0.2

4 SRAM RIT CYCLS #1 & #2 (V CC = 5.0V ± 10%) NO. SYMBOLS PARAMTR #1 #2 Alt. MIN MAX MIN MAX MIN MAX UNITS 12 t AVAV t AVAV t C rite Cycle Time ns 13 t LH t LH t P rite Pulse idth ns 14 t LH t LH t C Chip nable to nd of rite ns 15 t DVH t DVH t D Data Set-up to nd of rite ns 16 t HDX t HDX t DH Data Hold after nd of rite ns 17 t AVH t AVH t A Address Set-up to nd of rite ns 18 t AVL t AVL t AS Address Set-up to Start of rite ns 19 t HAX t HAX t R Address Hold after nd of rite ns 20 t LQZ h, i t Z rite nable to Output Disable ns 21 t HQX t O Output Active after nd of rite ns Note i: If is low when goes low, the outputs remain in the high-impedance state. Note j: or must be V IH during address transitions. V IH. SRAM RIT CYCL #1: Controlled j ADDRSS 12 t AVAV 14 t LH 19 t HAX 18 t AVL 17 t AVH 13 t LH 15 t DVH 16 t HDX DATA IN DATA OUT PRVIOUS DATA 20 t LQZ DATA VALID HIH IMPDANC 21 t HQX SRAM RIT CYCL #2: Controlled j ADDRSS 12 t AVAV t AVL t LH t HAX 17 t AVH 13 t LH 15 t DVH 16 t HDX DATA IN DATA VALID DATA OUT HIH IMPDANC March Document Control # ML0001 rev 0.2

5 MOD SLCTION MOD POR H X X X Not Selected Standby L H L H Read SRAM Active L L X H rite SRAM Active L H L L Nonvolatile RCALL k Active L L H L Nonvolatile STOR I CC2 L L L H L H L X No Operation Active Note k: An automatic RCALL takes place at power up, starting when V CC exceeds 4.25V and taking t RSTOR. STOR CYCLS #1 & #2 (V CC = 5.0V ± 10%) NO. SYMBOLS #1 #2 Alt. PARAMTR MIN MAX UNITS 22 t l LQX t LQX t STOR STOR Cycle Time 10 ms 23 t m LNH t LNH t C STOR Initiation Cycle Time 20 ns 24 t HNL Output Disable Set-up to Fall 0 ns 25 t HL Output Disable Set-up to Fall 0 ns 26 t NLL t NLL Set-up 0 ns 27 t LL Chip nable Set-up 0 ns 28 t LL rite nable Set-up 0 ns Note l: Measured with and both returned high, and returned low. STOR cycles are inhibited below 4.0V. Note m: Once t C has been satisfied by,, and, the STOR cycle is completed automatically. Any of,, or may be used to terminate the STOR initiation cycle. Note n: If is low for any period of time in which is high while and are low, then a RCALL cycle may be initiated. STOR CYCL #1: Controlled n t HNL t NLL t LNH 27 t LL 22 HIH IMPDANC t LQX STOR CYCL #2: Controlled n 25 t HL HIH IMPDANC 26 t NLL 28 t LL 23 t LNH 22 t LQX March Document Control # ML0001 rev 0.2

6 STOR INHIBIT/POR-UP RCALL (V CC = 5.0V + 10%) SYMBOLS NO. PARAMTR UNITS NOTS Standard MIN MAX 29 t RSTOR Power-up RCALL Duration 550 μs o 30 t STOR STOR Cycle Duration 10 ms 31 V SITCH Low Voltage Trigger Level V 32 V RST Low Voltage Reset Level 3.6 V Note o: t RSTOR starts from the time V CC rises above V SITCH. STOR INHIBIT/POR-UP RCALL V CC 5V 31 V SITCH 32 V RST STOR INHIBIT POR-UP RCALL 29 t RSTOR POR-UP RCALL BRON OUT STOR INHIBIT BRON OUT STOR INHIBIT BRON OUT STOR INHIBIT NO RCALL (V CC DID NOT O BLO V RST ) NO RCALL (V CC DID NOT O BLO V RST ) RCALL HN V CC RTURNS ABOV V SITCH March Document Control # ML0001 rev 0.2

7 RCALL CYCLS #1, #2 & #3 (V CC = 5.0V ± 10%) NO. SYMBOLS #1 #2 #3 PARAMTR MIN MAX UNITS 33 t NLQX p t LQXR t LQXR RCALL Cycle Time 20 μs 34 t NLNH q t LNHR t LNH RCALL Initiation Cycle Time 20 ns 35 t NLL t NLL Set-up 0 ns 36 t LNL t LL Output nable Set-up 0 ns 37 t HNL t HL t HL rite nable Set-up 0 ns 38 t LNL t LL t LL Chip nable Set-up 0 ns 39 t NLQZ Fall to Outputs Inactive 20 ns 40 t RSTOR Power-up RCALL Duration 550 μs Note p: Note q: Note r: Measured with and both high, and and low. Once t NLNH has been satisfied by,, and, the RCALL cycle is completed automatically. Any of, or may be used to terminate the RCALL initiation cycle. If is low at any point in which both and are low and is high, then a STOR cycle will be initiated instead of a RCALL. RCALL CYCL #1: Controlled n 36 t LNL 34 t NLNH 37 t HNL 38 t LNL 39 t NLQZ 33 t NLQX HIH IMPDANC RCALL CYCL #2: Controlled n 36 t LL 35 t NLL 37 t HL 34 t LNHR HIH IMPDANC 33 t LQXR RCALL CYCL #3: Controlled n, r 37 t HL 38 t LL 35 t NLL HIH IMPDANC 34 t LNH 33 t LQXR March Document Control # ML0001 rev 0.2

8 March Document Control # ML0001 rev 0.2

9 DVIC OPRATION The has two modes of operation: SRAM mode and nonvolatile mode, determined by the state of the pin. hen in SRAM mode, the memory operates as a standard fast static RAM. hile in nonvolatile mode, data is transferred in parallel from SRAM to Nonvolatile lements or from Nonvolatile lements to SRAM. NOIS CONSIDRATIONS Note that the is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1μF connected between V CC and V SS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM RAD The performs a RAD cycle whenever and are low and and are high. The address specified on pins A 0-8 determines which of the 512 data bytes will be accessed. hen the RAD is initiated by an address transition, the outputs will be valid after a delay of t AVQV (RAD cycle #1). If the RAD is initiated by or, the outputs will be valid at t LQV or at t LQV, whichever is later (RAD cycle #2). The data outputs will repeatedly respond to address changes within the t AVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until or is brought high or or is brought low. SRAM RIT A RIT cycle is performed whenever and are low and is high. The address inputs must be stable prior to entering the RIT cycle and must remain stable until either or goes high at the end of the cycle. The data on pins DQ 0-7 will be written into the memory if it is valid t DVH before the end of a controlled RIT or t DVH before the end of an controlled RIT. It is recommended that be kept high during the entire RIT cycle to avoid data bus contention on the common I/O lines. If is left low, internal circuitry will turn off the output buffers t LQZ after goes low. NONVOLATIL STOR A STOR cycle is performed when, and and low and is high. hile any sequence that achieves this state will initiate a STOR, only initiation (STOR cycle #1) and initiation (STOR cycle #2) are practical without risking an unintentional SRAM RIT that would disturb SRAM data. During a STOR cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STOR cycle is initiated, further input and output are disabled and the DQ 0-7 pins are tri-stated until the cycle is complete. If and are low and and are high at the end of the cycle, a RAD will be performed and the outputs will go active, signaling the end of the STOR. NONVOLATIL RCALL A RCALL cycle is performed when, and are low and is high. Like the STOR cycle, RCALL is initiated when the last of the four clock signals goes to the RCALL state. Once initiated, the RCALL cycle will take t NLQX to complete, during which all inputs are ignored. hen the RCALL completes, any RAD or RIT state on the input pins will take effect. Internally, RCALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. The RCALL operation in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. As with the STOR cycle, a transition must occur on any one control pin to cause a RCALL, preventing inadvertent multi-triggering. On power up, once V CC exceeds 4.25V, a RCALL cycle is automatically initiated. Due to this automatic RCALL, SRAM operation cannot commence until t RSTOR after V CC exceeds 4.25V. POR-UP RCALL During power up, or after any low-power condition (V CC < 3.0V), an internal RCALL request will be latched. hen V CC once again exceeds 4.25V, a RCALL cycle will automatically be initiated and will take t RSTOR to complete. March Document Control # ML0001 rev 0.2

10 If the is in a RIT state at the end of power-up RCALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between and system V CC or between and system V CC. HARDAR PROTCT The offers two levels of protection to suppress inadvertent STOR cycles. If the control signals (,, and ) remain in the STOR condition at the end of a STOR cycle, a second STOR cycle will not be started. The STOR (or RCALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, STORs are inhibited when V CC is below 4.0V, protecting against inadvertent STORs. LO AVRA ACTIV POR The draws significantly less current when it is cycled at times longer than 55ns. Figure 2 shows the relationship between I CC and RAD cycle time. orst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, V CC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for RIT cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of RADs to RITs; 5) the operating temperature; 6) the V CC level; and 7) I/ O loading Average Active Current (ma) TTL Average Active Current (ma) TTL CMOS 0 CMOS Cycle Time (ns) Cycle Time (ns) Figure 2: I CC (max) Reads Figure 3: I CC (max) rites March Document Control # ML0001 rev 0.2

11 ORDRIN INFORMATION - F 45 I Temperature Range Blank = Commercial (0 to 70 C) I = Industrial ( 40 to 85 C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Lead Finish Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin) Package = Plastic 28-pin 600 mil DIP March Document Control # ML0001 rev 0.2

12 Document Revision History Revision Date Summary 0.0 December 2002 Replaced 30 nsec device with 25 nsec device. 0.1 September 2003 Added lead-free lead finish 0.2 February 2006 Marked as Obsolete, Not recommended for new design.

STK25CA8 128K x 8 AutoStore nvsram QuantumTrap CMOS Nonvolatile Static RAM Module

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