Datasheet for ADTEC DDR4 Simplified Version

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1 Datasheet for ADTEC DDR4 Simplified Version Note: ADTEC Corporation reserves the right to change products and specifications without notice. This document and any information herein cannot not be reproduced without prior permission from ADTEC. The simplified version contained herein is presented only as brief introduction of products. Please ask ADTEC Sales for the latest detailed document. 1

2 Features DDR4 functionality and operations supported as defined in the component data sheet ADTEC original enhancements into JEDEC designs to bring the best out of DDR4 Fast data transfer rates: PC or PC V DD = 1.20V (NOM) V PP = 2.5V (NOM) Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Low-power auto self refresh (LPASR) Data bus inversion (DBI) for data bus On-die V REF DQ generation and calibration Single-rank Onboard I2C serial presence-detect (SPD) EEPROM Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts and chamfer the corners Halogen-free Fly-by topology Terminated control command and address bus Key Timing Parameters Industry Nomenclature Data Rate (MT/s) CL18 CL17 CL16 CL15 CL14 CL13 CL12 CL11 CL10 CL9 trcd (ns) trp (ns) trc (ns) PC PC Note: 1. The memory supports t AA = t RC = t RP = 13.50ns with CL9 operation. 2

3 Module Dimensions ( SO-DIMM ) 260-Pin DDR4 SODIMM Center Line ±0.10 (DATUM A) 4.00 ± COMPONENT AREA (FRONT) ±0.10 Border of Component Area x 4.00 MIN 2x 5.10 MIN PIN 1 PIN (1.675) (1.425) ± (DATUM A) (1.675) (1.425) x 3.00 MIN PIN 2 PIN 260 2x Φ1.80±0.10 2x 1.75 COMPONENT AREA (BACK) (4x R0.65) 4x R3.00 MIN 2x 1.10 MIN FLAT SURFACE 4x R0.75 MAX 4x 2.00 MIN # (#) : BASIC : REFERENCE 3

4 Module Dimensions ( UDIMM ) 288-Pin DDR4 UDIMM Center Line (DATUM A) DETAIL W COMPONENT AREA (FRONT) Border of Component Area 2x 4.00 MIN (0.50) PIN PIN (2 x 3.35) 1.40 ±0.10 (10.20) (10.20) PIN PIN 288 (2 x 3.35) 2x R0.80 MAX (8x R0.65) COMPONENT AREA (BACK) DETAIL W (DATUM A) 8x 1.45 MIN FLAT SURFACE 4x x 2.50 MIN 2x R x x x x (0.50) 4x 2.80 MIN # (#) : BASIC : REFERENCE 4

5 Electrical Specification < Absolute Maximum DC Rating > Symbol Parameter Min. Max. Units V DD V DD supply voltage relative to V SS V V PP Word line supply voltage V V IN, V OUT Voltage on any pins relative to V SS V T STG Storage Temperature < DC Operating Condition > Symbol Parameter Min. Typ. Max. Units Notes V DD Supply voltage V 1,2,3,4 V PP Word line supply voltage V 4,5 V REF CA V TT I DD I/O voltage reference for command/address Termination reference voltage Input leakage current; any input other than ZQ 0.49 x V DD 0.50 x V DD 0.51 x V DD V x V DD - 20mV 0.50 x V DD 0.51 x V DD + 20mV V μa 8,9 I DQ DQ leakage; 0V < V IN < V DD μa 8 I ZQ ZQ leakage current μa 8,10 I OZ PD Output leakage current; V OUT = V DD ; DQ is disabled μa I OZ PU Output leakage current; V OUT =V SS ; DQ and ODT are disabled μa I REF CA V REF CA leakage; V REF CA = V DD / μa 8 Note: 1. V DD and V DDQ are tied to each other in the module. 2. V DD slew rate between 300mV and 80% of its minimum shall be between V/ms and 600 V/ms, 20 MHz band-limited measurement. 3. V DD ramp time from 300mV to V DD Min. shall be no longer than 200ms. 4. A stable valid voltage level is a set DC level (0 Hz to 250 KHz) and must be no less than its minimum and no greater than its maximum. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is final. AC noise of ±60mV (greater than 250 KHz) is allowed provided the noise doesn't alter supply voltage to less than its minimum or greater than its maximum. 5. V PP must be greater than or equal to V DD at all times. 6. V REF CA must not be greater than 0.6 x V DD. When V DD is less than 500mV, V REF may be less than or equal to 300mV. 7. V TT termination voltages in excess of the specification limit adversely affect the voltage margins of command and address signals and reduce timing margins. 8. Need to multiply by the number of DRAM die on the module. 9. 0V < V IN < 1.1V 10. Tied to ground via 240Ω resister. Not connected to edge connector. 5

6 V REF DQ Supply and Calibration Ranges The device internally generates its own V REF DQ. DRAM internal V REF DQ specification parameters: voltage range, step size, V REF step time, V REF full step time, and V REF valid level are used to help provide estimated values for the internal V REF DQ and are not pass/fail limits. The voltage operating range specifies the minimum required range for DDR4 devices. The minimum range is defined by V REF DQ Min and V REF DQ Max. A calibration sequence should be performed by the DRAM controller to adjust V REF DQ and optimize the timing and voltage margin of the DRAM data input receivers. < V REF DQ Specification > Symbol Parameter Min. Typ. Max. Units Notes V REF DQ R1 Range 1 V REF DQ operating points 60% - 92% V DD 1,2 V REF DQ R2 Range 2 V REF DQ operating points NA NA NA V DD 2 V REF _step V REF step size 0.5% 0.65% 0.8% V DD 3 V REF _set_tol V REF set tolerance % 0% 1.625% V DD 4,5,6-0.15% 0% 0.15% V DD 4,7,8 V REF _time V REF valid tolerance ns 9,10,11 Note: 1. V REF (DC) voltage is referenced to V DD (DC). V DD (DC) is 1.2V. 2. DRAM range 1 or range 2 is set by the MRS6[Bit 6]. Only Range 1 should be selected for DIMM use. 3. V REF step size increment/decrement range. V REF at DC level. 4. V REF new = V REF old ±n V REF _step; n = number of steps. If increment, use +, if decrement, use For n >4, the minimum value of V REF setting tolerance = V REF new % V DD. The maximum value of V REF setting tolerance = V REF new % V DD. 6. Measured by recording the MIN and MAX values of the V REF output over the range, drawing a straight line between those points, and comparing all other V REF output settings to that line. 7. For n 4, the minimum value of V REF setting tolerance = V REF new % V DD. The maximum value of V REF setting tolerance = V REF new % V DD. 8. Measured by recording the MIN and MAX values of the V REF output across four consecutive steps (n = 4), drawing a straight line between those points, and comparing all V REF output settings to that line. 9. Time from MRS command to increment or decrement one step size for V REF. 10. Time from MRS command to increment or decrement more than one step size up to the full range of V REF. 11. If the V REF monitor is enabled, V REF must be derated by +10ns if DQ bus load is 0pF and an additional +15ns/pF of DQ bus loading. 6

7 V REF DQ Ranges MR6[6] selects range 1 (60% to 92.5% of V DD ) or range 2 (45% to 77.5% of V DD ), and MR6[5:0] sets the V REF DQ level, as listed in the following table. The values in MR6[6:0] will update the V DD range and level independent of MR6[7] setting. It is recommended MR6[7] be enabled when changing the settings in MR6[6:0], and it is highly recommended MR6[7] be enabled when changing the settings in MR6[6:0] multiple times during a calibration routine. < V REF DQ Range and Levels Table > Note: DRAM range 1 or range 2 is set by the MRS6[6]. Due to the DIMM use, only range 1 is in the following table. MR6[5:0] MR6[6] = 0 (Range 1) % % % % % % % % % % % % % % % % % % % % % % % % % % MR6[5:0] MR6[6] = 0 (Range 1) % % % % % % % % % % % % % % % % % % % % % % % % % to are reserved 7

8 SPD EEPROM Operating Conditions < DC Operating Condition for EEPROM > Parameter Symbol Min Max Units Notes Supply Voltage for EEPROM V DD SPD V 1 Operating Current for EEPROM I DD_EE ma 2 Operating Current for Temperature Sensor (TS) I DD_TS ma 3 Shutdown Current I SHDN - 10 μa 4 I/O Pin Leakage Current I LKG - 2 μa 4 Power On Reset (POR) for EEPROM V POR V Input High Voltage for EEPROM V IH 0.7 x V DD SPD - V Input Low Voltage for EEPROM V IL x V DD SPD V Output Low Voltage for TS & SDA V OL V 5 TS Accuracy Note: 1. Typical operational voltage for DDR4 is 2.5V. 2. EEPROM write mode; TS is in Shutdown Mode. 3. EEPROM is Inactive. 4. EEPROM and I2C Bus are Inactive. 5. IOL = 3 ma 6. It is the Grade B in the JC TSE2002B3. < Serial Interface Timing for EEPROM > Parameter Symbol Min Max Units Serial Port Frequency khz Clock Low Period t LOW ns Clock High Period t HIGH ns SDA Rise Time t R ns SDA Fall Time t F ns Input Data Setup time t DSU 50 - ns Output Data Hold time t DHD ns Start Condition Setup Time t SU:STA ns Start Condition Hold Time t HD:STA ns Stop Condition Setup Time t SU:STO ns Bus Idle t B:FREE ns Write Cycle time t WR - 5 ms 8

9 SPD EEPROM description DDR4 SDRAM modules incorporate serial presence detect (SPD). The SPD data is stored in a 512-byte JEDEC JC-42.4-compliant EEPROM. The SPD content is aligned with these blocks as shown in the table below Block Range Description h 07Fh Configuration and DRAM parameters h 0FFh Module-specific parameters h 13Fh Reserved; all bytes coded as 00h h 17Fh Manufacturing information h 1FFh End-user programmable The first 384 bytes of data is complied with JEDEC JC-45, Serial Presence Detect (SPD) for DDR4 SDRAM Modules. The remaining 128 bytes are open for customer use. JEDEC JC-42.4-compliant EEPROM operates as a slave device in the I2C bus protocol, and transfers up to 1MHz at nominal 2.5V power supply. Addressing Specifications Parameter 16GB 8GB 4GB 2 Ranks 1Rank 2Ranks 1Rank Row address 64K A[15:0] 64K A[15:0] 32K A[14:0] 32K A[14:0] Column address 1K A[9:0] 1K A[9:0] 1K A[9:0] 1K A[9:0] Device bank group address 4 BG[1:0] 4 BG[1:0] 4 BG[1:0] 4 BG[1:0] Device bank address per group 4 BA[1:0] 4 BA[1:0] 4 BA[1:0] 4 BA[1:0] Device configuration < Addressing tables by capacities > 8Gb (1 Gig x 8), 16 banks 8Gb (1 Gig x 8), 16 banks 4Gb (512 Meg x 8), 16 banks 4Gb (512 Meg x 8), 16 banks Module rank address 2x -S[1:0] 1x -S0 2x -S[1:0] 1x -S0 Note: Ask our Sales for specific product code for each module. 9

10 Address Mirroring DDR4 Multi-Rank modules often have mirrored address wiring designs to achieve optimum routing of the address bus. The mirrored and nor-mirrored address bus will be wired as the below table. Edge Connector Pin DRAM Pin (Non-Mirrored) DRAM Pin (Mirrored) A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A4 A4 A4 A3 A5 A5 A6 A6 A6 A5 A7 A7 A8 A8 A8 A7 A9 A9 A9 A10 A10 A10 A11 A11 A13 A12 A12 A12 A13 A13 A11 A14 A14 A14 A15 A15 A15 A16 A16 A16 A17 A17 A17 BA0 BA0 BA1 BA1 BA1 BA0 BG0 BG0 BG0 BG1 BG1 BG1 Note: Mirrored address is indicated in SPD Byte

11 Initialization and RESET Procedure To ensure proper device function, the power-up and reset initialization default mode register settings values are followings: Gear-down mode (MR3 A[3]): 0 = 1/2 rate Per-DRAM addressability (MR3 A[4]): 0 = disable Maximum power-saving mode (MR4 A[1]): 0 = disable CS to command/address latency (MR4 A[8:6]): 000 = disable CA parity latency mode (MR5 A[2:0]): 000 = disable Power-Up and Initialization Sequence The following sequence is required for power-up and initialization: 1. Apply power (#RESET should be maintained below 0.2 V DD while supplies ramp up; all other inputs may be undefined). When supplies have ramped to a valid stable level, #RESET must be maintained below 0.2 V DD for a minimum of t PW_RESET_L must be maintained below 0.2 V DD for a minimum of 700μs. CKE is pulled LOW anytime before #RESET is de-asserted (minimum 10ns). The power voltage ramp time between 300mV to V DD Min. must be no greater than 200ms. V PP must ramp at the same time or before V DD, and V PP must be equal to or higher than V DD at all times. After V DD has ramped and reached the stable level, the initialization sequence must be started within 64ms. During power-up, the following conditions may exist and must be met: Apply V PP without any slope reversal before or at the same time as V DD. Apply V DD without any slope reversal before or at the same time as V TT and V REF CA. V TT is limited to 0.76V Max. when the power ramp is complete. V REF CA tracks V DD /2. 2. After #RESET is de-asserted, wait for another 500μs until CKE becomes active. During this time, the device will start internal state initialization; this will be done independently of external clocks. A reasonable attempt was made in the design to power up with the following default MR settings: gear-down mode (MR3 A[3]): 0 = 1/2 rate per-dram addressability (MR3 A[4]): 0 = disable maximum power-down (MR4 A[1]): 0 = disable CS to command/address latency (MR4 A[8:6]): 000 = disable CA parity latency mode (MR5 A[2:0]): 000 = disable However, it should be assumed that at power up the MR settings are undefined and should be programmed as shown in the top of this chapter. 3. Clocks (CK+, CK-) need to be started and stabilized for at least 10ns or 5x t CK (whichever is larger) before CKE goes active. Because CKE is a synchronous signal, the corresponding setup time to clock ( t IS) must be met. Also, a DESELECT command must be registered (with t IS setup time to clock) at clock edge Td. After the CKE is registered HIGH after #RESET, CKE needs to be continuously registered HIGH until the initialization sequence is finished, including expiration of t DLLK and t ZQINIT. 11

12 Power-Up and Initialization Sequence (Continued) 4. The SDRAM keeps its ODT in High-Z state as long as #RESET is asserted. Further, it keeps its ODT in High-Z state after #RESET de-assertion until CKE is registered HIGH. The ODT input signal may be in an undefined state until t IS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be statically held either LOW or HIGH. If R TT (Nom) is to be enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power-up initialization sequence is finished, including the expiration of t DLLK and t ZQINIT. 5. After CKE is registered HIGH, wait a minimum of #RESET CKE EXIT time, t XPR, before issuing the first MRS command to load mode register ( t XPR = Max ( t XS; 5x t CK). 6. Issue MRS command to load MR3 with all application settings, wait t MRD. 7. Issue MRS command to load MR6 with all application settings, wait t MRD. 8. Issue MRS command to load MR5 with all application settings, wait t MRD. 9. Issue MRS command to load MR4 with all application settings, wait t MRD. 10.Issue MRS command to load MR2 with all application settings, wait t MRD. 11.Issue MRS command to load MR1 with all application settings, wait t MRD. 12.Issue MRS command to load MR0 with all application settings, wait t MOD. 13.Issue a ZQCL command to start ZQ calibration. 14.Wait for t DLLK and t ZQINIT to complete. 15.The device will be ready for normal operation. A stable valid V DD level is a set DC level (0 Hz to 20 MHz) and must be no less than V DD Min. and no greater than V DD Max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is stable. AC noise of ±60mV (greater than 20 MHz) is allowed on V DD provided the noise doesn't alter V DD to less than V DD Min. or greater than V DD Max. A stable valid V PP level is a set DC level (0 Hz to 20 MHz) and must be no less than V PP Min. and no greater than V PP Max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is stable. AC noise of ±120mV (greater than 20 MHz) is allowed on V PP provided the noise doesn't alter V PP to less than V PP Min. or greater than V PP Max. 12

13 < Chart 1: Power-Up and Initialization Timing Chart > Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK+,CK- t CKSRX V PP V DD t PW_RESET_L T = 500μs #RESET T MIN= 10ns t IS CKE VALID t DLLK t IS t t t t t XPR MRD MRD MRD MOD t ZQinit COMMAND Note 1 MRS MRS MRS MRS ZQCL Note 1 VALID BA, BG t IS MRx MRx MRx MRx VALID t IS ODT Static LOW in case R TT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID R TT = Don t Care = Time Break Note: 1. From time point Td until Tk, DES commands must be applied between MRS and ZQCL commands. 2. MRS commands must be issued to all mode registers that have defined settings. Symbol t CKSRX Parameter Valid Clock Requirement before Self Refresh Exit (SRX), Power-Down Exit (PDX), or Reset Exit DDR DDR DDR DDR Min Max Min Max Min Max Min Max Min = greater of 5xCK or 10ns; Max = N/A t DLLK DLL locking time CK t IS CTRL, CMD, ADDR setup to CK, /CK Refer to the table of the command and address timing table. t MOD Mode Register Set command update delay Min = greater of 24xCK or 15ns; Max = N/A t MRD Mode Register Set command cycle time CK t PW_RESET_L RESET pulse width during power-up µs t XPR Exit Reset from CKE HIGH to a valid command Min = greater of 5xCK or ( t RFC Min + 10ns); Max = N/A t ZQinit Power-up and RESET calibration time CK Units 13

14 CK+,CK- RESET Initialization with Stable Power Sequence The following sequence is required for #RESET at no power interruption initialization: 1. Assert #RESET below 0.2 V DD any time reset is needed (all other inputs may be undefined). #RESET must be maintained for a minimum of 100ns. CKE is pulled LOW before #RESET is de-asserted (minimum time 10ns). 2. Follow Steps 2 to 7 in the Power-Up and Initialization Sequence. When the reset sequence is complete, all counters except the refresh counters have been reset and the device is ready for normal operation. < Chart 2: RESET Procedure at Power Stable Condition > Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk t CKSRX V DD t PW_RESET_L T = 500μs #RESET TMIN = 10ns t IS CKE VALID t DLLK t IS t XPR t MRD t MRD t MRD t MOD t ZQinit COMMAND Note 1 MRS MRS MRS MRS ZQCL Note 1 VALID BA, BG MRx MRx MRx MRx VALID t IS t IS ODT Static LOW in case R TT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID R TT Note: = Don t Care = Time Break 1. From time point Td until Tk, DES commands must be applied between MRS and ZQCL commands. 2. MRS commands must be issued to all mode registers that have defined settings. Uncontrolled Power-Down Sequence In the event of an uncontrolled ramping down of V PP supply, V PP is allowed to be less than V DD provided the following conditions are met: A. V PP and V DD are ramping down (as part of turning off) from normal operating levels. B. The amount that V PP may be less than V DD is less than or equal to 500mV. C. The time V PP may be less than V DD is 10ms per occurrence with a total accumulated time in this state 100ms. D. The time V PP may be less than 2.0V and above V SS while turning off is 15ms per occurrence with a total accumulated time in this state 150ms. 14

15 Electrical Characteristics Overshoot and Undershoot Specifications Address, Command, and Control Overshoot and Undershoot Specifications < ADDR, CMD, CNTL Overshoot and Undershoot Specifications > Parameter DDR DDR DDR DDR Unit Area A: Maximum peak amplitude above V DD absolute MAX V Area B: Amplitude allowed between V DD and V DD absolute MAX V Area C: Maximum peak amplitude allowed for undershoot below V SS V Area A maximum overshoot area per 1 t CK V/ns Area B maximum overshoot area per 1 t CK V/ns Area C maximum undershoot area per 1 t CK V/ns < Figure 15: ADDR, CMD, CNTL Overshoot and Undershoot Definition > Absolute MAX overshoot V DD absolute MAX A B Overshoot area above VDD absolute MAX Overshoot area below V DD absolute MAX and above V DD MAX Voltage (V) V DD V SS 1 t CK C Undershoot area below V SS Clock Overshoot and Undershoot Specifications < CK Overshoot and Undershoot Specifications > Parameter DDR DDR DDR DDR Unit Area A: Maximum peak amplitude above V DD absolute MAX V Area B: Amplitude allowed between V DD and V DD absolute MAX V Area C: Maximum peak amplitude allowed for undershoot below V SS V Area A maximum overshoot area per 1UI V/ns Area B maximum overshoot area per 1UI V/ns Area C maximum undershoot area per 1UI V/ns 15

16 < Figure 16: CK Overshoot and Undershoot Definition > Absolute MAX overshoot V DD absolute MAX A B Overshoot area above VDD absolute MAX Overshoot area below V DD absolute MAX and above V DD MAX Voltage (V) V DD V SS 1UI C Undershoot area below V SS Data, Strobe, and Mask Overshoot and Undershoot Specifications < DM/DBI, DQ, DQS Overshoot and Undershoot Specifications > Parameter DDR DDR DDR DDR Unit Area A: Maximum peak amplitude above V DD absolute MAX V Area B: Amplitude allowed between V DD and V DD absolute MAX V Area C: Maximum peak amplitude allowed for undershoot below V SS V Area D: Maximum peak amplitude below V SS absolute MIN V Area A maximum overshoot area per 1UI V/ns Area B maximum overshoot area per 1UI V/ns Area C maximum undershoot area per 1UI V/ns Area D maximum undershoot area per 1UI V/ns < Figure 17: DM/DBI, DQ, DQS Overshoot and Undershoot Definition > Absolute MAX overshoot V DD absolute MAX A B Overshoot area above VDD absolute MAX Overshoot area below V DD absolute MAX and above V DD MAX Voltage (V) V DD V SS 1UI V SS absolute MIN C D Undershoot area below V SS MIN and above V SS absolute MIN Undershoot area below V SS absolute MIN Absolute MIN undershoot 16

1.35V DDR3L SDRAM Addendum

1.35V DDR3L SDRAM Addendum 1.35R3L SDRAM Addendum MT41K256M4 32 Meg x 4 x 8 banks MT41K128M8 16 Meg x 8 x 8 banks MT41K64M16 8 Meg x 16 x 8 banks 1Gb: x4, x8, x16 DDR3L SDRAM Addendum Description Description DDR3L SDRAM 1.35V is